JPH0481392B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a high-definition television receiver, and particularly relates to a high-definition television receiver suitable for receiving a high-definition television signal on which an energy diffusion signal is superimposed. .

[Background of the invention]

MUSE (Multiple Sub-Nyquist
Sampling Encoding) method has been proposed.
(Reference: Ninomiya et al. 2, "Satellite Single Channel Transmission System for High-Definition Television (MUSE)", Television Society Technical Report TEBS95-2) This 12 GHz band satellite broadcasting requires energy dispersion. (Reference: Japan Broadcasting Corporation, “Broadcasting Sanitation Technology”, published by Japan Broadcasting Publishing Association, p. 46) This prevents the energy of the FM modulated signal from concentrating on a single frequency and causing interference elsewhere. It is something.

FIG. 1 shows the energy spread signal superimposed on the MUSE signal, and FIG. 2 shows the correction signal for the spread signal.
Since there are audio signals, frame pulses, etc. during the vertical planking period, the spread signal is not superimposed. The transmitter superimposes the waveform shown in Fig. 1 on the video signal, and the receiver superimposes the waveform shown in Fig. 2 to obtain the original video signal.

FIG. 3 shows the control signal format in V-planking of the MUSE signal. According to the standard, spread signals are not superimposed on line numbers 1 to 47 and 563 to 610.
In order to always correctly generate an H-period energy diffusion signal, it is preferable to generate it based on an internal horizontal pulse having a flywheel effect. but,
In this way, until the system is properly phase synchronized, the correction signal of the spread signal will be
This is also done in 605-606, and the frame pulse is modulated, making detection of the frame pulse difficult in a weak electric field.

[Purpose of the invention]

An object of the present invention is to provide a high-definition television receiver that can stably perform phase locking of a high-definition television signal on which an energy spread signal is superimposed even at a low S/N ratio.

[Summary of the invention]

In order to achieve the above object, the present invention has a configuration in which no correction signal is superimposed before phase locking, and synchronization information can be stably extracted even at a low S/N.

In other words, if the correction signal shown in Fig. 2 is superimposed before the phase lock is applied, the vertical planking period in which the spread signal shown in Fig. 1 is not superimposed will become different from the original signal as shown in Fig. 4. It becomes an ivy signal. Low S/N showing the original signal in Figure 5
In this case, it is particularly difficult to stably extract synchronization information from the waveform shown in FIG. Therefore, in the present invention, before phase locking, superimposition of the correction signal is stopped and the waveform during the vertical blanking period is set to the waveform shown in FIG. 5, so that synchronization information can be stably extracted even with a low S/N.

[Embodiments of the invention]

Examples of the present invention will be described below.

FIG. 6 shows a part of a high-definition television receiver to which the present invention is applied. In the figure, 1 is the MUSE signal input terminal, 2 is the A/D converter, 3 is the adder, 4 is the synchronization circuit, 5 is the phase lock discrimination circuit, 6 is the gate circuit, and 7 is the correction circuit. signal generator, 8
The MUSE signal processing circuit is shown. 12G from input terminal 1
A baseband MUSE signal demodulated from the Hz band is input. This is converted into a digital signal by an A/D converter 2. A synchronization circuit 4 locks the phase using a PLL circuit (Phase Lock Loop) or the like.
A phase lock discriminating circuit 5 determines that the lock is established, and a gate circuit 6 is opened only when the lock is established. Then, the adder 3 adds the correction signal to the MUSE signal. The MUSE signal processing circuit 8 is an A/D
The MUSE signal digitized from converter 2 is
It receives control pulses such as clock pulses, subsampling pulses, and block control signals from the synchronization circuit 4, and performs known processing. The phase lock determination circuit 5 can be constructed using, for example, a phase comparator.

FIG. 7 shows an example of the phase lock discriminating circuit 5.
9 is an input terminal for an external vertical synchronizing pulse from the synchronizing circuit 4, 10 is an input terminal for an internal vertical synchronizing pulse from the synchronizing circuit 4, 11 is a phase comparator, 12 is a pulse generator, and 13 is a phase lock. The output terminal of the discrimination circuit is shown. FIG. 8 shows the input/output characteristics of the pulse generator 12. In the figure, Vo indicates the output voltage of the phase comparator when locked. As a result, Vb is output from the terminal 13 when the phase is locked, and Va is output when the phase is not locked.

FIG. 9 shows another example of the phase lock discriminating circuit. In the figure, 14 indicates an external horizontal synchronizing pulse input terminal from the synchronizing circuit 4, and 15 indicates an input terminal for internal horizontal synchronizing pulses from the synchronizing circuit 4. The basic operation is the same as that shown in FIG. The discrimination circuit of FIG. 7 discriminates only the lock of the vertical synchronizing signal, and the discrimination circuit of FIG. 9 discriminates the lock of the horizontal and vertical synchronizing signals.

Next, examples of partial configurations of the synchronous circuit 4 are shown in FIGS. 10 and 11. The system shown in FIG. 10 uses a frame pulse reset method, and the system shown in FIG. 11 uses a frame pulse phase comparison method. In Figures 10 and 11, 1
6 is a terminal connected to the A/D converter 2, 17 is an internal horizontal synchronizing pulse terminal connected to the correction signal generator 7, 18 is a voltage controlled oscillator VCO, 1
9 is a horizontal frequency divider circuit, 20 and 26 are phase comparators
21 is a vertical frequency divider circuit, 22 is a frame pulse detection circuit, 23 is a MUSE signal input terminal, 24 is an internal vertical synchronization pulse output terminal, 25 is a
27 represents an external vertical synchronization pulse output terminal and an adder.

In FIG. 10, frame pulse detection circuit 2
2, the frame pulse is detected and the frequency dividing circuit 21 is reset. From the frequency divider circuit 21, the horizontal frequency divider circuit 1
9 is reset, and a phase comparator 20 compares the phases of the internal horizontal synchronizing pulse and the external horizontal synchronizing pulse.
The phase comparator 20 controls the VCO 18. 11th
In the figure, a phase comparator 26 compares the phases of the external vertical synchronizing pulse and the internal vertical synchronizing pulse. The outputs of the phase comparators 26 and 20 are added by an adder 27,
Controls VCO18.

According to the embodiment shown in FIG. 6, since the diffusion correction signal is not superimposed before the phase lock, the electric field is weak and the S/N is low.
Stable phase lock can be achieved even when

In the embodiment shown in FIG. 6, the addition of the correction signals is performed in an analog manner, but if it is performed digitally, instability due to variations in elements is eliminated and reliability is increased. FIG. 12 shows another embodiment of the present invention,
An example of the configuration for digital addition is shown. The effect is the same as the embodiment of FIG.

〔Effect of the invention〕

According to the present invention, since no correction signal is applied during the vertical blanking period, the vertical synchronization information can be used at a low S/N.
Since it can be stably extracted even when the phase lock is in use, it is effective in improving the reliability and quick response of the phase lock.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the energy spread signal superimposed on the MUSE signal, Figure 2 is a diagram showing the correction signal for the spread signal, Figure 3 is a diagram showing the control signal in vertical blanking of MUSE, Figure 4, FIG. 5 is a diagram showing signals during the vertical blanking period, FIGS. 6 and 12 are diagrams showing an embodiment of the present invention, and FIG.
9 are diagrams showing a specific example of a phase lock discriminating circuit, FIG. 8 is a diagram showing the input/output characteristics of a pulse generator, and FIGS. 10 and 11 are specific examples of a portion of a synchronous circuit related to the present invention. FIG. 3... Adder, 4... Synchronous circuit, 5... Phase lock discrimination circuit, 6... Gate circuit, 7... Correction signal generator, 11, 20, 26... Phase comparator, 1
8...VCO, 19, 21... Frequency dividing circuit.

Claims (1)

[Claims] 1. MUSE (Multiple Sub-Nyquist Sampling)
In a high-definition television receiver that receives and demodulates a high-definition television signal superimposed with an energy spread signal transmitted by the encoding method, a VCO that oscillates in phase synchronization with the horizontal synchronization of the transmitted high-definition television signal; means for generating a correction signal for the energy spread signal; the correction signal is phase-locked with a frame synchronization signal of the transmitted high-definition television signal and a frame synchronization signal created by frequency-dividing the output of the VCO; A high-definition television receiver characterized in that it comprises means for preventing superimposition on the high-definition television signal and for superimposing the signal upon phase lock.