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JPH0481724B2 - - Google Patents
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JPH0481724B2 - - Google Patents

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Publication number
JPH0481724B2
JPH0481724B2 JP60135419A JP13541985A JPH0481724B2 JP H0481724 B2 JPH0481724 B2 JP H0481724B2 JP 60135419 A JP60135419 A JP 60135419A JP 13541985 A JP13541985 A JP 13541985A JP H0481724 B2 JPH0481724 B2 JP H0481724B2
Authority
JP
Japan
Prior art keywords
scan line
soldering
inspection area
soldered
scans
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60135419A
Other languages
Japanese (ja)
Other versions
JPS61293658A (en
Inventor
Kazunari Yoshimura
Tomoharu Nakahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP13541985A priority Critical patent/JPS61293658A/en
Publication of JPS61293658A publication Critical patent/JPS61293658A/en
Publication of JPH0481724B2 publication Critical patent/JPH0481724B2/ja
Granted legal-status Critical Current

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  • Length Measuring Devices By Optical Means (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 (技術分野) 本発明は電子部品等が実装された印刷配線基板
(プリント基板)の半田付け面における近接・ブ
リツジ・チツプ部品ずれ等の不良な実装状態を検
査する半田付け外観検査方法に関する。
Detailed Description of the Invention (Technical Field) The present invention is a soldering method for inspecting the soldering surface of a printed wiring board (printed circuit board) on which electronic components, etc. are mounted, for poor mounting conditions such as proximity, bridging, and chip component misalignment. This invention relates to a mounting appearance inspection method.

(背景技術) 例えばチツプ部品の如き電子部品が実装された
印刷配線基板の実装半田付け状態を自動的に検査
する場合、従来においては、第4図に示すように
チツプ部品11の半田付け部12の周囲に検査領
域Sを設定し、ITVカメラ等により撮像して画
像処理を行い、検査領域Sに半田付け部12が入
り込まなければ正常であると判定する方法があつ
た。しかしなが、らこの方法では、高密度実装の
場合において複数の半田付け部間の距離が短くな
ることにより適切な位置に検査領域を設定するの
が困難となり、仮に設定できた場合においても、
許容できるような少量のチツプ部品のずれ等でも
検査領域に半田付け部が入り込んでしまうため、
誤判定が多いという欠点があつた。
(Background Art) For example, when automatically inspecting the mounting soldering state of a printed wiring board on which electronic components such as chip components are mounted, conventionally, as shown in FIG. There is a method in which an inspection area S is set around the inspection area S, an image is taken with an ITV camera, etc., image processing is performed, and if the soldering part 12 does not enter the inspection area S, it is determined that the inspection area S is normal. However, with this method, in the case of high-density mounting, the distance between multiple soldering parts becomes short, making it difficult to set the inspection area at an appropriate position, and even if it is possible to set the inspection area,
Even a small amount of deviation of the chip component, which is acceptable, will cause the soldered part to enter the inspection area.
The drawback was that there were many false positives.

また、他の判定方法として第5図に示すように
正常に半田付けされた基準のチツプ部品11Sの
画像と検査対象となるチツプ部品11の画像との
差(斜線部aは差の部分、白部bは共通部分であ
る。)をとり、その差の部分aの面積等から実装
状態矢や半田付け状態を検査する方法がある。し
かしながら、この方法では、第6図に示すように
隣り合う2個のチツプ部品11A,11Bが互い
に近ずく方向にずれた場合、個々のチツプ部品の
ずれ量は許容値であつても実際にはき近接・ブリ
ツジ等が発生していることが多く、誤判定をする
ことが多かつた。また、単品のチツプ部品ずれに
あつては、許容値を越えてずれていても半田付け
が正常に行われていれば不良と判定する必要がな
いことが多く、ずれ量限界レベルを決定しにくい
という欠点があつた。
In addition, as another determination method, as shown in FIG. There is a method of inspecting the mounting state and soldering state based on the area of part a, which is the difference between the two parts (part b is the common part). However, in this method, when two adjacent chip parts 11A and 11B are shifted in a direction toward each other as shown in FIG. Errors such as close proximity and bridges often occurred, resulting in erroneous judgments. In addition, when it comes to misalignment of a single chip component, even if the misalignment exceeds the allowable value, it is often not necessary to judge it as defective if the soldering is done normally, making it difficult to determine the limit level of misalignment. There was a drawback.

(発明の目的) 本発明は上述の技術的課題を解決し、実装部品
ずれや半田付け状態を高精度で、かつ自動的に検
査することができる半田付け外観検査方法を提供
することを目的とする。
(Objective of the Invention) An object of the present invention is to solve the above-mentioned technical problems and provide a soldering appearance inspection method that can accurately and automatically inspect the misalignment of mounted components and the soldering condition. do.

(発明の開示) 以下、実施例を示す図面に沿つて本発明を詳述
する。なお、以下においてはチツプ部品を例にと
つて説明するが、その他の電子部品であつても差
し支えないことは言うまでもない。
(Disclosure of the Invention) The present invention will be described in detail below with reference to the drawings showing embodiments. Note that although chip parts will be explained below as an example, it goes without saying that other electronic parts may also be used.

第1図は本発明を具体化した検査装置の一実施
例を示す構成図である。図において、11は印刷
配線基板10上に実装半田付けされたチツプ部品
であり、周囲から拡散照明6により照明され、上
方からITVカメラ(工業用テレビカメラ)1に
より撮像が行われるようになつている。ITVカ
メラ1の撮像信号は二値化処理部2において半田
付け部が白く出る閾値レベルで画素毎に二値化さ
れると共に、半田付け部以外は黒くなるようなノ
イズ処理が行われ、膨張処理部3に与えられる。
膨張処理部3は本発明の特徴的な部分であり、二
値化された半田付け部の画像(ランド)を近接限
界距離の1/2だけ膨張するような処理を行う。次
いで、この膨張された二値化像はいつたんフレー
ムメモリ4で1フレーム分記憶され、このフレー
ムメモリ4上でスキヤンライン、検査領域を設定
し、輪郭線上を走査し、判定処理部5により隣り
合う半田付け部が接触していないかどうかを自動
的に検出することにより良否を判定するようにし
ている。
FIG. 1 is a configuration diagram showing an embodiment of an inspection apparatus embodying the present invention. In the figure, reference numeral 11 denotes a chip component mounted and soldered on a printed circuit board 10, which is illuminated by diffused lighting 6 from the surroundings and imaged by an ITV camera (industrial television camera) 1 from above. There is. The image signal of the ITV camera 1 is binarized for each pixel in the binarization processing unit 2 at a threshold level that makes the soldered part appear white, and also undergoes noise processing so that the parts other than the soldered part become black, and is subjected to expansion processing. Part 3 is given.
The expansion processing unit 3 is a characteristic part of the present invention, and performs processing to expand the binarized image (land) of the soldered part by 1/2 of the proximity limit distance. Next, this expanded binarized image is stored for one frame in the frame memory 4, a scan line and an inspection area are set on the frame memory 4, the outline is scanned, and the judgment processing unit 5 selects the adjacent The quality is determined by automatically detecting whether or not the mating soldered parts are in contact.

そして、これらの処理により 別々の半田付け部が互いに近接限界距離以下
になつていないかどうか(近接) 半田付け部間がブリツジの状態になつていな
いかどうか(ブリツジ) チツプ部品がずれて実装されていないかどう
か(チツプ部品ずれ) 等の不良の実装状態を検出することができる。
Through these processes, we check whether separate soldered parts are closer to each other than the limit distance (proximity), whether there is a bridge between soldered parts (bridged), and whether chip components are mounted out of alignment. It is possible to detect defective mounting conditions such as chip component misalignment.

第2図は画像処理の様子をより詳細に示したも
のであり、イは二値化処理部2の出力である二値
化像、ロは膨張処理部3の出力である膨張二値化
像である。すなわち、撮像視野S内におけるチツ
プ部品11A,11Bの半田付け部の二値化像
(ランド)LAND1〜LAND4に近接限界距離の1/
2だけ膨張処理を行うことにより、膨張二値化像
(ランド)LAND1′,LAND2′,LAND4′を得る。
しかして、この膨張処理によりチツプ部品ずれ、
半田の近接、ブリツジ等が発生している場合、本
来別々の半田付け部が接続して見える。このよう
に異なるランドが膨張処理により接続したかどう
かを見ることにより、部品の実装状態や近接・ブ
リツジ等を検査することができる。なお、上述の
説明ではランドを白となるようにしたが、反転し
て黒にしても差し支えないことは言うまでもな
い。
Figure 2 shows the image processing in more detail, where A is the binarized image that is the output of the binarization processing section 2, and B is the dilated binarized image that is the output of the expansion processing section 3. It is. That is, the binarized images (lands) LAND 1 to LAND 4 of the soldered parts of the chip components 11A and 11B within the imaging field of view S are 1/1 of the proximity limit distance.
By performing dilation processing by 2, dilated binary images (lands) LAND 1 ′, LAND 2 ′, and LAND 4 ′ are obtained.
However, this expansion process causes chip parts to shift,
If solder is close to each other or bridging occurs, separate soldered parts will appear to be connected. By checking whether or not different lands are connected by the expansion process, it is possible to inspect the mounting state of components, proximity, bridging, etc. Note that in the above explanation, the land is set to be white, but it goes without saying that the land may be reversed and set to black.

次に膨張二値化像内で異なるランドが接続して
いるか否かを検出する方法を説明する。この場
合、第2図ロにS′で示すように方形の検査領域を
設定する。この検査領域S′は隣接する2つのラン
ドにかかり、かつそれぞれの半田付け部全体が含
まれることのないように設定すると共に、近接・
ブリツジ・チツプ部品ずれ等の不良が発生してい
ない状態において中央部のスキヤンラインLがラ
ンドに寸断されないような位置に設定する。
Next, a method for detecting whether different lands are connected in an expanded binarized image will be explained. In this case, a rectangular inspection area is set as shown by S' in FIG. This inspection area S' is set so that it spans two adjacent lands and does not include the entire soldering part of each land, and is
The scan line L at the center is set at a position where it will not be cut off by the land when no defects such as bridge/chip component displacement occur.

第3図は検査領域S′を拡大して示したものであ
り、イ,ロは近接・ブリツジ・チツプ部品ずれ等
の発生していない場合、ハは近接・ブリツジ・チ
ツプ部品ずれが発生している不良品の場合であ
る。具体的な手順としては、スキヤンラインL上
を始点P1から走査し、終点P2まで到着できたら
正常とする。すなわちイのような場合は始点P1
からストレートに終点P2まで走査が行われる。
従つて、この場合、極めて高速に検査を行うこと
ができる。また、ロのようにスキヤンラインL上
でランドの輪郭線と交わる場合には、その分岐点
P3から一方の側、例えば左側にランドの輪郭線
に沿つて走査を行い、検査領域S′のスキヤンライ
ンLと交わらない辺の点P4に達してしまつた場
合には分岐点P3に戻つて逆方向に走査をやり直
し、点P5でスキヤンラインLと合流した場合は
再びスキヤンラインL上を終点P2まで走査する。
この場合も終点P2に到達できたので正常とする。
一方、ハのように左右のランドが完全に接触して
いる場合には分岐点P6から左右どちらに走査し
てもスキヤンラインLには合流できず、検査領域
S′のスキヤンラインLと交わらない辺に到着して
しまうので、この場合は、近接・ブリツジ・チツ
プ部品ずれが発生しているものとして不良と判定
する。
Figure 3 is an enlarged view of the inspection area S', where A and B indicate that no close contact, bridging, or chip component misalignment has occurred, and C indicates that close proximity, bridge, or chip component shift has occurred. This is the case for defective products. The specific procedure is to scan the scan line L from the starting point P1 , and if it can reach the ending point P2 , it is considered normal. In other words, in a case like A, the starting point P 1
Scanning is performed straight from the point to the end point P2 .
Therefore, in this case, inspection can be performed extremely quickly. Also, if it intersects with the contour line of the land on the scan line L as shown in (b), the branch point
Scanning is performed from P3 to one side, for example to the left, along the contour of the land, and if it reaches a point P4 on the side that does not intersect with the scan line L of the inspection area S', it will scan to the branch point P3 . Returning and redoing the scan in the opposite direction, if the scan line L merges with the scan line L at point P5 , the scan line L is scanned again to the end point P2 .
In this case as well, the end point P2 was reached, so it is considered normal.
On the other hand, if the left and right lands are in complete contact as shown in C, no matter which direction you scan from branch point P6 to the left or right, you will not be able to join the scan line L, and the inspection area
Since it arrives at a side that does not intersect with the scan line L of S', in this case, it is determined that the chip is defective because proximity, bridge, or chip component displacement has occurred.

なお、第3図ロ,ハの処理はランドの輪郭線を
走査するためイに比して処理時間がかかり走査が
低速となるが、実際に検査する印刷配線基板は正
常な半田付け状態がほとんどであり、イの処理状
態が大半を占めるため、全体としての処理時間は
短く、極めて高速で検査を行えるものである。
Note that the processing shown in Figure 3 (b) and (c) scans the outline of the land, so it takes longer and the scanning speed is slower than in (a), but the printed wiring boards that are actually inspected are mostly in a normal soldered state. Since the processing state (a) occupies the majority, the overall processing time is short and inspection can be performed at extremely high speed.

(発明の効果) 以上のように本発明にあつては、実装半田付け
された印刷配線基板の半田付け部をテレビカメラ
により撮像し、その画像信号を画素毎に二値化
し、膨張処理を行い、1フレーム分記憶し、この
フレームメモリ上でスキヤンライン、検査領域を
設定し、輪郭線上を走査し、判定処理部において
近接・ブリツジ・チツプ部分ずれ等の不良を自動
的に検出する検査方法であつて、撮像して得た半
田付け部の画像を近接限界距離の半分だけを膨張
させ、この膨張させた画像において隣接する半田
付け部に検査領域を設定し、この検査領域内にス
キヤンラインを設定すること、およびスキヤンラ
インの始点、終点の関係で正常を判定することに
より、 () 高密度実装でも近接・ブリツジ・チツプ
部分ずれ等の検査が可能である。
(Effects of the Invention) As described above, in the present invention, the soldered portion of a printed wiring board that has been mounted and soldered is imaged by a television camera, the image signal is binarized for each pixel, and an expansion process is performed. This is an inspection method that stores one frame, sets a scan line and inspection area on this frame memory, scans the contour line, and automatically detects defects such as proximity, bridging, and chip misalignment in the judgment processing section. The image of the soldered part obtained by imaging is expanded by half of the proximity limit distance, an inspection area is set in the adjacent soldered area in this expanded image, and a scan line is drawn within this inspection area. By setting this and determining normality based on the relationship between the start and end points of the scan line, it is possible to inspect for proximity, bridging, chip misalignment, etc. even in high-density packaging.

() 近接限界距離を設定することによりずれ
の絶対量に左右されず、真の不良を検出するこ
とが可能である。
() By setting the proximity limit distance, it is possible to detect true defects regardless of the absolute amount of deviation.

() 正常な実装半田付け時は高速に検査を行
い、欠陥のある部分は細かく検査を行うため、
全体としての検査時間が短縮され、高速で検査
が行える。
() A high-speed inspection is performed for normal mounting soldering, and a detailed inspection is performed for defective parts.
The overall inspection time is shortened and inspection can be performed at high speed.

等の効果がある。There are other effects.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を具体化した検査装置の構成
図、第2図および第3図は画像処理の説明図、第
4図ないし第6図は従来の外観検査方法の説明図
である。 1……ITVカメラ、2……二値化処理部、3
……膨張処理部、4……フレームメモリ、5……
判定処理部、6……拡散照明、10……印刷配線
基板、11,11A,11B……チツプ部品、S
……撮像視野、S′……検査領域、LAND1
LAND4……二値化像、LAND1′,LAND2′,
LAND4′……膨張二値化像。
FIG. 1 is a block diagram of an inspection apparatus embodying the present invention, FIGS. 2 and 3 are explanatory diagrams of image processing, and FIGS. 4 to 6 are explanatory diagrams of a conventional appearance inspection method. 1...ITV camera, 2...Binarization processing unit, 3
...Expansion processing unit, 4...Frame memory, 5...
Judgment processing unit, 6... Diffuse illumination, 10... Printed wiring board, 11, 11A, 11B... Chip parts, S
...Imaging field of view, S'...Inspection area, LAND 1 ~
LAND 4 ...Binarized image, LAND 1 ′, LAND 2 ′,
LAND 4 ′...Dilated binarized image.

Claims (1)

【特許請求の範囲】 1 実装半田付けされた印刷配線基板の半田付け
部をテレビカメラにより撮像し、その画像信号を
画素毎に二値化し、膨張処理を行い、1フレーム
分記憶し、このフレームメモリ上でスキヤライ
ン、検査領域を設定し、輪郭線上を走査し、判定
処理部において近接・ブリツジ・チツプ部品ずれ
等の不良を自動的に検出する検査方法であつて、 撮像して得た半田付け部の画像を近接限界距離
の半分だけ膨張させ、この膨張させた画像におい
て隣接する2つの半田付け部に渡つて、かつそれ
ぞれの半田付け部全体か含まれることのないよう
に検査領域を設定すると共に、この検査領域内に
正常な半田付けであれば寸断されない位置にスキ
ヤンラインを設定し、スキヤンライン上を当該ス
キヤンラインの始点から走査し、半田付け部の輪
郭線と交わつた場合はその分岐点から輪郭線上を
走査し、再びスキヤンラインに合流した場合はス
キヤンライン上を走査し、同一分岐点からスキヤ
ンラインと交わらない検査領域の2辺の両方に到
達せずにスキヤンラインの終点まで走査できた場
合は正常と判定することを特徴とした半田付け外
観検査方法。
[Scope of Claims] 1. The soldered portion of a printed wiring board that has been mounted and soldered is imaged by a television camera, the image signal is binarized for each pixel, expansion processing is performed, one frame is stored, and this frame is This is an inspection method that sets a scan line and inspection area in memory, scans the contour line, and automatically detects defects such as proximity, bridging, and chip component misalignment in the judgment processing section. The image of the part is expanded by half of the proximity limit distance, and the inspection area is set in this expanded image so that it spans two adjacent soldering parts and does not include the entirety of each soldering part. At the same time, a scan line is set within this inspection area at a position that will not break if the soldering is normal, and the scan line is scanned from the start point of the scan line, and if it intersects with the outline of the soldered part, the branch is Scans on the contour line from a point, and if it joins the scan line again, scans on the scan line, and scans from the same branching point to the end point of the scan line without reaching both sides of the inspection area that do not intersect with the scan line. A soldering appearance inspection method characterized in that if soldering is completed, it is determined to be normal.
JP13541985A 1985-06-21 1985-06-21 Method for inspecting soldering appearance Granted JPS61293658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13541985A JPS61293658A (en) 1985-06-21 1985-06-21 Method for inspecting soldering appearance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13541985A JPS61293658A (en) 1985-06-21 1985-06-21 Method for inspecting soldering appearance

Publications (2)

Publication Number Publication Date
JPS61293658A JPS61293658A (en) 1986-12-24
JPH0481724B2 true JPH0481724B2 (en) 1992-12-24

Family

ID=15151292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13541985A Granted JPS61293658A (en) 1985-06-21 1985-06-21 Method for inspecting soldering appearance

Country Status (1)

Country Link
JP (1) JPS61293658A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0619252B2 (en) * 1987-09-14 1994-03-16 工業技術院長 Soldering inspection device for printed wiring boards
JPH0774730B2 (en) * 1989-08-12 1995-08-09 松下電工株式会社 Appearance inspection method for soldered parts
JP2781022B2 (en) * 1989-09-20 1998-07-30 三菱電機株式会社 Solder appearance inspection device
JPH085572A (en) * 1995-05-26 1996-01-12 Matsushita Electric Ind Co Ltd Appearance inspection method for electronic parts
JP5096940B2 (en) * 2008-01-22 2012-12-12 株式会社フジクラ Inspection method and apparatus for printed wiring board
JP5947055B2 (en) * 2012-02-23 2016-07-06 富士機械製造株式会社 Substrate appearance inspection machine, production line, and substrate appearance inspection method
JP6500818B2 (en) * 2016-03-17 2019-04-17 株式会社デンソー Winding coil manufacturing method, winding coil inspection method, and inspection apparatus

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59192945A (en) * 1983-04-15 1984-11-01 Hitachi Ltd Detecting method of pattern defect

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JPS61293658A (en) 1986-12-24

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