JPH0482079B2 - - Google Patents
Info
- Publication number
- JPH0482079B2 JPH0482079B2 JP59269781A JP26978184A JPH0482079B2 JP H0482079 B2 JPH0482079 B2 JP H0482079B2 JP 59269781 A JP59269781 A JP 59269781A JP 26978184 A JP26978184 A JP 26978184A JP H0482079 B2 JPH0482079 B2 JP H0482079B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- carrier
- printed wiring
- solder
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子部品搭載用キヤリヤ用基板の実
装方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for mounting a carrier substrate for mounting electronic components.
従来の技術
半導体チツプを搭載した印刷配線キヤリヤーと
しては、基板の上下すなわち、両面に電極を付し
て、上部を半導体チツプのダイ及びワイアボンデ
イングによる接続用に用い、基板の側面あるいは
スルーホールによつて下部のはんだ付け電極に電
気的に連絡する構造が一般的である。Prior Art A printed wiring carrier mounted with a semiconductor chip has electrodes attached to the upper and lower sides of the substrate, that is, both sides, and the upper part is used for connection by die and wire bonding of the semiconductor chip, and the printed wiring carrier is used for connection by die and wire bonding of the semiconductor chip. It is common to have a structure in which the electrode is electrically connected to the soldering electrode at the bottom.
発明が解決しようとする問題点
従来の印刷配線キヤリヤーには、次に述べる構
造的問題点がある。すなわち、下面の電極をはん
だ付けするに当つて、前記キヤリヤーを接続する
印刷配線板の導体との間が密着するために、はん
だ付けをおこなう〓間がなく、周囲を囲うような
はんだ付けを行なつていた。このため、接合強度
が十分でなかつた。また、はんだめつき、はんだ
クリームの印刷のようにはんだを前もつてはんだ
付け面に供給しておいても、印刷配線キヤリヤー
の自重又は接続時の加圧のため、はんだがはみ出
し、適切な厚さを保つ事ができないが、流出はん
だによる印刷導体間の短絡事故の原因となつてい
た。Problems to be Solved by the Invention Conventional printed wiring carriers have the following structural problems. In other words, when soldering the electrodes on the bottom surface, in order to ensure close contact between the carrier and the conductor of the printed wiring board, it is necessary to solder the carrier in a manner that surrounds the periphery. I was getting used to it. Therefore, the bonding strength was not sufficient. In addition, even if solder is applied to the soldering surface in advance, such as when soldering or printing solder cream, the solder may bulge out due to the weight of the printed wiring carrier or the pressure applied during connection. Although the thickness could not be maintained, leaked solder caused short circuits between printed conductors.
問題点を解決するための手段
本発明は、スルーホール接続孔下面に、はんだ
処理耐熱性レジストによる微小突起を形成し、印
刷配線板に当接させ、前記下面の導体層と前記印
刷配線板の導体とをはんだ層で接続する電子部品
キヤリヤ用基板の実装方法である。Means for Solving the Problems The present invention forms minute protrusions made of a soldering heat-resistant resist on the lower surface of the through-hole connection hole, brings them into contact with the printed wiring board, and connects the conductor layer on the lower surface with the printed wiring board. This is a mounting method for electronic component carrier substrates that connects conductors with a solder layer.
作 用
電子部品キヤリヤ用基板のスルーホール接続孔
の下面に、同孔を埋め、一部が周辺ランド部にま
たがるような耐熱性レジストによる微小突起を設
けると、このキヤリヤ用基板を支持する印刷配線
板の表面導体との間に適切なギヤツプを形成して
はんだ接合（はんだペーストの印刷でもデイツブ
ソルダー液の侵入でもよい）部を形成するのに好
都合である。Function When a micro protrusion made of heat-resistant resist is provided on the bottom surface of the through-hole connection hole of the electronic component carrier substrate, filling the hole and partially extending over the peripheral land, the printed wiring supporting the carrier substrate can be formed. It is advantageous to form a suitable gap with the surface conductor of the plate to form a solder joint (which may be printed with solder paste or penetrated by Dave's solder fluid).
実施例
本発明の実施例を第１図の断面図により詳しく
のべる。Embodiment An embodiment of the present invention will be described in detail with reference to the sectional view of FIG.
キヤリヤ用基板１の両面に導体層２を有し、キ
ヤリヤ用基板１を貫通する孔を埋めて、導電ペイ
ント３によるスルーホール接続体によつて、両面
の導体層２を互いに接続する。そして、導電ペイ
ント３の表面は、必要に応じて、銀めつき層４を
形成し、十分な導電性を確保する。 A carrier substrate 1 has conductor layers 2 on both sides, and holes penetrating through the carrier substrate 1 are filled, and the conductor layers 2 on both sides are connected to each other by a through-hole connector made of conductive paint 3. A silver plating layer 4 is formed on the surface of the conductive paint 3, if necessary, to ensure sufficient conductivity.
次に、基板１の表面側導体層２上に半導体チツ
プ５を載置し、ボンデイングワイア６で接続す
る。このキヤリヤ基板は、印刷配線板７上で、配
線導体８と導体層２とをはんだ層９によつて接続
して回路結合される。このとき、スルーホール接
続孔の下面に、耐熱性レジストによる微小突起１
０を設けると、はんだ層９の厚みを確保する間〓
が得られる。微小突起１０の形成は、孔の下面に
レジスト印刷後、熱又は光硬化を行なう。第２図
に下面各層の厚さの関係を示す。キヤリヤ下面の
スルーホールランドの厚さH2に導電手段である
スルーホールめつき又はスルーホール導電ペイン
トの厚さH3に対して、絶縁性の樹脂厚さH4の印
刷付加層が得られる。こうして部品キヤリヤー裏
面の導体からの突出高さとしてH2＋H3＋H4が厚
さ75μｍとして得られる。本発明においては、こ
のレジスト印刷が、部品キヤリヤ１のスルーホー
ル孔の物理的閉鎖を兼用しているのが特徴であ
り、下面はんだ付けの際に生ずるはんだ粒、はん
だ付け用フラツクスの侵入を防ぐと共に、湿気・
水分の侵入も防いでいる。なお、はんだ接合後、
キヤリヤ上面は外囲樹脂１１で封止される。耐熱
性レジストとしては、エポキシ又はポリイミド樹
脂の熱硬化型のものもしくは光硬化性を賦与した
エポキシアクリレイトを用いる。特に無溶剤型と
したものが作業し易い、なお印刷は部品キヤリヤ
の底部電極面を上面として、下面の突出部を治具
により平面化し、金属マスクによる厚目の印刷を
行なう、こうしてスルーホール接続孔が閉鎖さ
れ、その下面ランド上に耐熱性レジスト層を追加
した部品キヤリヤを得る。部品キヤリヤと印刷配
線板とのはんだ接合は、はんだデイツプでおこな
う事ができる。勿論はんだペーストの印刷とリフ
ロウソルダリングでおこなつてもよく、実施態様
例によれば、導体層２と配線導体８との面同志の
はんだ付け層が厚さ75〜125μに形成できる。 Next, a semiconductor chip 5 is placed on the front surface conductor layer 2 of the substrate 1 and connected with bonding wires 6. This carrier board is circuit-bonded by connecting the wiring conductor 8 and the conductor layer 2 with the solder layer 9 on the printed wiring board 7 . At this time, a minute protrusion 1 made of heat-resistant resist is placed on the bottom surface of the through-hole connection hole.
If 0 is provided, the thickness of the solder layer 9 is secured.
is obtained. The microprotrusions 10 are formed by printing a resist on the lower surface of the hole and then curing with heat or light. FIG. 2 shows the relationship between the thicknesses of each layer on the bottom surface. For the thickness H 2 of the through-hole land on the underside of the carrier and the thickness H 3 of the through-hole plating or through-hole conductive paint as the conductive means, a printed additional layer of insulating resin with a thickness H 4 is obtained. In this way, the protrusion height from the conductor on the back side of the component carrier is obtained as H 2 +H 3 +H 4 with a thickness of 75 μm. The present invention is characterized in that this resist printing also serves to physically close the through-holes of the component carrier 1, thereby preventing the intrusion of solder grains and soldering flux generated during bottom-side soldering. Along with humidity,
It also prevents moisture from entering. In addition, after soldering,
The upper surface of the carrier is sealed with a surrounding resin 11. As the heat-resistant resist, a thermosetting type of epoxy or polyimide resin, or an epoxy acrylate imparted with photocurability is used. The solvent-free type is especially easy to work with.For printing, use the bottom electrode surface of the component carrier as the top surface, flatten the protrusion on the bottom surface with a jig, and print thickly using a metal mask.Thus, through-hole connections are made. A component carrier is obtained in which the holes are closed and a layer of heat-resistant resist is added on its lower land. The solder joint between the component carrier and the printed wiring board can be made with a solder dip. Of course, printing of solder paste and reflow soldering may be used, and according to the embodiment, a soldering layer between the conductor layer 2 and the wiring conductor 8 can be formed to have a thickness of 75 to 125 μm.
発明の効果
部品キヤリヤの製造プロセスを増加することな
く、キヤリヤ下部に樹脂層によるスルーホール部
の閉鎖形成をすることができ、また従来問題であ
つたはんだ付けを樹脂層の脚を用いてキヤリヤの
下面導体と印刷配線板導体の平行面間に、はんだ
層を通常のデイツプ又はリフロウソルダリング工
程で形成できる。Effects of the invention It is possible to close the through-hole portion with a resin layer at the bottom of the carrier without increasing the manufacturing process of the component carrier, and the conventional problem of soldering can be solved by using the legs of the resin layer. A solder layer can be formed between the parallel surfaces of the bottom conductor and the printed wiring board conductor by a conventional dip or reflow soldering process.
第１図は本発明の実施例を示す断面図、第２図
は同要部断面図である。
１……部品キヤリヤ、２……キヤリヤー面の導
体、３……導電ペイント、４……銀めつき層、５
……半導体チツプ、６……ボンデイングワイア、
７……印刷配線板、８……印刷配線板の上面導
体、９……はんだ層、１０……レジスト微小突
起、１１……部品キヤリヤの封じ樹脂。
FIG. 1 is a cross-sectional view showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of essential parts thereof. 1... Part carrier, 2... Conductor on carrier surface, 3... Conductive paint, 4... Silver plating layer, 5
...Semiconductor chip, 6...Bonding wire,
7...Printed wiring board, 8...Top conductor of printed wiring board, 9...Solder layer, 10...Resist minute protrusions, 11... Sealing resin of component carrier.
Claims (1)
ーホール接続孔を通して上面、下面の前記導体層
を導電手段により接続する工程と、前記スルーホ
ール接続孔下面の前記導電手段の下部に、はんだ
処理耐熱性レジストを印刷し、硬化させて微小突
起を形成する工程と、前記微小突起を印刷配線板
に当接する工程と、前記下面の導体層と前記印刷
配線板上面の導体とをはんだ層で接続する工程と
を備えた電子部品キヤリヤ用基板の実装方法。1. Connecting the conductive layers on the upper and lower surfaces by conductive means through the through-hole connection holes of a carrier substrate having conductor layers on both sides, and applying heat-resistant soldering to the lower part of the conductive means on the lower surface of the through-hole connection holes. A step of printing a resist and curing it to form microprotrusions, a step of abutting the microprotrusions against a printed wiring board, and a step of connecting the conductor layer on the lower surface and the conductor on the upper surface of the printed wiring board with a solder layer. A method for mounting a substrate for an electronic component carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59269781A JPS61145893A (en) | 1984-12-20 | 1984-12-20 | Substrate for electronic component carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59269781A JPS61145893A (en) | 1984-12-20 | 1984-12-20 | Substrate for electronic component carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61145893A JPS61145893A (en) | 1986-07-03 |
| JPH0482079B2 true JPH0482079B2 (en) | 1992-12-25 |
Family
ID=17477065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59269781A Granted JPS61145893A (en) | 1984-12-20 | 1984-12-20 | Substrate for electronic component carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61145893A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7650688B2 (en) * | 2003-12-31 | 2010-01-26 | Chippac, Inc. | Bonding tool for mounting semiconductor chips |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5136740B2 (en) * | 1972-08-23 | 1976-10-12 | ||
| JPS5779652A (en) * | 1980-11-05 | 1982-05-18 | Nec Corp | Resin-sealed semiconductor device |
| JPS57166095A (en) * | 1981-04-07 | 1982-10-13 | Sharp Kk | Circuit board and method of producing same |
| JPS58120662U (en) * | 1982-02-12 | 1983-08-17 | 株式会社日立製作所 | Chippukiyariya |
| JPS59182975U (en) * | 1983-05-20 | 1984-12-06 | 松下電器産業株式会社 | printed wiring board |
-
1984
- 1984-12-20 JP JP59269781A patent/JPS61145893A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61145893A (en) | 1986-07-03 |
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