JPH048820B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A logic circuit that requires a transmission delay exceeding the machine cycle of the computer system in a clock synchronous computer system equipped with a clock supply mechanism in continuous clock mode and single clock mode. For example, in order to transmit a flip-flop (FF) output, in addition to the normal output signal, a shift register that shifts and stores the logic circuit output by one clock less than the transmission delay time, and the normal output and , a selection circuit for selecting one of the shift register outputs, and when switching from continuous clock mode to single clock mode, the logic circuit output is stored in the shift register, and when switching from single clock mode to continuous clock mode, the logic circuit output is stored in the shift register. The information stored in the shift register is output, and the normal output is selected in continuous clock mode, and the shift output is selected in single clock mode.

[Industrial application field]

The present invention relates to a method for transmitting the output of a logic circuit FF, which requires a transmission delay exceeding a machine cycle, in a clock synchronous computer system equipped with two clock supply mechanisms, a continuous clock mode and a single clock mode.

With recent remarkable progress in highly integrated technology, the machine cycles of computer systems are becoming increasingly shorter.

Therefore, for example, when transmitting data between devices that make up the computer system or transmitting the output of a logic circuit element that requires a long transmission time, it may take several times the machine cycle of the computer system. be.

On the other hand, in a clock synchronous computer system, there are two clock modes: a normal continuous clock mode, and a single clock mode, in which instructions addressed to one clock are executed to read the internal state of the computer system in detail, such as when diagnosing the computer system. Often equipped with a feeding mechanism.

In this case, even if the clock supply mode is switched between continuous clock mode, single clock mode, and continuous clock mode, the logic circuit that requires a transmission time of multiple machine cycles,
For example, it is required that flip-flop (FF) outputs do not lose synchronization.

[Conventional technology]

FIG. 3 is a diagram illustrating a conventional flip-flop (FF)-to-flip-flop (FF) transmission system.

First, in Figure a, when the transmission time between FFA1 and FFB2 is 4 times the machine cycle due to a long cable, etc., in the conventional method, the clock for FFA1 is changed to the EARLY clock (hereinafter referred to as BCLK). ), and the clock for FFB2 is a NORMAL clock (hereinafter referred to as
NCLK).

Figure b is a time chart showing the transmission operation of the flip-flop FF output using the above ECLK and NCLK.The signal sent by the first clock of ECLK of FFA1 is received by the second clock of NCLK. .

As is clear from this figure, by performing such transmission between flip-flops (hereinafter referred to as FF), even if the clock supply in continuous clock mode and single clock mode is alternately repeated, the output signal of the FF is No clock synchronization will occur.

In this case, ECLK requires an EARLY value (preceding machine cycle value) that is three times the machine cycle of the computer system compared to NCLK.

To create this ECLK, a delay circuit is required between ECLK and NCLK, as shown in c in this figure.

[Problem that the invention seeks to solve]

If such an inter-FF transmission method is adopted, the
When the inter-transmission time is n times the machine cycle, the delay time of the delay circuit needs to be (n-1) times the cycle time value.

Generally, when increasing the delay time of a delay circuit,
There is a problem that clock skew and jitter increase, which is a factor that prevents speeding up of the machine cycle of the computer system.

In view of the above-mentioned conventional drawbacks, the present invention aims to provide a method that can reliably perform inter-FF transmission exceeding machine cycles without using the above-mentioned delay circuit in order to reduce clock skew and jitter. This is the purpose.

[Means for solving problems]

FIG. 1 is a diagram showing an example of the configuration of a logic circuit output transmission system according to the present invention.

This configuration example shows a case where, for example, the transmission time between FFs requires four times the machine cycle.

In this figure, the flip-flops that are subject to transmission between FFs are FF4 and FF9.
FFs 5, 6, and 7 are provided as shift registers.

For FF4 and FF9, there is a gated clock (hereinafter referred to as GCLK) that can switch between continuous clock mode and single clock mode.
and configures the above shift register.
For FFs 5, 6, and 7, a free run clock (hereinafter referred to as FCLK) is controlled by an enable signal ENB generated when switching from single clock mode to continuous clock mode.
and the above GCLK (hereinafter referred to as
FGCLK). And the above FF4
The selection circuit 8 is configured to select between the mode switching signal SEL and FF7.

[Effect]

That is, according to the present invention, in a clock synchronous computer system equipped with a clock supply mechanism in continuous clock mode and single clock mode, logic circuits that require a transmission delay exceeding the machine cycle of the computer system, e.g. In order to transmit the flip-flop (FF) output, in addition to the normal output signal, a shift register that shifts and stores the logic circuit output by one clock less than the transmission delay time; and the normal output;
A selection circuit for selecting one of the shift register outputs is provided, and when switching from continuous clock mode to single clock mode, the logic circuit output is stored in the shift register, and when switching from the single clock mode to continuous clock mode, The information stored in the shift register is output, and the normal output is selected in continuous clock mode, and the shift output is selected in single clock mode, so the EARLY clock Transmission can be performed without any problems in continuous clock mode or single clock mode without using
This eliminates the need for a delay circuit to generate the EARLY clock, making it possible to simplify the clock circuit, reduce clock skew and jitter, and speed up the machine cycle.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 2 is a time chart showing the operation when performing inter-FF transmission by implementing the present invention.
The same reference numerals as in FIG. 3 indicate the same objects.

Hereinafter, with reference to FIG. 1, the present invention will be described.
The inter-FF transmission method will be explained.

As described above, in this embodiment, it is assumed that the inter-FF transmission time requires four times the machine cycle of the computer system.

First, the signals transmitted between the FFs (FF4 to FF9) are assumed to be A, B, C, . . . .

In this case, in continuous clock mode, the above FCLK and GCLK can be considered to be clocks in the same mode, so for example, the signal A sent from FF4 at the 1Cth clock of FCLK is the 5Cth clock after 4τ. It is received by FF9 at the clock. Thereafter, in the same manner, for example, signal B is received by FF9 at the 6Cth clock.

At this time, the selection circuit 8 selects the signal from the FF 4.

In single clock mode, GCLK3 4τ before switching to the single clock mode.
At C to 5C, signals C, D, sent from FF4
E and the aforementioned OR clock FGCLK4C to 6C
Accordingly, the above FFs 5 to 7 are sequentially shifted and stored, and at the time of switching to the single clock mode {according to the mode switching signal SEL shown in the figure},
The selection circuit 8 selects the above FF7 (i.e., signal C) and uses the single clock GCLKm.
Received on FF9.

Since the next signal D is set in FF7 by the single clock GCLKm in the single clock mode, it is set to FF7 by the next GCLKn.
Received on 9th.

At this stage, signals E, F,
This means that G is stored.

Next, when switching from the single clock mode to the continuous clock mode, by receiving the single clock mode signal (SGCLM) 4τ in advance, the enable signal (ENB) that enables FCLK is generated as shown in the figure. is generated, and through AND circuit 1 and OR circuit 2, three FCLK (n
-3, n-2, n-1) are supplied to FF5-7.

As a result, as mentioned above, the signals (E, F, G) stored in FFs 5 to 7 are sequentially transferred to the selection circuit 8.
GCLK (n +
1, n+2, n+3) is received by FF9.

In this way, after the signal G stored in FF5 is sent out from FF7, it is possible to return to continuous clock mode.

In this embodiment, the case where the inter-FF transmission requires 4τ (therefore, the shift circuit requires 3τ) was explained, but in general, even when the inter-FF transmission requires nτ, for example, ( It is clear that this problem can be solved by configuring shift registers for n-1) τ.

In this way, in the present invention, when inter-FF transmission exceeds machine cycles, nτ is required.
For inter-FF transmission, a shift register for (n-1)τ is provided, and at the time of switching from continuous clock mode to single clock mode, the (n
-1) of FF signals are accumulated, and at the time of switching from single clock mode to continuous clock mode, the FF signals of (n-1)τ accumulated in the shift register are outputted. The place has its own characteristics.

〔Effect of the invention〕

As described above in detail, the logic circuit output transmission method of the present invention is applicable to a clock synchronous computer system equipped with a clock supply mechanism in continuous clock mode and single clock mode.
In order to transmit the output of a logic circuit that requires a transmission delay exceeding the machine cycle of the computer system, such as a flip-flop (FF), in addition to the normal output signal, the above-mentioned A shift register for shifting and accumulating the logic circuit output and a selection circuit for selecting either the normal output or the shift register output are provided, and when switching from continuous clock mode to single clock mode, the shift register is provided with the above logic. The circuit output is accumulated, and when switching from the single clock mode to the continuous clock mode, the information accumulated in the shift register is output, and when the continuous clock mode is selected, the normal output is selected, and when the mode is switched from the single clock mode to the continuous clock mode, the information stored in the shift register is output. The above shift output is selected at the time. Without using the EARLY clock, transmission can be performed without any problems in continuous clock mode or single clock mode.
This eliminates the need for a delay circuit to generate the EARLY clock, making it possible to simplify the clock circuit, reduce clock skew and jitter, and speed up the machine cycle.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration example of the logic circuit output transmission method of the present invention, FIG. 2 is a time chart showing the operation when transmitting between FFs by implementing the present invention, and FIG. Conventional flip-flop (FF)
FIG. 2 is a diagram explaining an inter-communication transmission method. In the drawing, 4 to 7, 9 are flip-flops (FF), 8 is a selection circuit, 1C, 2C, 3C, ... are clock signals, A, B, C, ... are transmission signals,
SGCLM is a single clock mode signal, SEL is a mode switching signal, ENB is an enable signal,
FCLK is free run clock, GCLK is gated clock, FGCLK is OR clock, ECLK
indicates the EARLY clock, and NCLK indicates the NORMAL clock.

Claims (1)

[Claims] 1. In a clock synchronous computer system equipped with a clock supply mechanism in a continuous clock mode and a single clock mode, the output of a logic circuit (FF) that requires a transmission time exceeding a machine cycle is transmitted. In addition to the normal output 4 of the logic circuit FF, there is also a shift register 5 that shifts and stores the 4 normal output signals in multiple stages.
6, 7, and a circuit 8 for selecting either one of the two logic circuit signals, and when switching from continuous clock mode to single clock mode, the shift registers 5, 7 are provided.
The normal output 4 signals are stored in the clocks 6 and 7, and when switching from the single clock mode to the continuous clock mode, the accumulated shift register outputs 5, 6, and 7 are output, and in the continuous clock mode, the normal output 4 is output. of,
A logic circuit output transmission system characterized in that the shifted signal 7 is selected by the selection circuit 8 in a single clock mode.