JPH048862B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data sampling circuit for digital disks, digital tape recorders, etc., and particularly to a sampling circuit that is not affected by jitter or level fluctuations.

Conventional technology and its problems In optical disks, tape recorders, etc.
When retrieving recorded data, it is necessary to correctly match the slice level of the signal and the phase with the sampling clock, but in this case, the signal has level fluctuations, waveform distortion, jitter, etc., and the signal is automatically In order to follow the clock, an oscillator using a phase servo loop (PLL) is used, and data slicing is automatically optimized. However, these use independent circuits and are complicated.

Purpose of the Invention The present invention was made in view of the above-mentioned drawbacks, and in order to perform correct extraction with a simple circuit, data is sliced by a comparator, its output is extracted by a PLL oscillator, and the previous slice signal and extracted data are combined. The PLL and comparator slice level are controlled to keep the phase constant, and the purpose is to obtain a circuit that extracts data correctly regardless of level time fluctuations.

According to the present invention, the above object is to provide a slicing means for slicing an input signal with a feedback voltage, a latching means for latching the output of the slicing means by a clock from a voltage controlled oscillator, and a rising point of the output of the slicing means. A voltage corresponding to the pulse interval between the clock point and the falling point and the clock point is generated respectively, and the difference between these two voltages is used as the input feedback voltage, and the sum is used as the control voltage of the voltage controlled oscillator. This can be achieved by providing a data extraction circuit that does the following.

Embodiments of the Invention The data extraction circuit of the present invention will be described in detail below with reference to FIGS. 1 to 4. Figure 1 is a system diagram of the data extraction circuit of the present invention, Figure 2 is a circuit diagram of the pulse width voltage conversion circuit of Figure 1, Figure 3 is a waveform diagram of each part of Figure 1, and Figure 4 is a diagram of the pulse width voltage conversion circuit of Figure 1. 2 is another embodiment of the set-reset flip-prop circuit of FIG. 1;

In Fig. 1, comparator 1 has input terminal T ₁
For example, an NRZ signal a as shown in FIG. 3a is input. The NRZ signal a is sliced by a comparator 1 to form a square wave as shown in FIG. 3b, and is added to the flip-flop circuit 2 and latched at the timing of the clock C in FIG. 3c to output the signal in FIG. 3d. Next, the reset flip-flop (RSFF) 6 is set at the rising edge of FIG. 3b, and is set at the same rising edge of FIG. 3d. As a result, the waveforms shown in FIG. 3e are obtained. The waveforms shown in FIGS. 3b and 3d are added to the inverters 4 and 5, and conversely, the flip-flop 7 is set at the falling edge of FIG. 3b and reset at the falling edge of FIG. 3d. Figure 3 f
get the signal. Here, the signals e and f shown in FIG. 3e and f correspond to the phase difference between the input data and the extraction clock C. Next, the pulses e and f are converted into voltages corresponding to the pulse widths by the voltage conversion circuits 3 and 8, respectively, with the pulse width →. A circuit example of the pulse width-voltage conversion circuits 3 and 8 is shown in FIG. In other words, when the reverse voltage of pulse e or f is applied to the base of transistor TR, the collector of the transistor rises to + of the power supply when the pulse is input, but here it rises with the time constant of R ₁ and C ₁ . Figure 3g,
The waveform becomes like i ₁ or i ₂ shown in h and discharges at the end of the pulse. This voltage i is peak-detected by a diode D and a capacitor _C2 through a buffer circuit _A1 , and is extracted by a buffer circuit _A2 to obtain a voltage corresponding to the pulse width as shown in FIG.
g' or Fig. 3h is obtained. Here, the resistance R ₂ is a discharge resistance having a large value. As a result, the phase difference between the signal from comparator 1 and the clock can be obtained.
i ₁ is the phase difference between rising edges, and i ₂ is the phase difference between falling edges.
The output of this phase difference circuit in FIG. 3b corresponds to the phase difference between the slice signal and the extraction clock in FIG. 3c, and the same holds true even if the clock in FIG. In addition, the flip-flop circuits 6 and 7
Instead, as shown in another circuit example of FIG. 4, _the waveforms of _FIG .
Similarly, gated outputs e and f may be obtained by The above pulse width-voltage conversion circuit 3,
The outputs of 8 are added together by a mixer 10, and a differential output from a reference voltage V corresponding to the phase difference of the reference is obtained by a comparison amplifier 11, which is then sent to a voltage control oscillator 12.
(VCO). This results in the sampling pulse shown in FIG. 3c, which is always in constant phase with signal b. On the other hand, the differential amplifier 9 amplifies the voltage of the difference between the waveforms in FIG. 3g and h, and feeds it back to one input of the input comparator 1. If the data are compared correctly at the center of the data as shown in FIG. 3a, then g and h in FIG. 3 will be equal, and a corresponding voltage j will be generated. If the voltage j deviates from the reference position as shown by the dotted line j' in Figure 3a, the waveform in Figure 3b will change to the dotted line.
It becomes like b′. For this reason, the waveforms g and h in Figure 3 g and h are shifted as g and h'. Therefore, the output j of the differential amplifier 9 rises, and the pulse widths of e and f are equal, that is, they are correct. It is fed back to the sampling voltage. Therefore, even if the input drifts or the level fluctuates, data can always be extracted at the correct position, the data can be taken into the flip-flop circuit 2 at the correct clock phase, and the output d can be obtained. Here, in order to not respond to fast input changes, such as dropouts, for each loop,
Of course it is possible to create a low pass filter.

Effects of the Invention Since the present invention is constructed as described above, it is possible to extract correct data even if the input data always fluctuates in level or time direction, and it is possible to provide an effective data extraction circuit for digital disks, etc. Has characteristics.

[Brief explanation of drawings]

FIG. 1 is a system diagram of the data extraction circuit of the present invention, FIG. 2 is a circuit diagram of the pulse width-voltage conversion circuit of FIG. 1, FIG. 3 is a waveform diagram for explaining the operation of FIG. 1, and FIG.
This figure is a circuit diagram showing another embodiment of the set/reset flip-flop circuit shown in FIG. 1. 1...Comparator, 2...Flip-flop circuit, 3, 8...Pulse width-voltage conversion circuit, 4,
5, I ₁ , I ₂ ... Inverter circuit, 6, 7 ... Set, reset flip-flop circuit, 9 ... Differential amplifier, 10 ... Mixer, 11 ... Comparison amplifier,
12...VCO, AND ₁ , AND ₂ ...AND circuit.

Claims (1)

[Claims] 1 slicing means for slicing an input signal with a feedback voltage; latching means for latching the output of the slicing means by a clock from a voltage controlled oscillator;
Voltages corresponding to the pulse intervals between the rising point and the clock point of the output of the slicing means and between the falling point and the clock point are generated respectively, and the difference between these two voltages is used as the feedback voltage of the input, and the voltage is determined by the summation. A data extraction circuit designed to be used as a control voltage for a controlled oscillator.