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JPH048961B2 - - Google Patents
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JPH048961B2 - - Google Patents

Info

Publication number
JPH048961B2
JPH048961B2 JP57216576A JP21657682A JPH048961B2 JP H048961 B2 JPH048961 B2 JP H048961B2 JP 57216576 A JP57216576 A JP 57216576A JP 21657682 A JP21657682 A JP 21657682A JP H048961 B2 JPH048961 B2 JP H048961B2
Authority
JP
Japan
Prior art keywords
metal substrate
line
circuit board
recess
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57216576A
Other languages
Japanese (ja)
Other versions
JPS59107601A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP57216576A priority Critical patent/JPS59107601A/en
Publication of JPS59107601A publication Critical patent/JPS59107601A/en
Publication of JPH048961B2 publication Critical patent/JPH048961B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00Waveguides; Transmission lines of the waveguide type
    • H01P3/02Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/08Microstrips; Strip lines
    • H01P3/081Microstriplines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Waveguide Connection Structure (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は、マイクロ波帯、ミリ波帯において伝
送線路として用いられるストリツプ線路、とくに
スロツト線路を備えたモジユールに関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a module equipped with a strip line, particularly a slot line, used as a transmission line in the microwave band and millimeter wave band.

マイクロ波帯、ミリ波帯(以下、マイクロ波と
略称する)を利用した通信装置の送信装置、受信
装置などのマイクロ波を伝送する伝送線路として
の線路は、小形化、軽量化および構造の簡素化な
どの要求からマイクロストリツプ線路が用いられ
ている。
Lines used as transmission lines for transmitting microwaves, such as transmitting devices and receiving devices of communication devices that utilize microwave bands and millimeter wave bands (hereinafter referred to as microwaves), need to be made smaller, lighter, and simpler in structure. Microstrip lines are being used due to demands such as

誘電体基板の上面に回路パターンが形成され、
裏面には全面接地導体層が形成された回路基板
を、金属基板の上面に接地導体層を半田付け、導
電性接着剤などで導電接着してモジユールに構成
される。このようなモジユールは回路基板に形成
される回路構成によつて、発振器、サーキユレー
タ、可変減衰器、増幅器、濾波器、変調器、ミキ
サなどの機能単位に構成され、それぞれが単位調
整された後に金属製箱形の筐体内に縦列に設置さ
れて金属基板が筐体底面に個々にねじ止め固定さ
れるとともに、相互間を回路接続される。信号は
筐体を貫通する信号線路により、電源は同じく筐
体を貫通する電源線によつてそれぞれ所定の個所
に接続され、総合的な調整が行われた後に筐体開
口が金属カバーで覆われてねじ止め固定されるこ
とによつて装置の高周波部が構成される。
A circuit pattern is formed on the top surface of the dielectric substrate,
A circuit board with a full-surface ground conductor layer formed on the back side is formed into a module by soldering a ground conductor layer to the top surface of the metal board and conductively bonding it with a conductive adhesive. These modules are configured into functional units such as oscillators, circulators, variable attenuators, amplifiers, filters, modulators, and mixers, depending on the circuit configuration formed on the circuit board. The metal substrates are installed in a vertical line inside a box-shaped housing, and the metal substrates are individually screwed and fixed to the bottom of the housing, and the circuits are connected to each other. Signals are connected to predetermined locations by signal lines that pass through the case, and power supplies are connected to predetermined locations by power lines that also pass through the case.After comprehensive adjustment is made, the case opening is covered with a metal cover. The high-frequency section of the device is configured by fixing with screws.

(b) 従来技術とその問題点 上記した要素モジユールで、例えばミキサは半
導体素子が用いられるが、半導体素子は気密に密
封されて空気に触れないような構成が要求され
る。そこで従来はパツケージ化された半導体素子
をモジユールの回路基板上に配置し、パツケージ
の電極を介して回路接続するようにしていた。こ
のようにパツケージを回路基板上に搭載すること
から大形化が避けられず、高周波領域で使用され
る場合には良好な整合を行うことが困難なために
所要の周波数特性が得られないといつた問題点が
あつた。
(b) Prior Art and its Problems Among the above-mentioned element modules, for example, a mixer uses a semiconductor element, but the semiconductor element is required to be hermetically sealed so that it does not come into contact with air. Conventionally, packaged semiconductor elements were placed on a module circuit board, and circuit connections were made via the package's electrodes. Since the package is mounted on the circuit board in this way, it is unavoidable to increase the size of the package, and when used in the high frequency range, it is difficult to achieve good matching, making it difficult to obtain the required frequency characteristics. A number of problems arose.

(c) 発明の目的 本発明は、上記従来の問題点に鑑み、良好な周
波数特性が得られるように、しかも大形化するこ
となくチツプ状の半導体素子を劣化させずに従来
のモジユール内に実装したストリツプ線路モジユ
ールの提供をすることにある。
(c) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention has been devised to provide a method for incorporating chip-shaped semiconductor elements into conventional modules so as to obtain good frequency characteristics without increasing the size and without deteriorating chip-shaped semiconductor elements. Our objective is to provide an implemented strip line module.

(d) 発明の構成 上記目的を構成するために本発明は、上面に信
号伝送路としてのマイクロストリツプ線路などの
パターンを備えた誘電体基板の裏面の一部を金属
基板の上面に密着してなるモジユールにおいて、
上記誘電体基板の裏面にスロツト線路のパターン
を備えかつ半導体素子を実装してなるとともに、
金属基板の裏面に凹所と該凹所底面に上記誘電体
基板のスロツト線路面が覗く窓孔と該凹所内に挿
通された気密封止形の端子を設け、上記半導体素
子と端子とをリード線で接線し、金属基板の凹所
開口をカバーで密閉した構成としている。
(d) Structure of the Invention In order to achieve the above object, the present invention provides a method in which a part of the back surface of a dielectric substrate having a pattern such as a microstrip line as a signal transmission path on the top surface is tightly attached to the top surface of a metal substrate. In the module that will be made,
A slot line pattern is provided on the back surface of the dielectric substrate and a semiconductor element is mounted thereon.
A recess is provided on the back surface of the metal substrate, a window hole through which the slot line surface of the dielectric substrate can be seen is provided at the bottom of the recess, and an airtight terminal inserted into the recess is provided to lead the semiconductor element and the terminal. The recessed opening of the metal substrate is sealed with a cover.

(e) 発明の実施例 以下、図面を参照して本発明の実施例を説明す
る。第1図は本発明の第1の実施例を示すもの
で、イはマイクロストリツプ線路モジユールの斜
視図、ロは裏面より見た斜視図、ハは分解状態の
縦断面図、ニは組立状態の縦断面図、ホは端子の
引き出し位置の他の例を示す縦断面図、第2図は
回路基板を素子搭載側すなわちスロツト線路側の
裏面から見た斜視図である。
(e) Embodiments of the invention Hereinafter, embodiments of the invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of the present invention, in which A is a perspective view of a microstrip line module, B is a perspective view seen from the back, C is a longitudinal cross-sectional view of an exploded state, and D is an assembled FIG. 2 is a vertical sectional view showing another example of the terminal extraction position, and FIG. 2 is a perspective view of the circuit board viewed from the back side on the element mounting side, that is, the slot line side.

図において、1は回路基板であり、セラミツク
やサフアイア、石英などの誘電体基板2の片方の
面、例えば図の上側の表面に、マイクロストリツ
プ線路3がパターン形成され、他方の面、例えば
図の下側の裏面にスロツト線路4がパターン形成
されている。
In the figure, 1 is a circuit board, and a microstrip line 3 is patterned on one side of a dielectric substrate 2 made of ceramic, sapphire, quartz, etc., for example, the upper surface of the figure, and on the other side, for example, A slot line 4 is patterned on the back surface at the bottom of the figure.

このマイクロストリツプ線路3やスロツト線路
4は、公知の金属蒸着法などの手法によりパター
ニングされる。また裏面のスロツト線路4側の面
にはチツプ状の半導体素子5、例えばビームリー
ド形ダイオードが4個搭載され、該半導体素子5
に金のワイヤないしリボン6が接地導体層上に形
成された接続用導体パターンPを介して接続され
て、本実施例の場合ミキサが形成される。マイク
ロストリツプ線路3には高周波信号と局部発振信
号が入力され、これらがスロツト線路に結合され
て信号成分が抽出される。この回路基板1は、キ
ヤリアとしての金属基板7に搭載される。金属基
板7は全体が一枚の金属板であり、裏面に凹所8
と開口段部9と凹所8の底面に所要の大きさの窓
孔が貫通形成されている。また、イ,ロに示され
るように左右両端に実装用のねじ挿通孔が穿設さ
れている。
The microstrip line 3 and the slot line 4 are patterned by a known method such as metal vapor deposition. Further, on the back surface on the side of the slot line 4, chip-shaped semiconductor elements 5, for example, four beam lead type diodes, are mounted.
A gold wire or ribbon 6 is connected to the ground conductor layer through a connecting conductor pattern P formed on the ground conductor layer to form a mixer in this embodiment. A high frequency signal and a local oscillation signal are input to the microstrip line 3, and these are coupled to the slot line to extract signal components. This circuit board 1 is mounted on a metal board 7 as a carrier. The metal substrate 7 is entirely made of one metal plate, and has a recess 8 on the back side.
A window hole of a required size is formed through the opening step 9 and the bottom of the recess 8. Further, as shown in A and B, screw insertion holes for mounting are bored at both left and right ends.

この金属基板7の上面に、孔10を塞ぐように
回路基板1の裏面を密着させて搭載され、封止部
11において、スロツト線路周囲の接地導体層に
よりロウ付け等で接合封止される。即ち、スロツ
ト線路4、半導体素子5、接続用導体パターンP
は凹所8内に窓孔10から覗いていることにな
る。窓孔10の大きさはこのような関係となるよ
うに定められている。
The back surface of the circuit board 1 is mounted on the upper surface of the metal substrate 7 in close contact with the hole 10 so as to close the hole 10, and is bonded and sealed by brazing or the like with a ground conductor layer around the slot line at the sealing portion 11. That is, the slot line 4, the semiconductor element 5, the connecting conductor pattern P
is looking into the recess 8 through the window hole 10. The size of the window hole 10 is determined to satisfy this relationship.

次にケース7に挿通されたハーメチツクガラス
端子12の内端に、半導体素子5のワイヤ6を接
続し、次いで凹所8内に窒素ガスなどの不活性ガ
スを充填した状態で、段部9に金属板でなるカバ
ー13を嵌め込み、接合部14でロウ付けし、封
止することによつてニのように底面が平坦となる
ように組み立てる。なお、信号出力用のハーメチ
ツクガラス端子は、ホに15で示すようにカバー
13と平行に挿通することもできる。
Next, the wire 6 of the semiconductor element 5 is connected to the inner end of the hermetic glass terminal 12 inserted through the case 7, and then, with the recess 8 filled with an inert gas such as nitrogen gas, the stepped portion is A cover 13 made of a metal plate is fitted to 9, and the joint part 14 is brazed and sealed, so that the bottom surface becomes flat as shown in D. Note that the hermetic glass terminal for signal output can also be inserted in parallel to the cover 13 as shown at 15 in E.

第2図において、スロツト線路4と反対側の表
面には、マイクロストリツプ線路3に代えてコプ
レナ線路を形成しても差支えない。
In FIG. 2, a coplanar line may be formed on the surface opposite to the slot line 4 instead of the microstrip line 3.

以上は回路基板の片面のみに半導体素子を実装
する例であるが、第3図のように回路基板1の上
下両面に半導体素子を実装することもできる。第
3図は、本発明の第2の実施例を示すもので、イ
は分解斜視図、ロは縦断面図である。回路基板1
は、その表面にマイクロストリツプ線路3または
コプレナ線路がパターン形成され、裏面にスロツ
ト線路4がパターン形成される点は、第1図およ
び第2図の例と同じである。しかしながら、半導
体素子は、スロツト線路4側の裏面に5のように
実装するとともに、16で示されるようにマイク
ロストリツプ線路3またはコプレナ線路側の表面
にも実装されている。回路基板1の金属基板7へ
の実装形態も第1図の例と同じである。そうして
表面側の半導体素子16を気密封止するために、
ケース17が用いられる。
Although the above is an example in which semiconductor elements are mounted only on one side of the circuit board, it is also possible to mount semiconductor elements on both the upper and lower sides of the circuit board 1 as shown in FIG. FIG. 3 shows a second embodiment of the present invention, in which A is an exploded perspective view and B is a longitudinal sectional view. circuit board 1
is the same as the examples shown in FIGS. 1 and 2 in that a microstrip line 3 or a coplanar line is patterned on the front surface, and a slot line 4 is patterned on the back surface. However, the semiconductor elements are mounted on the back surface on the slot line 4 side as shown at 5, and also on the surface on the microstrip line 3 or coplanar line side as shown at 16. The manner in which the circuit board 1 is mounted on the metal substrate 7 is also the same as the example shown in FIG. In order to hermetically seal the semiconductor element 16 on the front side,
Case 17 is used.

ケース17は、セラミツク材などで4角形の枠
状に形成され、外壁などの所要の面は金などでメ
タライズされ、金属面18となつている。この枠
状ケース17が回路基板1を取り囲むように金属
基板7に搭載され、接合部19が接着剤やロウな
どで接合される。次いで、ケース17内に窒素ガ
スなどの不活性ガスを充填した状態でカバー20
を被せ、接合部21を接着剤やロウで接合する。
22は表面の半導体素子16へのリード端子であ
り、ケース17のメタライズされていない側面か
ら金属基板7と接触しないように引き出される。
The case 17 is formed into a rectangular frame shape from ceramic material or the like, and required surfaces such as the outer wall are metallized with gold or the like to form a metal surface 18. This frame-shaped case 17 is mounted on the metal substrate 7 so as to surround the circuit board 1, and the joint portion 19 is joined with adhesive, wax, or the like. Next, the cover 20 is filled with an inert gas such as nitrogen gas inside the case 17.
, and the joint portion 21 is joined with adhesive or wax.
Reference numeral 22 denotes a lead terminal to the semiconductor element 16 on the front surface, which is pulled out from the non-metalized side surface of the case 17 so as not to come into contact with the metal substrate 7.

上記構成によれば、回路基板1の裏面側の半導
体素子5は、金属基板7内で気密が維持され、表
面側の半導体素子16はケース17で気密が維持
される。このように、両面の半導体素子を気密封
止する構成とすれば、回路基板1の両面に気密封
止を要する半導体素子を実装することができるの
で、第1図の例よりもさらに高密度実装を要する
装置の場合に極めて有効である。なお、この例の
場合もハーメチツクガラス端子を、第1図ホの場
合と同様にカバー13と平行に配置することもで
きる。
According to the above configuration, the semiconductor element 5 on the back side of the circuit board 1 is kept airtight in the metal substrate 7, and the semiconductor element 16 on the front side is kept airtight in the case 17. In this way, if the semiconductor elements on both sides are hermetically sealed, it is possible to mount semiconductor elements that require hermetic sealing on both sides of the circuit board 1, allowing for higher-density mounting than the example shown in FIG. This is extremely effective for devices that require In this example, the hermetic glass terminal can also be arranged parallel to the cover 13, as in the case shown in FIG. 1E.

第1図の例と逆に、回路基板1の表面側だけに
気密封止を要する半導体素子を実装する場合は、
第3図の例の表面側のケース17のみを気密封止
構造とし、裏面側の金属基板7は気密封止構造と
しないで、単なる実装用基板とする。
Contrary to the example in FIG. 1, when mounting a semiconductor element that requires hermetic sealing only on the front side of the circuit board 1,
In the example shown in FIG. 3, only the case 17 on the front side has an airtight sealing structure, and the metal substrate 7 on the back side does not have an airtight sealing structure, but is simply a mounting board.

(f) 発明の効果 以上のように、本発明によればストリツプ線路
モジユールの実装用金属基板中に気密封止を必要
とする半導体素子を同一基板の裏面に実装して効
果的に気密封止することができる。しかも構造が
簡単で、気密性を確実に維持することができ、モ
ジユール自体を従来と同一の寸法形状として大形
化することもなく、整合性も良好である。
(f) Effects of the Invention As described above, according to the present invention, semiconductor elements that require hermetic sealing in a metal substrate for mounting a strip line module can be mounted on the back side of the same substrate to effectively hermetically seal them. can do. In addition, the structure is simple, airtightness can be maintained reliably, the module itself has the same dimensions and shape as the conventional one without having to be enlarged, and the compatibility is good.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明によるストリツプ線路モジユール
の実施例を示すもので、第1図は第1の実施例を
示す斜視図および断面図、第2図は回路基板の斜
視図、第3図は本発明の第2の実施例を示す分解
斜視図と組立状態の縦断面図である。 図において、1は回路基板、2は誘電体基板、
3はマイクロストリツプ線路、4はスロツト線
路、5,16は半導体素子、7は金属基板、8は
凹所、9は段部、10は窓孔、11,14,1
9,21は接合部、12,15,22はハーメチ
ツクガラス端子、13,20はカバー、17はケ
ース、をそれぞれ示す。
The drawings show embodiments of the strip line module according to the present invention. FIG. 1 is a perspective view and a sectional view showing the first embodiment, FIG. 2 is a perspective view of a circuit board, and FIG. 3 is a strip line module according to the present invention. FIG. 7 is an exploded perspective view and a vertical cross-sectional view of the second embodiment in an assembled state. In the figure, 1 is a circuit board, 2 is a dielectric substrate,
3 is a microstrip line, 4 is a slot line, 5 and 16 are semiconductor elements, 7 is a metal substrate, 8 is a recess, 9 is a step, 10 is a window hole, 11, 14, 1
9 and 21 are joint parts, 12, 15 and 22 are hermetic glass terminals, 13 and 20 are covers, and 17 is a case, respectively.

Claims (1)

【特許請求の範囲】 1 上面に信号伝送路としてのマイクロストリツ
プ線路などのパターンを備えた誘電体基板の裏面
の一部を金属基板の上面に密着してなるモジユー
ルにおいて、 上記誘電体基板の裏面にスロツト線路のパター
ンを備えかつ半導体素子を実装してなるととも
に、金属基板の裏面に凹所と該凹所底面に上記誘
電体基板のスロツト線路面が覗く窓孔と該凹所内
に挿通された気密封止形の端子を設け、 上記半導体素子と端子とをリード線で接続し、
金属基板の凹所開口をカバーで密閉したことを特
徴とするストリツプ線路モジユール。
[Scope of Claims] 1. A module in which a part of the back surface of a dielectric substrate having a pattern such as a microstrip line as a signal transmission path on the top surface is closely attached to the top surface of a metal substrate, A slot line pattern is provided on the back surface of the metal substrate and a semiconductor element is mounted thereon, and a recess is provided on the back surface of the metal substrate, and a window hole through which the slot line surface of the dielectric substrate can be seen is inserted into the recess at the bottom of the recess. A hermetically sealed terminal is provided, and the semiconductor element and the terminal are connected with a lead wire.
A strip line module characterized by having a recessed opening in a metal substrate sealed with a cover.
JP57216576A 1982-12-10 1982-12-10 Strip line module Granted JPS59107601A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57216576A JPS59107601A (en) 1982-12-10 1982-12-10 Strip line module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57216576A JPS59107601A (en) 1982-12-10 1982-12-10 Strip line module

Publications (2)

Publication Number Publication Date
JPS59107601A JPS59107601A (en) 1984-06-21
JPH048961B2 true JPH048961B2 (en) 1992-02-18

Family

ID=16690575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57216576A Granted JPS59107601A (en) 1982-12-10 1982-12-10 Strip line module

Country Status (1)

Country Link
JP (1) JPS59107601A (en)

Also Published As

Publication number Publication date
JPS59107601A (en) 1984-06-21

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