JPH048969B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock and a radio receiver having a frequency display function of a radio receiving section. The device according to the present invention is used, for example, to control display switching between the frequency display and the clock display when the display section of a car radio is capable of displaying both a frequency display and a clock display.

[Prior art and problems to be solved by the invention]

Conventionally, when displaying both a frequency and a clock on a car radio display, the clock is always displayed. (1) When the power to the radio receiver is cut off, the clock is always displayed When the radio receiver is turned on after that, the frequency will be displayed for a certain period of time, and (2) the frequency will be displayed while the radio receiver is being tuned. The clock display state will be displayed for a certain period of time, and when these operations are completed, the display will be maintained for a certain period of time, and after these operations (1) and (2), the clock display state will be maintained at all times. There is.

By the way, users of radio receivers have various requirements regarding the use of their radio receivers. One such request is simply checking a low-priority display, but as in the past, by operating a switch, etc. that corresponds to the low-priority display, you can temporarily check that display. If the configuration is such that the switch is switched to , an erroneous operation may occur in some cases. That is, when selecting a station using the conventional radio receiver described above, the frequency is displayed in response to a tuning operation, such as raising or lowering the receiving frequency, and the user selects a station while checking the frequency. However, if you simply want to check the current reception frequency, if you perform a tuning operation to check the frequency, the reception frequency will change depending on the selection. Therefore, it is not possible to check the frequency that is currently being received.

Therefore, it is conceivable to provide a switch to check the low priority display, and when this switch is operated, the low priority display will be displayed for a certain period of time, but in this case, from the switch operation. There is a problem in that the display cannot be returned to a higher priority display until a certain period of time has elapsed, resulting in poor operability.

In other words, if a program scheduled to be broadcast at a certain time does not start at that time, the time and frequency may be compared alternately, and it is desirable to check the other display immediately after checking one display. It is rare.

However, when switching from a high-priority display to a low-priority display, the lower-priority display continues to be displayed for a certain period of time, making it difficult for the operator to see the display he or she wants to see immediately. bad. Especially when it comes to in-vehicle radio receivers, it is assumed that the display will be checked while driving, but it may take several seconds to check the display after groping the display changeover switch. Since the certain period of time is set relatively long, for example, 5 seconds, the operability becomes even worse when checking both displays when the vehicle is stopped. The present invention aims to solve these problems.

[Means for solving problems]

In the present invention, the display means 9 for displaying the time or frequency, the radio switch 342 for operating the radio, and the time display and the frequency display are given priority, and the display means usually has priority among the time or frequency. Along with the high degree of display,
In an in-vehicle radio receiver having a frequency display function of a clock and radio receiving section, which is equipped with a display control means 5 that displays a frequency at least when a radio switch is operated, the time display and the frequency display are switched and displayed. Manually operated recall switch 341 for
and display reversing means 501, 518, 502 for causing the display means to display the low priority display for a predetermined period of time when an operation of the recall switch is detected while displaying the high priority display; A clock and radio receiving section characterized by comprising a display return means 503 for immediately returning to a high priority display when an operation of the recall switch is detected while a low priority display is being displayed by the reversing means. A radio receiver having a frequency display function is provided.

〔Example〕

A display control device as an embodiment of the present invention is applied. A basic circuit diagram of a radio receiver is shown in FIG. The display device 9 in the circuit of FIG. 1 is, for example, a seven-element display figure 91 as shown in FIG.
The frequency f display shows, for example, 76.0MHz, and the clock c display shows, for example, 76.0MHz.
Display is performed using the display device 9 in common to show 12:30 AM (or PM).

The radio receiving circuit 1 includes a receiving input circuit 11, an integrated circuit phase lock loop unit 12, and a low-pass filter 1.
3, a radio output circuit 14 and a speaker 15. The tuning circuit 2 that supplies output to the phase lock loop section includes a manual and search operation holding circuit 41, an operation holding circuit 42, and an operation holding circuit 4 operated by switch sections 31, 32, 33, 34, and 35.
3, and receives the output signal of the band selection circuit 44. One of the outputs of the tuning circuit 2 is the frequency calculation circuit 6.
supplied to The output of the frequency calculation circuit 6 and the output of the clock counting circuit 7 based on the crystal oscillation XTL signal are supplied to the display selection circuit 8. Operation holding circuit 41, operation holding circuit 42, operation holding circuit 43,
In response to the output signal of the band selection circuit 44, the display selection circuit 8 is controlled by the output signal of the display control circuit 5 operated by the recall switch 341 and the clock/frequency priority changeover switch 343. (The recall switch 341 is a switch for responding to a request to display something on the opposite side of what is currently being displayed.) The display selection circuit 8
The display device 9 is driven by the output signal.

A specific circuit diagram of the circuit in FIG. 1 is shown in FIG.
A detailed circuit diagram of the display control circuit 5 in the circuit of FIG. 2 is shown in FIG. The circuit elements shown in FIGS. 3 and 4 will be explained as follows.

A. Phase locked loop synthesizer type tuning circuit 12: Receives the received signal from the reception input circuit 11, is controlled by the selection circuit, and supplies an output to the low-pass filter.

B Data selector 22: Generates output in synchronization with the 4-digit signal from the signal generator 21, and transfers the frequency division ratio N, which is composed of BCD and 4 bits, to the phase lock loop tuning circuit 12 in parallel. .

BCD programmable up/down counters 241, 242, 243: Performs up/down counting based on the signal from the decoder circuit 23. Random access memory 2
The preset data is taken in by the signal from 5. Change the upper and lower limits of the band.

D. 4-bit programmable up/down
Counter 244: Outputs the highest digit of the frequency division ratio N value and a reference switching signal.

16-bit digital comparator 28: Determines whether the division ratio N value has reached the upper or lower limit of the band.

Calculation circuit 6: A circuit that calculates the reception frequency fs from the frequency division ratio N value.
When fr is the reference frequency, fs is the reception frequency, fo is the local oscillation frequency, and fi is the intermediate frequency, the following relationship holds true. fo=N・fr, fs=fo±fi Display device 9: A device that displays either the receiving frequency or clock time.

4-bit or 16-bit random access memory25: Random access memory (RAM) that can be read and written freely, and has an upper or lower bandwidth limit of N
It stores the value and outputs when the band limit value is reached during sweep or manual operation. It also outputs the contents of the preset. Also, when switching bands, the previous state of that band is output.

(f) Read or write control circuit 26: When the write switch is closed and the preset contents are rewritten, and when the upper and lower limits of the band are reached, the N value of the next limit to be received is stored in the random access memory. Write to 25. Thereby, the random access memory 25 is controlled.

Long/medium wave selector 29: Automatically switches between long wave and medium wave bands.

Operation holding circuit 41: Holds up or down manual operation and up or down search operation, and determines priority.

Operation holding circuit 42: Holds the write state and is released by the preset key.

Operation holding circuit 43: Holds the preset states set by the preset switches 331 to 33n.

C Band selection circuit 44: Logicizes key input band information.

E. Long/medium wave power selection circuit 291: Switches the power of the long wave tuner section and the medium wave tuner section according to the logic of the long/medium wave selector 29.

Sweep control decoder 23: Uses the sweep clock to switch up and down the BCD and 4-bit programmable up-down counter by the number of pulses. When searching, the clock from the signal generator 21 is output to automatically vary the N value, and when searching is manual, the N value is varied by outputting as many times as the manual key switch is turned on and off.

H. Display control circuit 5: When the operation switch is pressed, it selects the appropriate clock or frequency to display, and outputs the result to the display signal selection circuit 8 as a clock/frequency display instruction signal.

Clock counting circuit 7: Sequentially divides and counts the clock reference signal based on the reference pulse.

Display signal selection circuit 8: Selects the output of either the frequency calculation circuit 6 or the clock counting circuit 7 according to the clock/frequency display instruction signal sent from the display control circuit 5, and outputs the result to the display device 9.

A specific circuit configuration example of the display control circuit 5 in the circuit of FIG. 3 is shown in FIG.

C. Timer counter 501: Counts T seconds on the clock. During counting, the output is "0",
After the counting is completed, the output becomes "1".

High flip-flop circuit 502: Usually operates through operation (input and output are equal), but when there is a “display priority switching” signal, it performs inversion operation (outputs with inverted input) and then latches, and the timer counter 501 finishes counting. At the same time, the latch is released and the through operation is resumed.

Flip-flop circuit 503: Normally performs a through operation, that is, outputs the signal given from one of the gate circuits 512 and 513, but during counting by the timer counter 501, a trigger signal due to the closing of the recall switch 341 is input to the trigger ( TRG), it latches after the inversion operation, and then the timer counter 50
When a rectangular wave pulse with a wave height of "1" is applied to the COND input that has finished counting 1, the latch is released and the through operation is resumed.

F. Display priority switching detection circuit 526: Generates a pulse regardless of whether the display priority switch 343 is switched to clock or frequency.

E. Search and scan state holding circuit (not shown): Although this circuit is inserted in the middle of the input line from the manual down/up switches 311 to 314 to the gate circuit 511, it is not directly related to the gist of the present invention. , illustration is omitted. This circuit consists of a flip-flop array. Outputs a "low" level signal when in the on state. It is reset when a receive (iF) signal is input during the search up/down state. When the search up/down switch is in the starting state, any operation of switches 331 to 33n, switches 311, 312, and switch 351 will reset the search. The scan state is set or reset by toggling. Search up/down switches 313, 314, manual switches 311, 312, band change switch 351
It will be reset if any of these operations are performed. When reset, it outputs a "high" level signal.

Instruction signal output circuit 509: Consists of a D-type flip-flop circuit having preset (PSET) and clear (CLR) inputs.
Clear input has priority over preset input. During a clock adjustment operation and when the radio power is cut off, the preset input is at a "high" level, and the output signal is at a "high" level regardless of the input signal from circuit 503. In contrast, search up/down, scanning, tuning, manual up/down, band switching, or
When a series of channel selection operations such as powering on the radio receiver are performed, the clear input becomes a "high" level, and the output signal becomes a "low" level regardless of the input signal from the circuit 503.

Time limit circuit 510: Gives priority to frequency display for a certain period of time after band switching or radio receiver power is turned on, and is then opened.

Gate circuit 511: The output is enabled when the power to the radio receiver is turned on, and the output is at the "high" level or open when the power to the radio receiver is turned off.

Gate circuits 512 to 522: Gate circuits 512 to 514 are 3-state buffer circuits, gate circuit 515 is a 3-state AND gate circuit, gate circuit 516 is a 3-state inverter circuit, gate circuits 517 to 519 are inverter circuits, Gate circuit 520 is a NAND gate circuit, and circuit 521 is a clock adjustment circuit.

In the circuit of FIG. 4, the timer counter 50
1. The inverter circuit 518 and the flip-flop 502 constitute display inversion means, and the flip-flop 503 constitutes display return means.

By using the circuits of FIGS. 1, 3, and 4, the operations described below are performed.

1 [When a tuning operation is performed with priority given to the clock display, the frequency is displayed during tuning and for a certain period of time (T seconds) after the operation is released, and then the clock is displayed.] For example, while the tuning switch 331 is closed. , the operation holding circuit 43 holds that state, and the output of the gate circuit 511 becomes "0" and the gate circuit 5
14, the timer counter 501 is reset, and the clear input signal of the instruction signal output circuit 509 becomes "1" through the gate circuit 516.
The instruction signal output circuit 509 is cleared and the output signal of the instruction signal output circuit 509 becomes "0" to instruct frequency display.

When the channel selection switch 331 is opened, the output of the operation holding circuit 43 becomes "1" and the timer counter 50
1 output signal “0” is the flip-flop circuit 50
2 is input to the instruction signal output circuit 509 via the gate circuit 513 and flip-flop circuit 503, and the output of the instruction signal output circuit 509 is "0".
will appear, indicating the frequency display. timer counter 5
This state continues until the timer counter 501 finishes counting (T seconds), and the output signal "1" of the timer counter 501 is output from the flip-flop circuit 502 and the gate circuit 51.
3. Input to the instruction signal output circuit 509 via the flip-flop circuit 503, and input to the instruction signal output circuit 5
The output of 09 becomes "1" and instructs clock display.

2 [Clock display is always displayed even if the clock adjustment operation is performed with priority to the clock display] When the clock adjustment switch in the clock adjustment circuit 521 is closed, the output of the clock adjustment circuit 521 becomes "0", and the gate circuit 517 and the gate circuit 5
22, the preset input signal of the instruction signal output circuit 509 becomes "1", and the instruction signal output circuit 509
09 is preset and the output signal becomes "1", instructing clock display. However, since the gate circuit 515 is in a prohibited state, the timer counter 501 is not reset.

3 [When the recall switch is closed with priority given to the clock display, the frequency is displayed for a certain period of time (T seconds) while the recall switch is closed and after the recall switch is opened, and then the clock is displayed.] When the recall switch 341 is closed, the gate circuit 519 is The timer counter 501 is reset. Output signal of timer counter 501 “0”
is inputted to the instruction signal output circuit 509 via the output of the flip-flop circuit 502, the gate circuit 513, and the flip-flop circuit 503, and the output of the instruction signal output circuit becomes "0" to instruct frequency display. This state continues while the recall switch is closed and the timer counter 501 is counting (for T seconds).
When the timer counter 501 finishes counting and the output of the timer counter 501 becomes "1", the output is inputted to the instruction signal output circuit 509 via the output of the flip-flop circuit 502, the gate circuit 513, and the flip-flop circuit 503, and outputs the instruction signal. The output of circuit 509 becomes "1" and instructs clock display.

4 [If the recall switch is closed again during the period in which a low-priority display is being performed for a predetermined period of time, a high-priority display will be performed from the moment the recall switch is closed] When the circuit is closed, the timer counter 50
1 is reset and outputs a signal "0". Then, due to the output "0" of the timer counter 501, the Q output and output of the flip-flop circuit 502 become "1" and "0", respectively.

One of the Q output (signal "1") and the output (signal "0") of this flip-flop circuit 502 is output to the gate circuit 5 according to the state of the display priority switch 343.
12 or 513 to the flip-flop circuit 503.

The flip-flop 503 inverts and latches the input for the trigger signal, and a signal "1" or "0" is input to the instruction signal output circuit 509 to instruct the display priority switch 343 to perform a corresponding display.

The flip-flop circuit 502 and the flip-flop circuit 503 latch the signal "1" or "0" while the timer counter 501 is counting,
When counting is completed, the latch is released.

In this way, by operating the recall switch again while a low-priority display is being performed, the display is immediately switched to a high-priority display, so even before the low-priority display ends, Displays can be easily switched, further improving operability.

5 [If the clock adjustment operation is performed with frequency display priority, the clock is displayed for T seconds during the clock adjustment and after the clock adjustment is completed, and then the frequency is displayed] While the clock adjustment switch in the clock adjustment circuit 521 is closed, the clock is The output of the adjustment circuit 521 becomes "0", the timer counter 501 is reset through the gate circuit 515, and the preset input of the instruction signal output circuit 509 becomes "1" through the gate circuit 517 and gate circuit 522.
The instruction signal output circuit 509 is preset and the output signal becomes "1", instructing clock display. This state continues while the clock adjustment switch is closed, and when the clock adjustment switch is opened, the clock adjustment circuit 521
The output of the timer counter 501 becomes "1", and the output signal "0" of the timer counter 501 is transmitted to the gate circuit 518, the Q output of the flip-flop circuit 502, the gate circuit 512,
It is input to the instruction signal output circuit 509 via the flip-flop circuit 503, and the instruction signal output circuit 509
The output becomes "1" and instructs the clock display. This state continues until the timer counter 501 finishes counting (T seconds). When the timer counter 501 finishes counting, the output "1" of the timer counter 501 is output to the gate circuit 518 and the flip-flop circuit 502.
A signal "0" is inputted to the instruction signal output circuit 509 through the Q output of the Q output, the gate circuit 512, and the flip-flop circuit 503, and the output of the instruction signal output circuit 509 becomes "0" to instruct frequency display.

6 [Frequency display is always displayed even if selection operation is performed with frequency display priority] For example, while the channel selection switch 331 is closed, the instruction signal output circuit 509 is cleared, and the instruction signal output circuit 509 outputs "0". to instruct the frequency display. However, since the gate circuit 514 is in a prohibited state, the timer counter 501 is not reset. This state continues while the channel selection switch 331 is closed, and when the channel selection switch 331 is opened, the output signal "1" of the timer counter 501 is output from the gate circuit 518, the Q output of the flip-flop circuit 502,
Gate circuit 512, flip-flop circuit 503
After that, "0" is input to the instruction signal output circuit 509, and the output of the instruction signal output circuit 509 becomes "0" to instruct frequency display.

7 [When the recall switch is closed with priority given to frequency display, a clock is displayed for T seconds while the recall switch is closed and after the recall switch is opened, and then the frequency is displayed.] When the recall switch 341 is closed, the timer counter 501 passes through the gate circuit 519. is reset. Output “0” of timer counter 501
are gate circuit 518 and flip-flop circuit 50
The Q output of 2 is input to the instruction signal output circuit 509 via the gate circuit 512 and flip-flop circuit 503, and the output of the instruction signal output circuit 509 is "1".
will appear and instruct the clock display. Recall switch 3
This state continues while the 41 circuit is closed and the timer counter 501 is counting, and when the timer counter 501 finishes counting (T seconds), the output "1" of the timer counter 501 is output from the gate circuit 518, the Q output of the flip-flop circuit 502, the gate circuit 512, Instruction signal output circuit 50 via flip-flop circuit 503
The output of 9 becomes "0" and instructs frequency display.

8 [When switching from clock display priority to frequency display priority, frequency display is performed from the moment of switching] When the display priority changeover switch 343 is switched from the OFF state to the ON state, the gate circuits 512 and 51
A signal "0" is given to the control terminal of No. 3, the gate circuit 512 enters the passing state, and the gate circuit 51
3 is prohibited.

On the other hand, in response to the switching of the display priority switching switch 343, a pulse of "1" is selected from the display priority switching detection circuit 504 and passes through the gate circuit 520 to reset the timer counter 501.

Note that if the timer counter 501 is already counting due to processing such as changing the frequency, the gate circuit 50
Since the output of timer 2 remains "1", timer counter 501 is not reset again.

The output "0" of the timer counter 501 is input to the flip-flop circuit 502 through the gate circuit 518, and the Q output temporarily becomes "1", but immediately after that, a trigger pulse given through the delay circuit 524 causes the gate circuit 518 The Q output signal "1" is inverted to "0" and then latched, and the latched result is outputted from the Q output to the gate circuit 512.

Then, as the timer counter 501 finishes counting, the flip-flop 502 is released from the latch state. At this time, since the output of the timer counter 501 is "1", the flip-flop circuit 50
The Q output of 2 remains "0".

This output signal "0" is the gate circuit 5 in the passing state.
12. Input to the instruction signal output circuit 509 via the flip-flop circuit 503 and input to the instruction signal output circuit 5
The output of 09 becomes "0" and instructs frequency display.

9 [When switching from frequency display priority to clock display priority, the clock display is performed from the moment of switching] When the display priority changeover switch 343 is switched from the on state to the off state, the gate circuits 512, 51
A signal "1" is given to the control terminal of gate circuit 512, and the gate circuit 512 becomes inhibited.
3 becomes a passing state.

On the other hand, in response to the switching of the display priority switching switch 343, a pulse of "1" is selected from the display priority switching detection circuit 504 and passes through the gate circuit 520 to reset the timer counter 501.

Note that if the timer counter 501 is already counting due to the time change process, the output of the gate circuit 502 remains "1", so the timer counter 5
01 is not reset again.

The output "0" of the timer counter 501 is input to the flip-flop circuit 502 through the gate circuit 518, and the Q output temporarily becomes "1", but immediately after that, a trigger pulse given through the delay circuit 524 causes the gate circuit 518 The Q output signal "1" is inverted to "0" and then latched, and the latched result is outputted from the Q output to the gate circuit 512.

Then, as the timer counter 501 finishes counting, the flip-flop circuit 502 is released from the latch state. At this time, since the output of the timer counter 501 is "1", the Q output of the flip-flop circuit 502 remains "0" and the output is also "1".

This output signal "1" is input to the instruction signal output circuit 509 via the gate circuit 513 in the pass state and the flip-flop 503, and is input to the instruction signal output circuit 509.
The output of 9 becomes "1" and instructs clock display.

10 [The clock is displayed when the radio receiver power is cut off] When the radio receiver power is cut off by the switch 342, the signal passes through the gate circuit 522 to the preset input PSET of the instruction signal output circuit 509.
is set to "1", and the signal output circuit 509 is preset to instruct clock display regardless of the operation of the channel selection switch. At this time, even if the tuning switch is operated, it has no effect because the gate circuit 516 is in the inhibited state.

11 [When changing the band and turning on the power of the radio receiver, the frequency is displayed for T seconds, and thereafter the display is performed according to the display priority. ] When the band is switched by the band switching switch 351 or the radio receiver power switch 342 or the radio receiver is powered on, a pulse signal based on the switching is applied to the time limit circuit 510. The timer circuit 510 operates at gates 512 and 51 for a predetermined time.
5 is enabled, thereby the pulse signal is applied to the timer counter 501 via the gate circuit 515, the timer counter 501 is reset, and a signal "0" is output.

As a result, the Q output of flip-flop 502 becomes "1", and a signal "1" is applied to instruction signal output circuit 509 via gate 512 and flip-flop 503, thereby performing frequency display.

Thereafter, when the timer circuit 510 is opened and the timer counter 501 has finished counting, a display according to the display priority changeover switch 343 is performed.

In addition to the above-mentioned matters, the first, third and fourth
In the circuit shown in the figure, when the operation switches on the channel selection side and the watch side are pressed simultaneously, the operation on the channel selection side can be configured to take priority over the operation on the watch side.

〔Effect of the invention〕

According to the present invention, in response to an operation of a recall switch to display something opposite to what is currently displayed, the display means displays a display with a low priority for a predetermined period of time, and displays the display with a low priority. If the operation of the recall switch is detected while the switch is on, the display is immediately returned to the one with the highest priority, thereby ensuring that the display switching operation faithfully responds to the user's various requests, avoids erroneous operations, and ensures proper display switching. It will be done.

In addition, in this case, after operating the recall switch to display a low-priority display for a certain period of time, by operating the recall switch again, a high-priority display can be displayed immediately, improving operability. A device that can be used

[Brief explanation of drawings]

FIG. 1 is a basic circuit diagram of a radio receiver to which a display control device as an embodiment of the present invention is applied, FIG. 2 is a diagram showing a display device in the circuit of FIG. 1, and FIGS. 3A and B are FIG. 2 is a circuit diagram showing a specific configuration of the circuit, and FIG. 4 is a detailed circuit diagram of a display control circuit in the circuit of FIG. 1...Radio receiving circuit, 11...Receiving input circuit, 1
2... Phase locked loop synthesizer, 13... Low pass filter, 14... Radio output circuit, 15... Speaker, 2... Tuning circuit, 21... Signal generator, 22... Data selector, 23... Decoder circuit, 241-2
44...Counter, 25...Random access memory, 26...Read/write control circuit, 27...Read only memory, 28...Comparator, 29...
Long/medium wave selection circuit, 311, 312...Manual lowering/
Up switch, 313, 314... Search down/up switch, 32... Write (memory) switch, 33
1, 33n...Channel selection switch, 341...Recall switch, 342...Receiver power switch,
343...Clock/frequency priority display switch, 3
51,352...Band selection switch, 41,42,
43...operation holding circuit, 44...band selection circuit, 5...
Display control circuit, 501... timer counter, 50
2,503...Flip-flop circuit, 509...Instruction signal output circuit, 510...Flip-flop circuit, 511-520...Gate circuit, 521...Clock adjustment circuit, 524...Delay circuit, 525...Radio receiver power supply opening/closing detection circuit, 526...Display Priority switching detection circuit, 6... Frequency calculation circuit, 7... Clock counting circuit, 8... Display signal selection circuit, 9... Display device, 91
...Display figure.

Claims (1)

[Claims] 1. Display means 9 for displaying time or frequency;
A radio switch 342 for operating the radio, a time display and a frequency display are given priority, and the display means normally displays the time or frequency, which has a higher priority, and at least when the radio switch is operated. is a manual operation recall for displaying a time display and a frequency display in an in-vehicle radio receiver having a frequency display function of a watch and a radio receiver section, which is equipped with a display control means 5 that displays a frequency. switch 341
and display reversing means 501, 518, 502 for causing the display means to display the low priority display for a predetermined period of time when an operation of the recall switch is detected while displaying the high priority display; A clock and radio receiving unit comprising: a display return means 503 for immediately returning to a high priority display when an operation of the recall switch is detected while a low priority display is being performed by the display means. Radio receiver with frequency display function.