JPH0510752B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a reading speed adjusting device for adjusting the information reading speed of a recorded information reproducing device.

BACKGROUND ART Conventionally, some recorded information reproducing apparatuses such as video disk players, CD players, and tape decks are capable of changing the information reading speed within a predetermined range to set a desired performance speed. In such devices, a desired playing speed is obtained by turning a so-called pitch control knob. For example, in a digital audio disk player, the reproduction clock extracted from the read signal is compared with the basic clock. Since the digital signal is demodulated while functioning as a spindle servo, if the pitch control knob is turned too quickly, the spindle servo will not be able to follow the frequency changes of the basic clock, making it impossible to synchronize the reproduced clock with the basic clock signal. Therefore, a problem may arise in that the digital signal is not demodulated.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a reading speed adjusting device that prevents out-of-synchronization in the reproduction system even if the pitch control is rapidly rotated.

In order to achieve the above object, the reading speed adjusting device of the present invention uses a delay means to gradually change the reading speed command signal indicating the performance speed set by the operation, so that the rate of change of the signal is kept constant. The configuration is such that the clock signal is maintained below this value and supplied to the basic clock signal generation circuit.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG.

FIG. 1 shows an embodiment in which the present invention is applied to a CD player. In a CD player, a laser diode (not shown) in a pickup 2 irradiates a laser beam onto a track consisting of a row of pits on a disk 1 on which music information etc. are recorded, and the reflected light of the laser beam is transmitted to a photodetector (not shown) in the pickup 2. (not shown). In order to properly irradiate the laser beam, the pickup 2 includes an objective lens, a focusing actuator, a tracking actuator, etc., but these will not be described in detail here.
The output from the pick-up 2 is a focusing error generation circuit 3, a tracking error generation circuit 4,
The signal is supplied to a data reading circuit 5 and a reproduced clock generation/phase comparison circuit 6.

A focusing error generation circuit 3 and a tracking error generation circuit 4 generate a focusing control signal and a tracking control signal, respectively, from the output of the photodetector. The focusing control signal is amplified by the focusing amplifier 7 and drives the focusing actuator of the pickup 2. Further, the tracking control signal is amplified by the tracking amplifier 8 to drive the tracking actuator. In this way, a focus servo and tracking servo system is formed.

The reproduced clock generation/phase comparison circuit 6 extracts the clock component from the output of the photodetector, and
The phase of this clock component and the supplied basic clock signal are compared, and a difference output corresponding to the phase difference is supplied to the drive amplifier 9. The drive amplifier 9 increases or decreases the rotation of the spindle motor 10 according to the differential output. Then, spindle servo is performed so that the phase and frequency of the clock component match the basic clock signal, that is, so that the difference output becomes zero.

The clock component is also supplied to the data reading circuit 5. The data reading circuit 5 demodulates the digital music information signal from the output of the photodetector based on the clock component. This music information signal undergoes error correction by an error correction circuit 11 and is supplied to a D/A converter 12.
The D/A converter 12 converts the music information signal into an analog signal and supplies it to the low-pass filter 13. Error correction circuit 11 and D/A converter 1
2 operates in synchronization with the basic clock signal.
The low-pass filter 13 smoothes the analog signal and outputs it as an audio signal.

The basic clock signal mentioned above is supplied from the basic clock generation circuit 14. The basic clock generation circuit 14 uses, for example, a variable capacitance diode.
Formed by VCO. Then, a basic clock signal having a frequency corresponding to, for example, a voltage signal corresponding to the reading speed supplied from the basic clock changing circuit 15 is generated.

The basic clock generation circuit 14 and the basic clock change circuit 15 are formed by a reading speed command circuit 20 that sets the reading speed, a delay circuit 21 that makes the signal level change more gradual, and a VCO 22. An example of the circuit will be explained with reference to FIG. First, the reading speed command circuit 20
I will explain about it.

The reading speed command circuit 20 is connected to the bias power supply V _CC
It is formed by a resistive voltage divider circuit with a variable resistor V _R connected between and ground. This resistance-divided voltage output set according to the desired performance speed is supplied to the delay circuit 21 as a reading speed command signal via a slider.

The delay circuit 21 is formed by a charging/discharging circuit in which a resistor R ₁ and a capacitor C ₁ are connected in series, and the output voltage of the resistor voltage dividing circuit is applied to the other end of the resistor R ₁ . Further, the other end of the capacitor _C1 is grounded. The voltage at the connection point between the resistor R ₁ and the capacitor C ₁ is applied to the variable capacitance diode VD of the VCO 22 via the coupling resistor R ₂ . Capacitor _C1 charges and discharges according to the applied voltage with a time constant determined by resistor _R1 and capacitor _C1 , so even if the slider is suddenly rotated, the variable capacitance diode
Changes in the voltage applied to VD are suppressed and change slowly, and the rate of change of this voltage is suppressed to below a certain value.

Furthermore, the configuration of the VCO 22 will be explained. A transistor Q ₁ and an emitter resistor R ₅ are connected in series between the bias power supply V _CC and ground, and base bias resistors R ₃ and R ₄ are connected in series. The connection point of resistors R ₃ and R ₄ is connected to the base of transistor Q ₁ . A capacitor between this base and ground
C ₂ and C ₃ are connected in series. The junction of capacitors C ₂ and C ₃ and the emitter of transistor Q ₁ are connected. The output of this emitter is supplied to a buffer amplifier 23 via a coupling capacitor _C4 , and a basic clock signal is output from the output terminal of the buffer amplifier 23. The base of the transistor Q ₁ is connected to a coupling resistor R ₂ and one end of a variable capacitance diode VD via a coupling capacitor C ₅ . The other end of this variable capacitance diode VD is grounded via an inductor L. Inductor L and variable capacitance diode
VD and capacitors C ₂ , C ₃ and C ₅ constitute a resonant circuit of the transistor oscillation circuit. Then, the oscillation frequency changes depending on the voltage applied to the variable capacitance diode VD, and the frequency of the basic clock signal changes.

With this configuration, even if the output level of the reading speed command circuit 20 changes rapidly,
Since this level change is gently adjusted by the delay circuit 21 and supplied to the VCO 22, the frequency change of the basic clock signal becomes gradual.
Since the spindle servo system operates in full accordance with the basic clock signal, it is possible to suppress the synchronization between the clock component of the read digital signal and the basic clock signal.

Furthermore, FIG. 3 shows another embodiment of the present invention.
In the figure, when the phase difference output of the reproduced clock generation/phase comparator circuit 6 exceeds a certain value, the absolute value circuit 24 gradually decreases the collector-emitter resistance of the transistor Q ₂ as shown in FIG. This limits the output of the delay circuit 21. In this way, it is possible to accelerate the response of the output of the delay circuit 21 to the point where the spindle servo system becomes unlocked. Such a circuit can be realized using a microprocessor, for example, with a circuit configuration as shown in FIG. In this case, the output value of the microprocessor is increased or decreased step by step according to a programmed procedure up to a predetermined value corresponding to the value input from the keyboard, and also according to the level of the phase difference output. The output value is selected accordingly. And similar effects can be obtained.

In the embodiment, the delay means is configured electrically, but it is also possible to configure it mechanically. For example, a spring, a viscous resistance, a braking piece, etc. are combined on the rotating shaft of the variable resistance VR to form a slow motion structure in which the slider rotates slowly. Further, the variable capacitor or variable inductor that sets the oscillation frequency of the oscillation circuit that outputs the basic clock signal may be operated slowly by, for example, the structure described above.

Furthermore, it is clear that the present invention can be applied to any recorded information reproducing apparatus that is of a type that obtains clock information from recorded information on a recording medium.

The reading speed command signal described above is not limited to a voltage signal.

Effects of the Invention As explained above, in the reading speed adjusting device of the recorded information reproducing apparatus of the present invention, a delay means is provided to gradually change the reading speed command signal and supply it to the basic clock signal generating means. This structure is preferable because even if the pitch control for setting the playing speed is operated quickly, the sound does not break up and the operation is stable, and the structure is inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the recorded information reproducing apparatus of the present invention, FIG. 2 is a diagram showing a specific circuit of the basic clock generation circuit and basic clock changing circuit of FIG. 1, and FIG. A circuit diagram showing another embodiment. FIG. 4 is a circuit diagram showing an example in which the circuit shown in FIG. 3 is constructed by a microprocessor. 6...Regenerated clock generation/phase comparison circuit, 14
...Basic clock generation circuit, 15...Basic clock change circuit, 20...Reading speed command circuit, 2
1...Delay circuit, 22...VCO.

Claims (1)

[Claims] 1. An information signal recorded on an information recording medium is read and a clock signal contained therein is extracted to obtain a reproduced clock signal, and the reproduced clock signal is determined based on the phase difference between the reproduced clock signal and the basic clock signal. A read speed adjustment device for a recorded information reproducing apparatus that demodulates the information signal at a read speed corresponding to the basic clock signal while performing servo in the reading time axis direction, the read speed having a level corresponding to a desired read speed. A reading speed command means for generating a command signal, a delay means for slowing a level change of the reading speed command signal, and a basic clock for generating a pulse signal of a frequency corresponding to the output of the delay means as the basic clock signal. 1. A reading speed adjusting device for a recorded information reproducing device, comprising: signal generating means. 2. The reading speed adjusting device for a recorded information reproducing device according to claim 1, wherein the delay means is formed by a charging/discharging circuit.