JPH0512751B2 - - Google Patents

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a method for controlling the execution start timing of a subsequent instruction in a vector processing device when the processing result of a preceding instruction is used as an input operand of the subsequent instruction. Regarding.

(b) Technical Background A vector processing device processes a second operand A that has a plurality of unit data that are elements of a vector.
= a0, a1, ..., ai, ..., a _o-1 , and the third operand B having multiple unit data = b0, b1, ...
..., bi, ..., b _o-1 and the first operand C = c0,
Its basic function is to obtain c1, ..., ci, ..., c _o-1 . For example, vector operation C=A+
B consists of unit data calculation ci=ai+bi repeated n times.

Such operations are performed in the vector processing device as execution of vector instructions. A vector instruction generally has an instruction code, a first operand specification part, a second operand specification part, and a third operand specification part; for example, "VM1, 2, 3" is
This is a vector multiplication instruction that specifies that the contents of vector register 2 and vector register 3 are multiplied and the result is stored in vector register 1.

(c) Prior art and problems Figure 1 shows an example of a vector processing device.
The vector processing device 200 is connected to the main storage device 1 via the main storage control device 2 and processes data on the main storage device, but the data to be processed is stored in the main storage device 1 and the vector register storage device 4. The direct target of the operation is the data in the storage device 4. This data transfer is processed by the load processing section 7 and the store processing section 8.
Calculations are performed by the adder 9 and multiplier/divider 10 of the arithmetic processing unit 6.
Processed by The command control section 5 controls each of the above sections.

In order to execute vector instructions at high speed, a load processing unit 7, a store processing unit 8, an adder 9, a multiplier/divider 1
0, etc. can operate in parallel, and multiple instructions are executed in parallel using a so-called pipeline control method. In such a vector processing device, when a certain instruction is followed by a subsequent instruction that uses its execution result as an input operand (this situation is called register interference), the start of the subsequent instruction is delayed by the execution of the preceding instruction. Special considerations are required to synchronize the state. An improved system for controlling the initiation of subsequent commands in such cases is disclosed in Japanese Patent Application Laid-Open No. 57-206982, ``Instruction Control System'', published by the same applicant.

FIG. 2 shows the timing when executing the multiplication instruction VM and addition instruction VA by applying the present invention. In the figure, IF represents an instruction fetch, D represents an instruction decode, Q represents a waiting phase, and E represents an instruction execution phase. As shown in the figure, a write flag signal is output from the executing instruction management unit when writing of unit data of the execution result of the preceding instruction is started, and if other conditions are met, the write flag signal is output.
A flag signal initiates a subsequent instruction. This allows the resources of the vector processing device to be used effectively.

However, the method shown in Figure 2 does not work if there is a stage in the pipeline of the preceding instruction that takes a long processing time, and therefore the writing speed of the result is slower than the reading speed of the same data by the subsequent instruction. Not applicable. Therefore, in the conventional case of such a combination, it is necessary to wait for the completion of execution of the preceding instruction before starting the subsequent instruction, which increases the idle time of the resources of the vector processing device.

(d) Object of the Invention Therefore, in view of the above-mentioned problems in vector processing devices, the object of the present invention is to provide a method for processing when the processing speed of the preceding instruction is slower than the processing speed of the subsequent instruction.
The object of the present invention is to provide an improved method for increasing the parallelism of execution of both instructions.

(e) Structure of the Invention An object of the present invention is to provide a storage device that sequentially accesses a plurality of ordered unit data in a fixed order, and a first calculation unit and a second calculation unit that process the data in the storage device. The second arithmetic unit processes each of the unit data in the access order in a processing time equal to the access cycle of the storage device, and the first arithmetic unit requires an integer X times the processing time of the second arithmetic unit. , in a vector processing device that processes unit data by treating only one access for each unit data of the column as a valid access among X repeated accesses to the same unit data column of the storage device, A second instruction is executed following the first instruction, the first instruction is executed using the first arithmetic unit, and the second instruction is executed using the first operation unit.
The Xth time for storing the processing result data of the first instruction in the storage device when the data in the storage device which is the processing result of the instruction is used as an operand and is executed using the second arithmetic unit. The second instruction is configured to start executing the second instruction after the first access start of the unit data to be repeatedly accessed and before the start of storage processing of the final unit data of the processing result. This is achieved by a command control method characterized by:

(f) Embodiments of the Invention Embodiments of the present invention will be described below, but before that, the configuration of a vector register storage device 4 suitable for application of the present invention will be briefly described.

Such a storage device consists of a plurality of banks (bank 1 is shown in the figure), as schematically illustrated in FIG.
Example of 8 banks from 00 to 107), address circuit 1
By selecting 1 from addresses 0 to M-1 using 4, unit data of all banks belonging to the address can be accessed. In that case, each bank receives 100% of the data from 100 to
7 is accessed in order. The bank to be accessed is selected by selectors 120 and 121. 1
10 is a control circuit for the storage device.

In such a storage device, an access control method when the throughput (amount of data that can be input/output per time) of the access source 6 is smaller than the throughput of the storage device is disclosed in a patent application filed by the same applicant (Japanese Patent Application No. 59-20313). No.) ``Storage Device Access Control Method''. According to this, the throughput of the access source is 1/X that of the storage device.
An integer X that is larger is selected, and the sequential bank access performed as described above is repeated X times. During this time, by accessing only once every X times as a valid access, all banks can be accessed with a throughput of 1/X.

As the most preferred embodiment of the present invention, an instruction control system for a vector processing device using the above storage device as the vector register storage device 4 will be described.

FIG. 4 shows a command control device. The vector instruction fetched from the main memory 1 is set in the instruction fetch D register 11. This instruction is decoded by decoder 12. The decoded instruction information is set in the waiting Q register 13. The instruction transmission control circuit 14 includes a Q register 13 and an executing instruction management section 15-1 or 15-2.
Based on the information from the
If it is possible to make a call, the vacant executing command management unit 1
The instruction information in the Q register 13 is transferred to 5-1 or 15-2.

The executing instruction management unit 15-1 is for executing instructions.
It has an E1 register 16-1, a counting circuit 17-1, and a write flag 18-1. E1 register 1
In 6-1, instruction information to be executed by the corresponding arithmetic processing section is set. Counting circuit 17-1 is E1
Time counting is started when the instruction information is set in the register 16-1, and when the time determined by the instruction information has been counted, the write flag 18-1 is set on. The executing instruction management unit 15-2 is also 15-
It has the same configuration as 1.

The command transmission control circuit 14 determines whether the arithmetic processing unit and the executing command management unit to which the command is transmitted are vacant.
It is determined whether the command can be issued based on whether there is any interference with the vector register of the command operand, whether the write flag is on, etc. Here, vector register interference refers to a state in which the above-mentioned register interference occurs in the registers on the vector register storage device. If this interference is detected, a write request will be made for the preceding instruction, even if other conditions are met.
The command transmission is waited until the flag 18-1 or 18-2 is turned on.

FIG. 5 shows an embodiment of a register interference check circuit within the instruction generation control circuit 14. The illustrated circuit corresponds to the executing command management unit 15-1, and the command transmission control circuit 14 is provided with another set of similar circuits corresponding to the executing command management unit 15-2.

In the figure, the write flag signal is a signal from the write flag 18-1, and the other input signals are operand register number information of the instruction information in the E1 register 16-1 and Q register 13, respectively.

The first operand register number of the E1 register,
In other words, the result storage destination register number of the instruction being executed, and Q
When the second or third operand register number of the register matches, the "1" output of the respective comparator circuit 19 or 20 is input to the AND gate 21 or 22. At this time, if the write flag signal input to the NOT circuit 23 is "0", the gate 21 or 2
At least one output of 2 becomes "1", and the command transmission wait signal becomes "1" through the OR gate 24. Under other conditions, the command transmission wait signal is "0". In the command transmission control circuit 14, while the command transmission wait signal is "1", transmission of the waiting command in the Q register 13 is suppressed.

FIG. 6 shows an example of vector instruction execution according to the present invention. The figure shows a case where the following two instructions are to be executed in the following order.

VD 1, 2, 3 VA 4, 5, 1 Here, the VD instruction executes division between the vectors of vector register number 2 and number 3, and stores the result in vector register number 1. Yes, the VA instruction is vector register number 5
This instruction executes addition between the vectors 1 and 1 and stores the result in vector register number 4. Therefore, there is register interference in register number 1 between both instructions.

In addition, the instruction holds the arithmetic circuit for 5 cycles in the division of each vector element,
For this reason, the input/output of unit data between the vector register storage device 4 and the arithmetic unit 6 is executed with one valid access every five cycles according to the method of the aforementioned patent application (Japanese Patent Application No. 59-20313). .

FIG. 6 shows the flow of time from left to right, and the diamonds represent the progress of the stages of each instruction execution pipeline as a flow from top to bottom. IF,D,
The meanings of symbols such as Q and E are the same as in Figure 2.
The lowest stage in the VD instruction flow is the stage where the operation result is stored in the vector register storage device, and the number indicates the number of the storage device bank accessed in each cycle. Among these, the bank whose number is surrounded by □ is valid. Indicates that it will be accessed as an access. In this example, the vector is composed of eight unit data, and the same address in the storage device is accessed five times, and eight data are input/output through a total of 40 cycles of access.

On the other hand, in the vector addition instruction VA, all stages of the pipeline advance in one cycle, so data can be input/output to/from the vector register storage device 4 every cycle, and all data can be input/output in eight cycles.

When the VD instruction is set in the E1 register 16-1, the counting circuit 17-1 starts counting time, and is incremented by 1 every cycle, and when the counted value reaches the set value,
The write flag 18-1 is turned on (“1”).
Therefore, the write flag signal shown in FIG. 5 becomes "1" and the command transmission wait signal becomes "0", so that in the command transmission control circuit 14, the VA instruction in the Q register 13 is transferred to the E2 register for executing instructions. 16-2, and execution of the VA instruction is started.

In the above, the setting value of the counting circuit 17-1 is
In an access control method in which each bank of the vector register storage device 4 is accessed repeatedly X times, a setting is made to determine the start point of the X-th access. Therefore, when using a counting circuit that counts up every cycle as described above, the set value is N(X-1), where the number of banks is N and the number of repeated accesses is X, which is the first value from the start of instruction execution. It is determined by the time it takes to store the results. If the latter value is 10 cycles, the set value in this example is 8×(5-1)+10=42.

(g) Effects of the Invention As is clear from the above description, according to the present invention, when there is register interference and the preceding vector instruction requires a longer processing time than the subsequent vector instruction, the execution start time of the subsequent instruction can be determined. , it is possible to advance the execution to before the completion of the preceding instruction.
It is possible to increase the parallelism of execution of the vector processing device and thus improve the processing performance of the device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an overview of a vector processing device, FIG. 2 is a diagram showing an example of conventional instruction sequence processing timing,
FIG. 3 is a diagram showing an example of a vector register storage device, FIG. 4 is a block diagram of an embodiment of the instruction control device of the present invention, and FIG. 5 is a diagram of an embodiment of the register interference check circuit in the instruction generation control circuit. Block diagram, No. 6
The figure is a diagram showing an example of instruction sequence processing timing of the present invention. In the figure, 200 is a vector processing device, 1 is a main storage device, 2 is a main storage control device, and 3 is a memory controller.
Access processing unit, 4 is a vector register storage device, 5 is an instruction control unit, 6 is an arithmetic processing unit, 11 is a D register for instruction fetching, and 13 is a Q for waiting.
register, 14 is an instruction transmission control circuit, 15-1 and 15-2 are executing instruction management units, 16-1 and 1
6-2 are E1 and E2 registers for instructions being executed, 17-1 and 17-2 are counting circuits, 18-1
and 18-2 are write flags, 19 and 20 are comparison circuits, 21 and 22 are AND gates, 23 are NOT gates, 24 are OR gates, 100 to 10
7 is a storage device bank, and 110 is a control circuit for the storage device.

Claims (1)

[Claims] 1. A storage device that sequentially accesses a plurality of ordered unit data in a fixed order, and a first calculation unit and a second calculation unit that process data in the storage device, and a second calculation unit that processes data in the storage device. The arithmetic unit processes each of the unit data in the access order in a processing time equal to the access cycle of the storage device, and the first arithmetic unit requires an integer X times the processing time of the second arithmetic unit; In a vector processing device that processes unit data, with only one access for each unit data in the column being a valid access among the X number of repeated accesses to the same unit data column, Then execute the second command and
When the instruction is executed using the first arithmetic unit, the second instruction uses data in the storage device which is the processing result of the first instruction as an operand, and is executed using the second arithmetic unit, Storage of the final unit data of the processing result after the start of the first access of the unit data for performing the X-th repeated access for storing the processing result data of the first instruction in the storage device An instruction control method characterized by being configured to start execution of a second instruction before the start of processing.