JPH0513559B2 - - Google Patents
Info
- Publication number
- JPH0513559B2 JPH0513559B2 JP19416786A JP19416786A JPH0513559B2 JP H0513559 B2 JPH0513559 B2 JP H0513559B2 JP 19416786 A JP19416786 A JP 19416786A JP 19416786 A JP19416786 A JP 19416786A JP H0513559 B2 JPH0513559 B2 JP H0513559B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- board
- layer
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010410 layer Substances 0.000 claims description 51
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 239000000919 ceramic Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229920001721 polyimide Polymers 0.000 claims description 10
- 239000009719 polyimide resin Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 16
- 229910052737 gold Inorganic materials 0.000 description 16
- 239000010931 gold Substances 0.000 description 16
- 238000007747 plating Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920006332 epoxy adhesive Polymers 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、コンピユータ等の電子機器に使用す
るのに適する多層回路基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a multilayer circuit board suitable for use in electronic equipment such as computers.
従来この種の多層回路基板には、装置の処理能
力の高速化を達成するため、配線の高速化と高密
度化にたいする努力がなされて来た。具体的に
は、高速化については、誘電率の低い有機樹脂な
どを絶縁材に使用したり、銅などの低抵抗の導電
材を使用し、高密度化について、配線パターンの
微細化、もしくは、配線層の高多層化を進めて来
た。（例えば、日経エレクトロニクス1984年８月
27日号P145〜P159、日経エレクトロニクス1985
年６月17日号P243〜P266）
〔解決すべき問題点〕
上記従来の多層回路基板における配線パターン
の微細化には、配線の断面積が小さくなるため、
導体抵抗が高くなり配線の高速化を阻害すると言
う欠点があつた。また、配線層の高多層化には、
全層をセラミツク・グリーンシートと厚膜印刷配
線の同時焼成で行う方法があるが、セラミツクの
比誘電率が低くないために配線の高速化には不適
当である。一方、有機樹脂を層間絶縁に用いて高
多層配線を形成した場合にはセラミツク基板上
に、配線層を下層より順次形成して行かねばなら
ず、製造日数が多くなり、設計変更に対する迅速
な対応ができない事と、製造コストが高くなると
言う欠点があつた。
Conventionally, efforts have been made to increase the speed and density of wiring in this type of multilayer circuit board in order to achieve faster processing performance of the device. Specifically, to increase speed, use organic resin with a low dielectric constant as an insulating material, use a low-resistance conductive material such as copper, and increase density by miniaturizing wiring patterns. We have been increasing the number of interconnect layers. (For example, Nikkei Electronics August 1984
27th issue P145-P159, Nikkei Electronics 1985
(June 17, 2016 issue, P243-P266) [Problems to be solved] The miniaturization of the wiring patterns in the conventional multilayer circuit board mentioned above requires a reduction in the cross-sectional area of the wiring.
The drawback was that the conductor resistance increased, impeding high-speed wiring. In addition, to increase the number of wiring layers,
There is a method of simultaneously firing all layers of ceramic green sheets and thick film printed wiring, but this is not suitable for increasing the speed of wiring because the dielectric constant of ceramic is not low. On the other hand, when high multilayer wiring is formed using organic resin for interlayer insulation, the wiring layers must be formed sequentially from the bottom layer on the ceramic substrate, which increases the manufacturing time and requires quick response to design changes. The drawbacks were that it was impossible to do so and the manufacturing cost was high.
本発明は、上記従来の問題点に着目してなされ
たもので、積層に要する日数を短縮でき、かつ製
造欠陥に起因する損失工数を低減できる多層回路
基板の製造方法を提供せんとするものである。
The present invention has been made in view of the above-mentioned conventional problems, and aims to provide a method for manufacturing a multilayer circuit board that can shorten the number of days required for lamination and reduce man-hours lost due to manufacturing defects. be.
そのために、本発明は、ポリイミド系樹脂を層
間絶縁として、セラミツク基板上に複数の配線層
を形成することにより構成される多層回路基板の
製造方法において、あらかじめ多層回路基板を下
層部を構成する第１の配線基板と、上層部を構成
する第２の配線基板とにわけ、セラミツク基板上
に下層より順次配線層を積層して第１の配線基板
を形成する第１の工程と、アルミニウム等の金属
板上に下層より順次もしくは上層より順次配線層
を積層して第２の配線基板を形成する第２の工程
と、第２の配線基板の金属板を希塩酸により溶解
除去する第３の工程と、第１の配線基板の表面に
形成された金属パツドと、第２の配線基板の表面
に形成された金属パツドとを半田付けもしくは導
電性接着剤で接着する第４の工程とを有すること
を特徴とする多層回路基板の製造方法を提供する
ものである。 To this end, the present invention provides a method for manufacturing a multilayer circuit board formed by forming a plurality of wiring layers on a ceramic substrate using polyimide resin as interlayer insulation. A first step is to form a first wiring board by laminating wiring layers sequentially from the bottom layer on a ceramic substrate, and a second wiring board constituting an upper layer. a second step of laminating wiring layers sequentially from the bottom layer or from the top layer on the metal plate to form a second wiring board; and a third step of dissolving and removing the metal plate of the second wiring board with dilute hydrochloric acid. , a fourth step of bonding the metal pads formed on the surface of the first wiring board and the metal pads formed on the surface of the second wiring board with soldering or a conductive adhesive. The present invention provides a method for manufacturing a multilayer circuit board characterized by:
以下、本発明の実施例を図面に基づいて説明す
る。
Embodiments of the present invention will be described below based on the drawings.
第１図は、本発明の第一の実施例を示す縦断面
図である。この実施例では、多層回路基板をセラ
ミツク積層配線基板１を有する下層部用の第１の
配線基板１０と、金属板としてのアルミニウム板
３０を有する上層部用の第２の配線基板４０とに
あらかじめわけている。セラミツク積層配線基板
１は、一辺15センチメートルの正方形で、厚さ
は、３ミリメートルである。このセラミツク積層
配線基板は、酸化アルミニウムを主成分とする層
間絶縁層１１と、４種の、タングステンを用いて
形成された電源配線層１２，１３，１４，１５と
が交互に積層されている。また、このセラミツク
積層配線基板１には、表裏を貫通し、あるいは、
各電源配線層と基板表面に形成された金パツド１
６，１７とを接続するための、スルーホール２０
が形成されている。スルーホール配線は、タング
ステン、もしくはモリブデンで形成されている。 FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention. In this embodiment, the multilayer circuit board is assembled in advance into a first wiring board 10 for the lower layer having a ceramic laminated wiring board 1 and a second wiring board 40 for the upper layer having an aluminum plate 30 as a metal plate. It's divided. The ceramic laminated wiring board 1 has a square shape of 15 centimeters on each side and a thickness of 3 millimeters. This ceramic laminated wiring board has an interlayer insulating layer 11 mainly composed of aluminum oxide and four types of power supply wiring layers 12, 13, 14, and 15 formed using tungsten, which are alternately laminated. In addition, this ceramic laminated wiring board 1 has a structure that penetrates the front and back sides, or
Gold pads 1 formed on each power supply wiring layer and substrate surface
Through hole 20 for connecting 6 and 17
is formed. The through-hole wiring is made of tungsten or molybdenum.
このセラミツク積層配線基板は、第１の工程に
先立つて、あらかじめ準備されているものであ
る。 This ceramic laminated wiring board is prepared in advance prior to the first step.
第１の工程では、基板１の表面に電源配線１８
を金めつきで形成し、これを覆う第１のポリイミ
ド樹脂絶縁層１９を形成し、その上に第１の信号
配線２１を金めつきで形成し、続いて第２のポリ
イミド樹脂絶縁層２２をその上に形成し、さらに
第２の信号配線２３を金めつきで形成し、続いて
第３のポリイミド樹脂絶縁層２４を形成する。最
後に、金パツド２５と電源配線２６とを金めつき
で形成して第１の配線基板１０を得る。 In the first step, power supply wiring 18 is placed on the surface of the substrate 1.
is formed by gold plating, a first polyimide resin insulating layer 19 is formed to cover this, a first signal wiring 21 is formed by gold plating thereon, and then a second polyimide resin insulating layer 22 is formed. is formed thereon, and further a second signal wiring 23 is formed by gold plating, and then a third polyimide resin insulating layer 24 is formed. Finally, the gold pad 25 and the power supply wiring 26 are formed by gold plating to obtain the first wiring board 10.
第２の工程では、アルミニウム板３０の表面に
金パツド３１を形成し、次に第４のポリイミド樹
脂絶縁層３２を形成し、続いて第３の信号配線層
３３をその上に金めつきで形成し、さらに第５の
ポリイミド樹脂絶縁層３４を形成し、続いて第４
の信号配線層３５をその上に金めつきで形成し、
これを覆う第６のポリイミド樹脂絶縁層３６を形
成する。そして、最後に金パツド３７をその上に
形成する。 In the second step, a gold pad 31 is formed on the surface of the aluminum plate 30, then a fourth polyimide resin insulating layer 32 is formed, and then a third signal wiring layer 33 is plated with gold thereon. A fifth polyimide resin insulating layer 34 is formed, and then a fourth polyimide resin insulating layer 34 is formed.
A signal wiring layer 35 is formed thereon by gold plating,
A sixth polyimide resin insulating layer 36 is formed to cover this. Finally, a gold pad 37 is formed thereon.
第３の工程では、第２の工程で用いられたアル
ミニウム板を希塩酸で溶解除去して第２の配線基
板４０を得る。この工程では図示せぬがアルミニ
ウム板３０の下面に上層より順次配線層を積層す
るようにしても良い。 In the third step, the aluminum plate used in the second step is dissolved and removed with dilute hydrochloric acid to obtain the second wiring board 40. Although not shown in this step, wiring layers may be sequentially laminated on the lower surface of the aluminum plate 30 from the upper layer.
第４の工程では、第１の工程で得られた、第１
と第２の信号配線を有する第１の配線基板１０の
表面の金パツド２５と、第３の工程で得られた、
第３と第４の信号配線を有する第２の配線基板４
０の表面の金パツド３１とを金−エポキシ系接着
剤を用いて接着することにより、第１から第４ま
での４層の信号配線と２層の電源配線１８，２６
と表層の金パツド３７の合計７層の配線層を有す
る高多層化された回路基板を得る。 In the fourth step, the first
and the gold pad 25 on the surface of the first wiring board 10 having the second signal wiring, and the gold pad 25 obtained in the third step.
Second wiring board 4 having third and fourth signal wiring
By bonding the gold pad 31 on the surface of 0 using a gold-epoxy adhesive, four layers of signal wiring from the first to fourth layers and two layers of power supply wiring 18, 26 are formed.
A highly multi-layered circuit board having a total of seven wiring layers including the gold pad 37 on the surface layer and the gold pad 37 on the surface layer is obtained.
本実施例では、第２の工程でアルミニウム板を
用いているが、これを亜鉛板に替えることも可能
である。 In this embodiment, an aluminum plate is used in the second step, but it is also possible to replace this with a zinc plate.
第２図は、本発明の第２の実施例を示す縦断面
図である。 FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention.
本実施例は、第１図に示した第１の実施例とほ
ぼ同じ構成であるが、各配線に金めつきの代りに
銅めつきを用いている点と、第２の配線基板が複
数の配線基板群５０，５１，５２，５３に分割さ
れている点と、第１の配線基板と第２の配線基板
（群）との接着に錫−鉛共晶半田を用いている点
とが異なる。 This embodiment has almost the same configuration as the first embodiment shown in FIG. 1, except that copper plating is used instead of gold plating for each wiring, and the second wiring board has a plurality of The difference is that it is divided into wiring board groups 50, 51, 52, and 53, and that tin-lead eutectic solder is used to bond the first wiring board and the second wiring board (group). .
次に本発明に係る多層回路基板の製造方法にお
ける製造欠陥に起因する損失工数について例をも
つて説明する。 Next, the loss of man-hours due to manufacturing defects in the method for manufacturing a multilayer circuit board according to the present invention will be explained using an example.
（例）１層あたり、10％の製造欠陥による廃棄品
がでる配線層を、８層、積層する場合
各層での廃棄率が等しく10％であり、各層の所
要工数も等しくＭであると仮定すれば、１枚の基
板が良品である期待値K1は、
K1＝0.98＝0.430
１枚の基板の損失工数の期待値L1は、１層目
で廃棄されるものから８層目で廃棄されるものま
での累積であるから、
L1＝8
〓n=1
（0.1×ｎ×Ｍ×0.9n-1）＝0.1M8
〓n=1
（ｎ×0.9n-1）＝2.252M
従つてこの場合の、良品基板１枚あたりの損失
工数L1／K1は、
L1／K1＝5.24M
である。(Example) When stacking 8 wiring layers in which each layer has 10% waste due to manufacturing defects. Assume that the waste rate in each layer is equal to 10%, and the number of man-hours required for each layer is also M. Then, the expected value K1 for one board being good is K1 = 0.9 8 = 0.430 The expected value L1 of lost man-hours for one board is from the one discarded at the 1st layer to the one discarded at the 8th layer. Since it is the accumulation up to In this case, the man-hour loss L1/K1 per good board is L1/K1=5.24M.
つぎに、本発明の方法にしたがつて、４層づつ
の２枚の基板に分割して積層し、最後に接着を行
う場合は、
１枚の基板が良品である期待値K2は、
K2＝0.94＝0.656
１枚の基板の損失工数の期待値L2は、
L2＝4
〓n=1
（0.1×ｎ×Ｍ×0.9n-1）＝0.1M4
〓n=1
（ｎ×0.9n-1）＝0.815M
４層基板が２枚必要であるから、最終的な良品
基板１枚あたりの損失工数は、
２×L2／K2＝2.48M
である。 Next, according to the method of the present invention, if two boards each having four layers are divided and laminated, and then bonded at the end, the expected value K2 for one board to be a good product is: K2= 0.9 4 = 0.656 The expected value L2 of lost man-hours for one board is L2 = 4 〓 n=1 (0.1×n×M×0.9 n-1 )=0.1M 4 〓 n=1 (n×0.9 n- 1 ) = 0.815M Since two 4-layer boards are required, the final man-hour loss per good board is 2 x L2/K2 = 2.48M.
実際には、この他に、接着の工程と、接着工程
における製造欠陥に起因する損失工数が加えられ
る。 In reality, in addition to this, there are also the steps of bonding and lost man-hours due to manufacturing defects in the bonding process.
これらから製造欠陥に起因する損失工数の低減
がなし得ることが判明する。 From these results, it is clear that the loss of man-hours due to manufacturing defects can be reduced.
以上説明したように、本発明は、多層にわたる
積層配線を下層の第１の配線基板と上層の配線基
板とに分け、それらを同時に積層して行くことに
より、積層に要する日数をほぼ半減できるという
効果がある。
As explained above, according to the present invention, the number of days required for lamination can be reduced by almost half by dividing multi-layer laminated wiring into a lower first wiring board and an upper wiring board and laminating them simultaneously. effective.
また、別個に積層した第１及び第２の配線基板
を接着することとしたため、上述した如く、製造
欠陥に起因する損失工数を低減できるという効果
がある。 Furthermore, since the separately laminated first and second wiring boards are bonded together, there is an effect that the number of lost man-hours due to manufacturing defects can be reduced, as described above.
第１図は、本発明の第１の実施例を示す縦断面
図、第２図は、本発明の第２の実施例を示す縦断
面図である。
１：セラミツク積層配線基板、１０：第１の配
線基板、１１：層間絶縁層、１２，１３，１４，
１５：電源配線層、１６，１７，２５，３１，３
７：金属パツド、１９，２２，２４，３２，３
４，３６：ポリイミド樹脂絶縁層、３０：金属板
としてのアルミニウム板、４０：第２の配線基
板、４１：金−エポキシ系接着剤、５０，５１，
５２，５３：第２の配線基板群、５４：錫鉛共晶
半田。
FIG. 1 is a longitudinal sectional view showing a first embodiment of the invention, and FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention. 1: Ceramic laminated wiring board, 10: First wiring board, 11: Interlayer insulating layer, 12, 13, 14,
15: Power wiring layer, 16, 17, 25, 31, 3
7: Metal pad, 19, 22, 24, 32, 3
4, 36: polyimide resin insulating layer, 30: aluminum plate as metal plate, 40: second wiring board, 41: gold-epoxy adhesive, 50, 51,
52, 53: second wiring board group, 54: tin-lead eutectic solder.
Claims (1)
ツク基板上に複数の配線層を形成することにより
構成される多層回路基板の製造方法において、あ
らかじめ多層回路基板を下層部を構成する第１の
配線基板と、上層部を構成する第２の配線基板と
にわけ、セラミツク基板上に下層より順次配線層
を積層して第１の配線基板を形成する第１の工程
と、アルミニウム等の金属板上に下層より順次も
しくは上層より順次配線層を積層して第２の配線
基板を形成する第２の工程と、第２の配線基板の
金属板を希塩酸により溶解除去する第３の工程
と、第１の配線基板の表面に形成された金属パツ
ドと、第２の配線基板の表面に形成された金属パ
ツドとを半田付けもしくは導電性接着剤で接着す
る第４の工程とを有することを特徴とする多層回
路基板の製造方法。1. In a method for manufacturing a multilayer circuit board formed by forming a plurality of wiring layers on a ceramic substrate using polyimide resin as interlayer insulation, a first wiring board forming a lower layer portion of the multilayer circuit board in advance; A first step is to form a first wiring board by laminating wiring layers sequentially from the lower layer on a ceramic substrate, and a second wiring board forming the upper layer. A second step of laminating wiring layers sequentially or sequentially from the upper layer to form a second wiring board, a third step of dissolving and removing the metal plate of the second wiring board with dilute hydrochloric acid, and a first wiring board. and a fourth step of bonding the metal pads formed on the surface of the second wiring board and the metal pads formed on the surface of the second wiring board with a conductive adhesive. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19416786A JPS6350094A (en) | 1986-08-20 | 1986-08-20 | Manufacture of multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19416786A JPS6350094A (en) | 1986-08-20 | 1986-08-20 | Manufacture of multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6350094A JPS6350094A (en) | 1988-03-02 |
| JPH0513559B2 true JPH0513559B2 (en) | 1993-02-22 |
Family
ID=16320042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19416786A Granted JPS6350094A (en) | 1986-08-20 | 1986-08-20 | Manufacture of multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6350094A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101657666B1 (en) * | 2016-06-09 | 2016-09-19 | 김옥수 | scarf |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2638518B2 (en) * | 1994-11-18 | 1997-08-06 | 日本電気株式会社 | Manufacturing method of polyimide multilayer wiring board |
| JPH08213757A (en) * | 1995-06-26 | 1996-08-20 | Hitachi Chem Co Ltd | Production of wiring board |
-
1986
- 1986-08-20 JP JP19416786A patent/JPS6350094A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101657666B1 (en) * | 2016-06-09 | 2016-09-19 | 김옥수 | scarf |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6350094A (en) | 1988-03-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |