JPH0514950B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a tone signal generation method for a microcomputer that includes a built-in tone generator capable of outputting a buzzer sound or a melody.

(b) Prior art Generally, general-purpose microcomputers do not have built-in tone generators, but when using this general-purpose microcomputer to generate melodies, etc., the frequency of the tone to be generated is The output signal of the output terminal was manipulated by an output command so that the tone output time was also created by a program. Therefore, a program that generates a melody or the like has an increased number of steps, and the number of steps of other programs is inconveniently limited.

Therefore, a microcomputer with a built-in tone generator was developed, as described in "NEC Electronic Device New Product Bulletin μPD6651P" published on September 21, 1981. The tone generator divides the fundamental frequency to a specific value to create a tone signal of a predetermined pitch, and also uses a counter to create a time for outputting the created tone signal. Further, the frequency division ratio that determines the pitch of the tone signal and the time for outputting the tone signal are set by the operand data of the command.

(c) Problems to be solved by the invention However, in the conventional microcomputer with a built-in tone generator, it is necessary to process the order, pitch, and occurrence time of each note of a melody using a normal program. Since tone data is sent to the tone generator with a command to generate a tone generator, the tone data written to each operand of the command is different, making programming complicated. Another drawback was that the longer the melody, the longer the number of program steps.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and it is possible to generate each tone of a melody, etc. in accordance with a tone signal generation request during normal program execution. Address data indicating a predetermined address of a table area of a memory (ROM) in which tone data is fixedly stored is stored at a specific address of a data memory (RAM), and a predetermined subroutine is used to read address data indicating a predetermined address of a table area of a memory (ROM). The tone data is transferred to the tone data register by instructing, the interrupt processing is executed based on a signal indicating the end of generation of each tone signal, and the predetermined subroutine is executed in the interrupt processing. Each tone signal is generated successively.

(e) Effect According to the above method, data memory (RAM)
A predetermined address of a table area in which tone data such as a melody is stored is stored in a predetermined address, and then a predetermined subroutine program specifies a specific address in the data memory (RAM) and executes a predetermined command (table reference command). ), the tone data stored in the table area of the memory (ROM) is transferred to the tone data register. Further, in a predetermined subroutine program, +1 is added to the address data stored at a specific address in the data memory (RAM) in order to specify the address of the next table area. Then, a predetermined subroutine program is executed in an interrupt process executed in response to a signal indicating the end of tone signal generation, and tone data indicating the pitch and length of the next tone signal is transferred to the tone data register.

(F) Embodiment FIG. 1 is a block diagram of a microcomputer according to the present invention. 1 and 2 are counters, 3 and 4
5 is a ROM, 5 is a pulse generation circuit, and 6 is a tone data register, which constitute a tone generator. The tone data register 6 is composed of 8 bits, the lower 4 bits store frequency designation data that designates the frequency of the tone signal, and the higher 4 bits store time designation data that designates the time to output the tone signal. The ROM 3 receives the output of the lower 4 bits of the tone data register 6, that is, the frequency designation data, and creates a numerical value counted by the counter 1 in order to create the frequency designated by the data. The counter 1 is composed of a down counter, counts the numerical value applied from the ROM 3 based on the reference frequency CL1, and generates an output when the counting is completed. The pulse generating circuit 5 generates a pulse based on the signal outputted when the counter 1 finishes counting, and applies it to the counter 1 via the OR gate 7, causing the counter 1 to set the value from the ROM 3 again and restart counting. Therefore,
When the counter 1 repeatedly counts the numerical value created in the ROM 3 based on the reference frequency DL1, a tone signal of the frequency designated by the frequency designation data is created. That is, the ROM 3, counter 1, pulse generation circuit 5, and OR gate 7 form a tone signal generation circuit.

On the other hand, the counter 2 and the ROM 4 form a tone time generation circuit, and the ROM 4 inputs the upper 4 bits output of the tone data register 6, that is, time designation data, and creates a numerical value counted by the counter 2. Counter 2 is formed by a down counter, and uses the value applied from ROM 4 as a reference frequency.
By counting based on CL2, the output during the time from the start of counting to the end of counting
It controls the AND gate 8 and outputs the tone signal output from the counter 1 to the outside. That is, it determines the generation time of the tone signal.

The control circuit 9 controls the internal operation of the microcomputer based on the output from the instruction decoder 10 and the timing signal from the timing generator 11, and performs interrupt control to which the output from the counter 2 is applied. It has a built-in circuit 12. The timing generator 11 generates timing signals necessary for the operation of the microcomputer based on the reference clock pulse CP, and one machine cycle consists of T ₁ , T ₂ ,
It consists of four basic timings: T ₃ and T ₄ . The instruction decoder 10 is
The output of the instruction register 14 which stores the instruction code to be executed read from the ROM 13, that is, the instruction code is input and the control circuit 9 decodes the instruction. Indicates the control signal to be used.

The ROM 13 is a program area 15 in which a program consisting of a set of instruction codes is permanently stored.
and a table area 16 in which tone data indicating the pitch and length of each note constituting a melody is stored, and the output of a multiplexer 17 is connected to the address input of the ROM 15.
The output of the program counter 18 is applied to the input of the multiplexer 17 and is addressed by the output of the accumulator 19 that temporarily holds data and the data pointer 20.
The output of RAM21 is applied. The multiplexer 17 normally outputs the output of the program counter 18.
The instruction code is applied to the ROM 13 to enable the program counter 18 to specify the address of the program area 15, and at this time, the read instruction code is sent to the instruction register 14 and stored therein. Further, the multiplexer 17 is controlled by the control signal TABLE output from the control circuit 9 when a table reference instruction (TML instruction) is executed, and the multiplexer 17 is controlled by the control signal TABLE output from the control circuit 9.
1 is applied to the ROM 13, and the address of the table area 16 can be specified by the outputs of the accumulator 19 and RAM 21. At this time, the read tone data is sent to the data bus 22 and applied to the tone data register 6. still,
Other accumulator 19 of ROM 13, RAM 21, and data pointer 2 are connected to data bus 22.
0 input/output is connected.

FIG. 2 shows the ROM 13 and
This is an example of a data allocation diagram of RAM21,
Address AO(H) of table area 16 of ROM 13
Tone data constituting one song is stored from BF(H) to BF(H), and data 00(H) indicating the end of the song is stored in the last BF(H). On the other hand, addresses 00(H) and 01(H) of the RAM 21 are used as areas for storing address data specifying the address of the table area 16 of the ROM 13, and the address 00(H) of the RAM 21 is used as an area for storing address data specifying the address of the table area 16 of the ROM 13. Four bits are stored, and the upper four bits of address data are stored at address 01(H).

Therefore, an embodiment of the present invention in the case where the layout is as shown in FIG. 2 is shown in FIGS. 3 and 4, and will be explained with reference to FIG. 1. First, in FIG. 3, when there is a request to generate a melody while a normal program is being executed, the data pointer 20 is set to 0 (H) by a data pointer manipulation command, and the melody specified by the data pointer 20 is set to 0 (H) by a data pointer manipulation command. RAM21 address 00
(H) is the lower bit 0 (H) of address A0 (H) of ROM13.
to remember. Next, set 1 (H) to data pointer 20.
, and the value specified by data pointer 20 is set.
The upper 4 bits A(H) of the address AO(H) of the ROM 13 are stored in the address 01(H) of the RAM 21. Then, the jump command causes the program to proceed to the subroutine shown in FIG. 4.

The subroutine program in FIG. 4 sets the data pointer 20 to 0 (H), transfers the lower 4 bits of address data 0 (H) stored at address 00 (H) of the RAM 21 to the accumulator 19, and Furthermore, the data pointer 20 is set to 1 (H). Here, when the TML instruction is executed, at timings _T3 and _T4 of instruction execution, the control circuit 9
The control signal TABLE is output from the multiplexer, and the output of the accumulator 19, that is, 0 (H), and the address data A (H) read from the address 01 (H) of the RAM 21 specified by the data pointer 20 are sent to the multiplexer. 17 to the ROM 13 and specified by the address data AO(H).
The first tone data stored at address AO(H) of No. 6 is sent to the data bus 22. Then, in the first half of timing _T4 , the control signal STB1 output from the control circuit 9 causes the data bus 2 to
The tone data sent out at T2 is set in the tone data register 6, and furthermore, the control signal output from the control circuit 9 in the latter half of timing _T4 is set to the tone data register 6.
When STB2 is applied to counters 1 and 2, the upper 4 bits of tone data register 6 cause the ROM to be
The value determining the time output from 4 is set in counter 2, while the tone data register 6
A numerical value that determines the frequency output from the ROM 3 is set in the counter 1 by the lower 4 bits of the ROM 3. As a result, counters 1 and 2 start counting operations, and the first tone signal of the melody is outputted to the melody output. When the TML instruction finishes executing,
In order to designate the address A1(H) where the next tone data is stored, +1 is added to the accumulator 19, and the result is held in the accumulator 19 again. Then, the content of accumulator 19 is 0
(H), and if it is not 0 (H), sets 0 (H) to the data pointer 20, and sets the address 0 of the RAM 21 specified by the data pointer 20.
Transfer the data of accumulator 19 to (H),
Execute the return command RET to return to the original program. On the other hand, if the result of adding +1 to the accumulator 19 is 0 (H) due to the generation of tone signals several times, the RAM 22 specified by the data pointer 20 in which data 1 (H) is stored
Transfer the address 1 (H) of 1 to the accumulator 19 and add +1 to the address data.
Transfer to address 1 (H) of RAM21. Next, set the data pointer 20 to 0 (H) and load the RAM 21.
Set the address data of address 0(H) to 0(H).
As a result, carry processing from the lower 4 bits of the address data in the ROM 13 to the higher 4 bits is performed. After performing the above processing, execute the return command RET and return to the original program.

By the way, after executing the program shown in FIG. 4, the tone signal generation operation continues even when a normal program is executed, but when the counter 2 finishes counting, the output is set to "0". In order to do this, the tone signal output from the counter 1 is blocked at the AND gate 8. Furthermore, an interrupt request is made to the interrupt control circuit 12 of the control circuit 9 by the signal FIN in which the output of the counter 2 becomes "0", and when this interrupt is accepted, the interrupt processing program is entered. In the interrupt processing program, after saving data, etc., the subroutine shown in FIG. 4 is executed. in this case,
The address data stored in addresses 0 (H) and 1 (H) of the RAM 21 is data that specifies the next address of the address that stores the previously transmitted tone data, so the address data shown in FIG. By executing the subroutine, the next tone data is read and a tone signal is created based on this. In this way, by repeatedly executing the subroutine shown in FIG. 4 through interrupt processing each time the tone signal generation time ends, the tone signals that make up the melody are output in sequence. . On the other hand, when the generation of the last tone signal of the melody ends, interrupt processing is executed in the same way, but at this time, tone data 00(H) read from address BF(H) of the table area 16 is stored in the tone data register 6.
Therefore, the value 0 is set in both counters 1 and 2, the counters 1 and 2 continue to stop counting, and no interrupt request is generated by the signal FIN thereafter. Therefore, the output of the melody ends.

In this way, a melody can be generated by repeatedly executing the same subroutine using interrupt processing, and when changing the melody, the melody can be generated from address AO(H) in table area 16.
All you need to do is change the tone data stored in BF(H). Furthermore, if the tone data of a plurality of melodies is stored in the table area 16, in FIG. It is only necessary to do this, and multiple melodies can be generated.

(G) Effects of the Invention As described above, the present invention has the advantage that a program for generating tone signals such as a melody or a buzzer can be easily programmed, and it is also easy to change the melody or select a plurality of melodies. However, since the number of program steps for tone signal generation is reduced, it has the advantage that the capacity for other normal programs can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention, FIG. 2 is a data allocation diagram of the ROM and RAM shown in FIG. 1, and FIGS. 3 and 4 are embodiments of the present invention. FIG. 1, 2...Counter, 3, 4...ROM, 5...
... Pulse generation circuit, 6 ... Tone data register, 9 ... Control circuit, 10 ... Instruction decoder, 11 ... Timing generator, 12 ... Interrupt control circuit, 13 ...
ROM, 14...instruction register,
15...Program area, 16...Table area, 17...Multiplexer, 18...Program counter, 19...Accumulator, 20...
...Data pointer, 21...RAM, 22...Data bus.

Claims (1)

[Claims] 1. In a microcomputer with a built-in tone generator that generates a tone signal of a specified pitch and a specified length by setting tone data consisting of frequency specification data and time specification data in a tone data register. During normal program execution, in response to a tone signal generation request, address data indicating a predetermined address in a table area of a memory (ROM) in which tone data for each tone forming a melody, etc. is fixedly stored is generated. By storing the tone data at a specific address in a memory (RAM) and instructing the specific address in the data memory (RAM) by a predetermined subroutine, the tone data is transferred to a tone data register, indicating the end of generation of each tone signal. 1. A tone signal generation method for a microcomputer, characterized in that each tone signal is successively generated by executing interrupt processing based on the signal and executing the predetermined subroutine in the interrupt processing.