JPH0515084B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an attenuation circuit, and more particularly to an attenuation circuit having a circuit configuration with low distortion by removing nonlinear elements.

[Technical background of the invention and its problems] Generally, a voltage dividing circuit using resistors is used as an attenuation circuit. As shown in Figure 1, a conventional attenuation circuit consists of an emitter follower circuit in which the base is the signal input terminal 1, the collector is connected to a DC power supply, and the emitter is grounded via voltage dividing resistors R ₁ and R ₂ . The connection point between resistors R ₁ and R ₂ is the signal output terminal 2. The equivalent circuit when looking at this circuit from the output side is, where the output impedance of the emitter follower is h _ib , the impedance h _ib and the resistances R ₁ and R ₂ between the signal input terminal 1 and the ground are shown in Figure 2. are connected in series, and the input signal V _IN supplied to the signal input terminal 1 is voltage-divided and taken out from the signal output terminal 2 as the output signal V _OUT . In this case, the attenuation rate G is given by G=R ₂ /(R ₁ +R ₂ + _hib ) (1). Output impedance shown in equation (1)
h _ib is a nonlinear term, and this output impedance
The nonlinearity of h _ib causes distortion in the output signal V _OUT .

In order to reduce this distortion, it is necessary to make the output impedance h _ib of the emitter follower sufficiently smaller than the voltage dividing resistors R ₁ and R ₂ . For this reason, the third
A circuit configuration as shown in the figure can be considered. In FIG. 3, a constant current source I ₁ is connected to the emitter of a transistor Q ₁ whose base is connected to the signal input terminal ₁ and whose collector is connected to the DC power supply V _CC .
The emitter of is grounded through voltage dividing resistors _R1 and _R2 ,
The connection point between resistors R ₁ and R ₂ is defined as signal output terminal 2. Here, if the output impedance of the emitter follower is h _ib and the DC emitter current is Ie, it is given by h _ib (V _T /Ie) (2). V _T is defined as V _T =kT/q.
However, T is the absolute temperature, k is the Boltzmann constant, and q is the charge of the electron. Therefore, if V _T /Ie≪R ₁ + R ₂ ...(3), then the output impedance h _ib is divided by the voltage dividing resistor R ₁ ,
It can be made sufficiently smaller than R ₂ , and distortion due to nonlinearity can be reduced.

In order for formula (3) to hold true, either a large amount of direct current Ie must be passed through the emitter follower, or the voltage dividing resistor R _{1 must} be
All you have to do is set a high resistance to +R ₂ .

However, in a circuit like the one shown in Figure 3, flowing a large amount of direct current Ie increases power consumption, which is inappropriate for a circuit that requires low power consumption _. Setting +R ₂ to a high resistance has the disadvantage of deteriorating high frequency characteristics.

[Object of the Invention] In view of the above-mentioned points, the present invention is capable of preventing distortion caused by the nonlinearity of the output impedance in a conventional emitter follower attenuation circuit, and also allows a large amount of direct current to flow. It is an object of the present invention to provide an attenuation circuit that can achieve low power consumption without increasing the voltage dividing resistance and causing no deterioration of frequency characteristics.

[Summary of the Invention] The attenuation circuit of the present invention provides a first and second attenuation circuit between the emitter of an NPN transistor whose collector is connected to a first DC power supply and the emitter of a PNP transistor whose collector is grounded. voltage dividing resistors are connected in series, the base of the NPN transistor is used as a signal input terminal, and a second DC power supply is connected to the base of the PNP transistor (or a second DC power supply is connected to the base of the PNP transistor).
The connection point between the first and second voltage dividing resistors is used as a signal output terminal.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described based on the drawings.

FIG. 4 is a circuit diagram showing an embodiment of the attenuation circuit according to the present invention, and FIG. 5 is an equivalent circuit diagram as seen from the output side.

As shown in FIG. 4, the attenuation circuit consists of an NPN transistor Q ₁ , a PNP transistor Q ₂ , and voltage dividing resistors R ₁ and R ₂ arranged between the transistors Q ₁ and Q ₂ .
It is composed of a combination of. The base of the NPN transistor _Q1 is used as signal input terminal 1 to supply the input signal V _IN , its collector is connected to the DC power supply V _CC , and its emitter is connected to the voltage dividing resistor.
It is connected to the series circuit of R ₁ and R ₂ , and this series circuit is
Connected to the emitter of PNP transistor _Q2 ,
Its collector is grounded and its base is connected to the DC power supply _VB . Then, the connection point between the resistors R ₁ and R ₂ is used as the signal output terminal 2 to take out the output signal V _OUT .

In such a configuration, an NPN transistor
If the output impedances of Q ₁ and PNP transistor Q ₂ are h _ib1 and h _ib2 , the equivalent circuit seen from the output side is shown in Figure 5, and the attenuation rate G of this circuit is G = (R ₂ + h _ib2 ) / (R ₁ + R ₂ + h _ib1 + h _ib2 ) ......(4). In the above equation, h _ib1 and h _ib2 are nonlinear terms, but since the emitter currents of transistors Q ₁ and Q ₂ are equal, h _ib1 h _ib2 , and if R ₁ = R ₂ , G = 1/2. . Therefore, when R ₁ =R ₂ in the circuit shown in FIG. 4, the attenuation factor is -6 dB regardless of the two nonlinear impedances h _ib1 and h _ib2 , and nonlinear distortion is canceled out at this attenuation factor.

FIG. 6 is a circuit diagram showing another embodiment of the present invention.

The attenuation circuit shown in Fig. 6 has a circuit configuration in which a resistor R ₃ and a PNP type transistor Q ₃ are added to the circuit shown in Fig. 4.
voltage dividing resistors R ₁ , R ₂ at the emitter of type transistor Q ₁
Connect one end of resistor R ₃ in parallel with , and connect the other end of resistor R ₃ to the emitter of PNP transistor Q ₃ , its collector is grounded, and the base is connected to DC power supply V _B along with the base of PNP transistor Q ₂ . is connected to.

In such a configuration, an NPN transistor
If the output impedances of Q ₁ and PNP transistor Q ₂ are h _ib1 and h _ib2 , the attenuation rate G of this circuit is
is given by G=(R ₂ +h _ib2 )/(R ₁ +R ₂ +h _ib1 +h _ib2 ) similarly to the above equation (4). In the above formula, R ₂ /R ₁ = h _ib2 /
If h _ib1 , then G=R ₂ /(R ₁ +R ₂ ). Therefore, the attenuation factor G is determined by the voltage dividing resistance ratio and the transistor
By appropriately setting the output impedance ratio of Q ₁ and Q ₂ , that is, the emitter current ratio of each transistor _{Q 1 and Q 2 ,} it is possible to eliminate _the It can take any value, and nonlinear distortion is canceled out at that attenuation rate. However, the set damping rate G is 1/
A value greater than 2 and less than 1 is suitable. In addition,
In this case, if the emitter currents of transistors Q ₁ and Q ₂ are Ie ₁ and Ie ₂ , respectively, then {R ₃ (R ₁ + R ₂ )}/
If (R ₁ +R ₂ )=R ₁ /R ₂ , then Ie ₁ /Ie ₂ R ₂ /R ₁ , and h _ib2 / h _ib1 R ₂ /R ₁ . However, R ₃
(R ₁ +R ₂ ) is the parallel combined resistance value of the series resistor (R ₁ +R ₂ ) and the resistor R ₃ .

FIG. 7 is a circuit diagram showing still another embodiment of the present invention.

The attenuation circuit shown in FIG. 7 has a circuit configuration in which an NPN transistor Q ₃ and a resistor R ₃ are added to the circuit shown in FIG.
An NPN transistor _Q3 whose collector is a common collector and _whose base is a common base is arranged, one end of a resistor _R3 is connected to its emitter, and the other end of the resistor _R3 is connected to a voltage dividing resistor _R1. , R ₂ and is connected to the emitter of PNP transistor Q ₂ in parallel.

In such a configuration, an NPN transistor
If the output impedances of Q ₁ and PNP transistor Q ₂ are h _ib1 and h _ib2 , the attenuation rate G of this circuit is
is given by G=(R ₂ +h _ib2 )/(R ₁ +R ₂ +h _ib1 +h _ib2 ), similar to the above equation (4). In the above formula, R ₂ /R ₁ = h _ib2 /
If h _ib1 , then G=R ₂ /(R ₁ +R ₂ ). Therefore, the attenuation factor G is determined by the voltage dividing resistance ratio and the transistor
By appropriately setting the output impedance ratio of Q ₁ and Q ₂ , that is, the emitter current ratio of each transistor _{Q 1 and Q 2 ,} it is possible to eliminate _the It can take any value, and nonlinear distortion is canceled out at that attenuation rate. However, the set damping rate G is 0
A value larger than 1/2 is appropriate. In addition,
In this case as well, if the emitter currents of transistors Q ₁ and Q ₂ are Ie ₁ and Ie ₂ , respectively, then {R ₃ (R ₁ + R ₂ )}/
If (R ₁ +R ₂ )=R ₁ /R ₂ , then Ie ₁ /Ie ₂ R ₂ /R ₁ , and h _ib2 / h _ib1 R ₂ /R ₁ . However, R ₃
(R ₁ +R ₂ ) is the parallel combined resistance value of the series resistor (R ₁ +R ₂ ) and the resistor R ₃ .

8 to 10, the DC power supply V _B of the circuits shown in FIGS. 4, 6, and 7 is removed and a second signal input terminal 3 is provided, and two input signals V _IN1 ,
This is a circuit configuration that adds V _IN2 and outputs it. By configuring in this way, low distortion 2
An input type adder can be realized.

[Effects of the Invention] As described above, according to the present invention, an NPN transistor is connected at both ends of a voltage dividing resistor connected in series.
By disposing a PNP type transistor and providing a nonlinear impedance at the ends of both voltage dividing resistors, the attenuation factor is set regardless of the two nonlinear impedances, so distortion based on the nonlinearity of the output impedance is achieved. In addition, it is possible to configure a circuit with low power consumption without flowing a large amount of direct current, and it is also possible to realize an attenuation circuit with good frequency characteristics without the need to increase the voltage dividing resistance for nonlinear impedance. be able to.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional attenuation circuit, Fig. 2 is an equivalent circuit diagram of the circuit in Fig. 1 viewed from the output side, Fig. 3 is a circuit diagram showing another conventional example, and Fig. 4 is a circuit diagram of the present invention. 5 is an equivalent circuit diagram of the circuit in FIG. 4 viewed from the output side; FIG. 6 is a circuit diagram showing another embodiment of the present invention; FIG. 7 is a circuit diagram showing still another embodiment of the present invention, No. 8
The figure is a circuit diagram of the circuit in Figure 4 as a two-input type.
The figure is a circuit diagram of the circuit in Figure 6 as a two-input type.
FIG. 0 is a circuit diagram of the circuit of FIG. 7 as a two-input type. 1, 3...Signal input end, 2...Signal output end,
V _CC ...First DC power supply, V _B ...Second DC power supply, _Q1 ...NPN transistor, _Q2 ...PNP transistor, _R1 ...First resistor, _R2 ...First 2
resistance.

Claims (1)

[Claims] 1 An NPN transistor whose base is a signal input terminal, whose collector is connected to a first DC power supply, and whose emitter is connected to a first resistor, and whose emitter is connected in series to the first resistor via a second resistor. a PNP transistor whose base is connected to a first DC power supply and whose collector is grounded;
A connection point between the resistor and the second resistor is used as a signal output terminal, and the ratio of the resistance values of the second and first resistors is made equal to the ratio of the output impedances of the PNP type and NPN type transistors. An attenuation circuit characterized by: