JPH0515326B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Example (a) One Implementation Explanation of examples (Figures 2, 3, and 4) (b) Explanation of other embodiments (Figures 5 and 6) (c) Explanation of other embodiments Effects of the invention [Summary] Input Creates a window synchronized with the input clock in the input error detection circuit that detects errors in the input clock of the synchronous clock generation circuit, which generates the synchronous clock according to the phase difference between the rising or falling points of the clock and the synchronous clock. a first error detection circuit that detects an error when a specific change point of the input clock does not exist in the window; and a first error detection circuit that detects an error when a specific change point of the input clock exists in the inversion window. 2 error detection circuits are provided to detect input clock errors.

[Industrial application field]

The present invention relates to an input error detection circuit for a synchronous clock generation circuit which generates a clock synchronized with an input clock, and which detects as an error the asynchrony of the input clock, such as a dropout or cracking of the input clock.

Frequency (or phase) synchronized clock generation circuits that output clocks synchronized in frequency or phase with input signals are used in various fields.

For example, in the magnetic disk drive shown in FIG. 7, the controller CONT is provided with a frequency phase synchronization circuit FSYNC, and the disk unit
An internal clock (read/write control clock) synchronized with the servo clock signal from the DKU is generated and used for control. The servo clock signal is obtained as the output of the internal voltage controlled oscillator VCO, which synchronizes the servo signal read by the magnetic head HD from the servo track of the magnetic disk DK of the disk unit DKU with the phase synchronized circuit PLL. The magnetic head has a frequency proportional to the rotation speed.
Voice coil motor (VCM) accessing HD
It is used for control. The servo clock, which is the output of the voltage controlled oscillator VCO, is input to the controller CONT via the cable CBL, and is input as an input signal to the frequency and phase synchronization circuit FSYNC, which generates an internal clock synchronized with the servo clock.

[Conventional technology]

As shown in FIG. 8, such a synchronous circuit includes a frequency divider 1 that divides the frequency of the output clock SCL.
, a frequency phase comparator 2 which compares the frequency phase of the divided clock DCL of the frequency divider 1 and the servo clock SVC which is an input signal, and a lead signal FI and a delay signal FD which are the comparison results of the frequency phase comparator 2.
Charge pump 3 outputs control voltage according to
, a filter 4 for the output control voltage of the charge pump 3, an amplifier 5, and a voltage controlled oscillator 6 that generates an output clock SCL having a frequency corresponding to the output control voltage of the amplifier 5.

The operation of this synchronous circuit is as shown in Figure 8B.
and servo clock SVC and frequency phase comparator 2
Compare the frequency phase with . The frequency phase comparator 2 is a combination of logic circuits, and compares the phases between the rising edge of the output DCL at a specific change point and the rising edge of the servo clock, and when the phases are equal, both the leading signal FI and the lagging signal FD are output. In principle, it is at a high level, and short whisker-like pulses are output as the circuit operates, and the servo clock SVC is lower than the output DCL.
has a phase delay of d, that is, when the frequency is low, the pulse width of the delayed signal FD widens by d. Conversely output DCL
Compared to this, when the servo clock SVC has a phase lead (high frequency), the pulse width of the lead signal FI widens.

The lead/lag signal FI/FD, which is the output of the frequency phase comparator 2, is sent to the switch 3 of the charge pump 3.
1 and 32 are operated, and a current corresponding to the phase difference d is caused to flow in or out from the current sources 30 and 33, respectively, and is exchanged into an analog quantity. This exchanged analog quantity passes through a low-pass filter 4 consisting of capacitors 40, 41 and a resistor 42, and is input to a voltage controlled oscillator 6 as a control voltage by an amplifier 5, changing the oscillation frequency of the oscillator 6 to generate an output clock. Synchronize the SCL frequency with the servo clock SVC.

Such a digital synchronization circuit has a feature that no matter how the frequency of the oscillator 6 deviates from the input, as long as it is within the variable range of the oscillator 6, it will always be synchronized.

[Problem that the invention seeks to solve]

However, in such a synchronous circuit, the frequency phase comparator compares the phases based on a specific change point of the input servo clock and a specific change point of the output DCL, so in the synchronous state, the phase difference shown in FIG.
If the servo clock is lost as in SVC, SVC, or if the servo clock is divided into multiple clocks due to noise as in SVC in Figure 9B, the output frequency of the oscillator 6 will be disturbed and the output clock SCL will be greatly disturbed. It was hot. The causes of these bit omissions and waveform cracks are external noise, a failure in the voltage controlled oscillator VCO of the disk unit DKU, a disconnection of the cable CB, and a partially disconnected connector. The problem was that the density was also disturbed and writing errors occurred.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input error detection circuit for a synchronous clock generation circuit that can detect such input (servo) clock omissions and waveform breaks from the input clock and generate errors.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

The present invention includes a frequency phase comparator 2 that compares the phases of an input clock and a synchronous clock based on the rising or falling transition points, and generates a clock synchronized with the input clock based on the output of the frequency phase comparator 2. Synchronous clock generation circuit
The input error detection circuit that detects an error in the input clock of FSYNC includes a window generation circuit 7 that generates a window signal and an inverted window signal using the generated clock, and a window generation circuit 7 that detects that the window signal does not have a specific changing point of the input clock. a first error detection circuit 8 that detects and generates a first error signal;
and a second error detection circuit 9 which detects the presence of a specific change point of the input clock in the inverted window signal and generates a second error signal.

[Effect]

In the present invention, a window signal W and an inverted window signal W are created using an output clock SCL synchronized with an input clock SVC, and an error is detected by the presence or absence of a change point of the input clock SVC in both window signals W and W. It is something.

That is, as shown in FIG. 3, the window signal W is created by the output clock SCL synchronized with the input clock SVC, so when there is no gap in the input clock SVC as shown in FIG. Since there is a specific changing point of the input clock SVC, when there is no specific changing point of the input clock SVC as shown in FIG. 3, the first error detection circuit 8 detects that the output E1 does not change. This allows detection of input clock SVC failure. On the other hand, for waveform cracking of the input clock SVC as shown in Figure 4,
An inverted window signal W is used, and the presence of a specific change point of the input clock SVC in the inverted window signal W indicates a waveform break.

Therefore, if the input clock is input to the inverted window signal W,
The second error detection circuit 9 detects the existence of a specific change point in SVC, and
It is designed to detect SVC waveform cracks.

〔Example〕

(a) Description of one embodiment FIG. 2 is a configuration diagram of an embodiment of the present invention.

In the figure, the same parts as those shown in Fig. 1 are indicated by the same symbols, and 7a, 7b, and 7c are each J
-K flip-flops, each with a synchronous clock.
SCL is input to the clock terminal C, and the output of the previous stage is input to the J or K terminal. Therefore, the window creation section 7 has three stages of flip-flops 7a to 7
It consists of a well-known 1/6 frequency divider consisting of c.
8a is a delay circuit, which delays the input clock SVC in order to set the input clock SVC at the center of the window signal W; 8b is a flip-flop, in which the delayed input clock DSVC is connected to the clock terminal C, and the window signal W is connected to the data terminal. At D, an inverted window signal is input to the reset terminal R,
8c is a flip-flop, the output of the flip-flop 8b is input to the clock terminal C, the output of the flip-flop 8b is input to the data terminal D, and 9 is a flip-flop with a delay input. The clock DSVC is input to the clock terminal C, the inverted window signal is input to the data terminal D, the window signal W is input to the reset terminal R, and the Q output is output as an error E2. 9b is an OR circuit, and the Q output of the flip-flop 8c and Q of flip-flop 9a
The logical sum with the output is output as an error signal ERR. 10 is a flip-flop;
A synchronous clock SCL is input to the clock terminal C, an inverted window signal is input to the data terminal D, and a Q output delayed by one clock with respect to the window signal W is applied to the frequency phase comparator 2 as a synchronous clock DCL for comparison.

That is, in order to increase the detection margin, the generated window signal W has a rising edge, which is a specific change point of the input clock SVC, at the center, so the wind signal W is created by leading the phase of the input clock SVC. , Therefore, the comparison synchronous clock DCL that compares the frequency phase with the input clock SVC is:
It is applied later than the window signal W by the flip-flop 10.

In addition, the flip-flop 8b sets the window signal W as data at the rising edge of the delayed input clock SVC, which is a specific change point.
Checks whether there is a rising edge that is a specific changing point of the input clock SVC in the window signal W,
The flip-flop 8c generates an error by checking whether or not the flip-flop 8b detects the rising edge of the input clock SVC within the window signal W at the rising edge of the inverted window signal.

On the other hand, the flip-flop 9a converts the input clock SVC into the inverted window signal by setting the inverted window signal as data at the rising edge of the delayed input clock SVC, which is a specific change point.
Error E2 is generated by checking whether there is a rising edge that is a specific change point in the signal.

Next, the operation of the embodiment configuration shown in FIG. 2 will be explained using the main waveform diagrams shown in FIGS. 3 and 4.

First, according to FIG. 3, the first error detection circuit 8
The input clock dropout detection operation will be explained below.

The window creation section 7 is controlled by the synchronized clock SCL.
In the first stage, the flip-flop 7a outputs the frequency divided by 1/3 of S1 in FIG. 3, and the middle stage flip-flop 7b outputs the frequency divided by 1/3 of S2 in FIG. A window signal W, which is a /6 frequency-divided output, is output from the Q side, and an inverted window signal thereof is output from the Q side.

This window signal W is ahead of the input clock SVC in phase, and therefore the input clock SVC
A comparison synchronization clock DCL, which is compared in phase with the clock DCL, is generated by a flip-flop 10 with a delay of one clock.

On the other hand, the input clock SVC is slightly delayed by the delay circuit 8a, and in a normal synchronized state, the phase relationship is set so that the rising edge of the input clock SVC, which is a specific change point, is at the center of the window signal W. Therefore, the detection margin is large.

In the first error detection circuit 8, the window signal W is set in the flip-flop 8b at a specific rising edge of the delayed input clock DSVC, and therefore, the delay input clock SVC is specified while the window signal W is at a high level. When there is a rising edge, which is a change point, the output of the flip-flop 8b becomes low level, and is reset by the rising edge of the inverted window signal, returning to high level.

Since the output of the flip-flop 8c is set at the rising edge of the inverted window signal, if the output is at a low level at the rising edge of the inverted window signal, its Q output is at a low level and does not indicate an error.

On the other hand, when the input clock SVC is disconnected as shown in FIG. 3, the output of flip-flop 8b does not change to low level and remains high level, so that the high level output is transferred to flip-flop 8c at the rise of the inverted window signal. is set to
Therefore, the Q output becomes high level and the first error signal E1 is outputted as ERR from the OR circuit 9b.

Similarly, the input clock SVC as shown in Figure 3
Similarly, even if the flip-flop 8b is missing, the output of the flip-flop 8b remains at a high level, thereby the Q output of the flip-flop 8c becomes a high level, and the first error signal E1 is output from the OR circuit 9b.
Output as ERR.

That is, the first error detection circuit 8 changes the state of the flip-flop 8b when there is a rising edge of the input clock SVC in the window signal W, and when there is no change in the state, the input clock changes. There was no rising edge in the window signal W, which is a specific change point in SVC. In other words, an error occurs due to an input clock dropout.

Next, the waveform crack detection operation by the second error detection circuit 9 will be explained with reference to FIG.

In FIG. 4, the steps up to the creation of the window signal W, are the same as those in FIG. 3, and are therefore omitted.

In the second error detection circuit 9, an inverted window signal is set in the flip-flop 9a at a specific rising edge of the delayed input clock DSVC, and therefore, while the inverted window signal is at a high level, the delayed input clock DSVC is set to the flip-flop 9a. When there is a rising edge, which is a specific change point, the Q output of the flip-flop 9a becomes high level, and in the opposite case, it is kept low level.

Therefore, as shown in Figure 4, the input clock SVC
(DSVC) is broken or noise is added to the input clock SVC (DSVC) as shown in Figure 4, the flip-flop 9a is set to the high level of the inverted window signal, and therefore the Q output becomes high level and the second Error signal E2 is output,
The OR circuit 9b outputs the error signal FRR.

That is, the second error detection circuit 9 detects an error when the rising edge of the input clock SVC, which is a specific change point, is within the inverted window signal outside the normal window signal W.

In this way, it is possible to detect omissions in the input clock SVC, waveform breaks, etc., and generate errors.

(b) Description of Other Embodiments FIG. 5 is a block diagram of main parts of another embodiment of the present invention, showing another example of the first and second error detection circuits 8 and 9.

In the figure, the same parts as those shown in FIG. 2 are indicated by the same symbols. 9c is a flip-flop, the window signal W is applied to the clock terminal C, and the Q output of the flip-flop 9a is applied to the data terminal D. An external reset signal LST is input to the terminal R, and an error is indicated by the Q output.

In this embodiment, the configuration of the first error detection circuit 8 is the same as that of the embodiment shown in FIG. 2, and therefore the input clock dropout detection operation is also the same as that of FIG. 3.

On the other hand, in the second error detection circuit 9, there is no reset input to the flip-flop 9a, but a flip-flop 9c is provided separately, and the same input as that of the flip-flop 8c of the first error detection circuit 8 is applied.

The operation of this second error detection circuit 9 will be explained with reference to the operation diagram of another embodiment shown in FIG.

Flip-flop 9a is a delayed input clock.
The point of setting the inverted window signal at the rising edge, which is a specific change point of DSVC, is the same as in Fig. 2, but in Fig. 2, the wind signal W is set.
The flip-flop 9a is reset by the flip-flop 9a, whereas the flip-flop 9a is set to the inverted window signal by the rising edge of the delayed input clock DSVC.

Then, at the rise of the window signal W, the Q output of the flip-flop 9a is set to the flip-flop 9c.

Therefore, the second error signal E2 is the error signal
It can be output for a long time as ERR. That is,
An error signal of the same length as the first error signal E1
ERR can be output, making it possible to reliably grasp the error signal in subsequent circuits.

(c) Description of another embodiment In the above embodiment, the OR circuit 9b outputs the error signals as one signal, but the OR circuit 9b is not provided and the error state of the input clock can be detected. You can also output them separately.

Although the present invention has been described above with reference to examples, the present invention can be modified in various ways according to the gist of the present invention.
These are not excluded from the present invention.

〔Effect of the invention〕

As described above, since the present invention includes the first error detection circuit and the second error detection circuit, it is possible to detect input clock omissions and waveform cracks, and it is possible to detect synchronous clock generation. It is possible to detect that the synchronous clock of the circuit is disturbed by an error in the input clock, thereby improving the reliability of the synchronous clock generation circuit.

In addition, since the window signal and inverted window signal are created from the generated clock, the window signal and inverted window signal are synchronized, the error detection timing is stable and does not vary, and input clock dropouts and waveform cracks can be stably detected. This has the effect of being detectable.

Furthermore, even if the input clock duty changes,
This also has the effect that it is possible to detect errors in the input clock with high reliability without causing any errors to occur.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the invention, Figs. 3 and 4 are waveform diagrams of main parts of the embodiment of Fig. 6 is a waveform diagram of the main part of the embodiment shown in FIG. 5, FIGS. 7 and 8 are illustrations of a synchronous clock generation circuit, and FIG. 9 is a diagram illustrating problems in the prior art. be. In the figure, SYNC... synchronous clock generation circuit, 2... frequency phase comparator, 7... window creation circuit, 8... first error detection circuit, 9... second error detection circuit.

Claims (1)

[Claims] 1. A frequency phase comparator 2 that compares the phases of an input clock and a synchronous clock based on the rising or falling change points, and a clock that is synchronized with the input clock by the output of the frequency phase comparator 2. The input error detection circuit detects an error in the input clock of a synchronous clock generation circuit (FSYNC) that generates a synchronous clock. a first error detection circuit 8 for detecting the absence of a specific change point of the input clock and generating a first error signal; and detecting the presence of a specific change point of the input clock in the inverted window signal; An input error detection circuit comprising a second error detection circuit 9 that generates a second error signal.