JPH051632B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION The present invention relates to a static induction transistor photodetection device having a light receiving sensitivity tailored to arbitrary spectral sensitivity characteristics, and a method for manufacturing the same. Prior Art In the operation of a photodetector using a static induction transistor (hereinafter referred to as SIT), the gate voltage of the SIT is determined by the light irradiated to the SIT, while the potential barrier height in the channel is determined by the gate voltage. It is based on the principle that the voltage is controlled by the electrostatic induction effect of the drain voltage. As a result, as a photodetection device, SIT has the characteristics of high current gain, high signal-to-noise ratio, wide dynamic range, and high frequency operation. SIT photodetectors with various structures have already been proposed by the present inventor (Japanese Patent Application Laid-Open No. 1986-
No. 93386). On the other hand, SIT photodetectors have already been applied to imaging devices (hereinafter referred to as SIT image sensors) that take advantage of their characteristics of high current gain (high optical gain), high signal-to-noise ratio, wide dynamic range, and high frequency operation. Patent No. 1380712 by the inventor,
It is disclosed in Japanese Patent Application Laid-open No. 105672/1983, Japanese Patent No. 1556905, etc. However, SIT photodetector or
Attempts to increase the wavelength characteristics, particularly the blue sensitivity on the short wavelength side, in SIT image sensors using the gate accumulation method using this method have already been disclosed in Japanese Patent Application Laid-open No. 108458/1982 and Japanese Patent Application No. 14832/1999. The method is to add a structural modification to the gate part of the pixel of the SIT photodetector or SIT image sensor. As an example, a conventional example is shown in FIG. Figure 1 shows one pixel of an SIT image sensor using the gate accumulation method with increased short wavelength sensitivity.
b shows the circuit configuration and b shows the cross-sectional structure of the device.
Each part will be explained with reference to the figures. 10 is an n ⁺ substrate or a buried layer, which serves as a source region of the SIT portion. Reference numeral 11 is an n ^- or p ^- , i high resistance layer which forms a channel portion of the SIT. The p ⁺ region 13 formed in the deep diffusion region is the gate of the SIT and is for controlling the current flowing between the n ⁺ drain 15 and the n ⁺ source 10.
The p region 12 formed by a relatively shallow diffusion region is
It is also a SIT gate, but it is not used for current control, but rather for receiving short wavelength light with a relatively short penetration distance. A dotted line A shows the state of the depletion layer spread within the gates 13 and 12, and a dotted line B shows the state of the depletion layer spread within the high resistance layer 11.
14 is an insulating film such as SiO ₂ . The electrode 16 serves as a drain electrode as well as a signal readout line, and the electrode 17 forms a capacitor between it and the p-gate 12 via a thin insulating film 18, and serves as a gate address line.
The above configuration constitutes an X-Y address type image sensor. However ^, as is clear from the ^{way the} depletion layer spreads ⁱⁿ FIG.
pin diode and p region 12 and n ^- (p ^- , i)
Comparing the light-receiving sensitivity of pin diodes consisting of layer 11 and n ⁺ region 10, the p(12)n ^- (11)n ⁺ (10) diode has better short wavelength sensitivity, and the p ⁺ (13)n ^- (11)n ⁺ (10) The diode receives light with a relatively deep penetration distance. The device having the cross-sectional structure shown in FIG. 1 may be used as an individual element, that is, as a one ^- element SIT light emitter.
The upright operation using the n ⁺ region 10 as a drain is also similar to the operation of an image sensor pixel.
It may also be used for an inverted operation in which the n ⁺ region 15 is the drain and the n ⁺ region 10 is the source. In order to have blue sensitivity, the gate part of the SIT that operates as a light receiving part is made into a shallow diffusion region 12,
The gate portion of the SIT, which operates to control the current of the SIT, is made up of a deep diffusion region 13, and the shallow diffusion region 12 provides sensitivity to short-wavelength light, which has a shallow penetration distance. . Furthermore, for the same purpose, there is an example in which a hole is partially formed in the gate part of the SIT, and a structure having a depleted region that is hardly diffused is provided in place of the shallow diffusion region. Already special fair 4-
Proposed in No. 14833. However, in the conventional example described above, an important point was to reduce the diffusion depth of the gate portion in order to increase sensitivity on the short wavelength side, particularly in blue. However, if this method is used as it is, it is difficult to construct a SIT photodetector or image sensor pixel that has a light receiving sensitivity that matches any given spectral sensitivity characteristic. That is, if the diffusion depth of the p ⁺ gate diffusion region of the SIT is made shallower, the sensitivity at a specific short wavelength side will certainly increase, but the light receiving sensitivity in other wavelength ranges cannot be controlled. In particular, SIT photodetectors with light receiving sensitivity that matches the given spectral sensitivity characteristics, or
Conventional structures are insufficient for configuring pixels of SIT image sensors. Furthermore, in the conventional gate structure, only two diffusion steps (shallow diffusion and deep diffusion) are used, and the gates 12, 1
Since there is no restriction on the thickness of the high-resistance layer 11 between the layer 3 and the n ⁺ layer 10, it is also difficult to provide sensitive characteristics to specific wavelengths. Furthermore, in the conventional example, in order to have light receiving sensitivity for a specific wavelength, specific methods such as a method for determining the diffusion depth of the gate, a method for designing the thickness of the depletion layer, and a restriction on the area of the gate are required. However, the optimum design considering the spectral sensitivity characteristics had not been made. OBJECTS OF THE INVENTION It is an object of the present invention to utilize the excellent characteristics of the pixels of the SIT photodetector or image sensor described above, and to develop selective and sensitive sensitivity characteristics for some specific wavelengths into a gate as a light receiving part. By giving the characteristics as an amplifier to the SIT part, the structure of the pixel of the SIT photodetector or image sensor, which has selective sensitivity characteristics to some specific wavelengths, can be created as an overall characteristic. The purpose is to propose this method and provide a specific manufacturing method thereof. Furthermore, another object of the present invention is to provide a gate structure as a light-receiving portion with a light-receiving sensitivity that matches the spectral sensitivity characteristics not only for a specific wavelength but also for any required spectral sensitivity characteristics by combining the above structures. The purpose of the present invention is to provide a pixel of a SIT photodetector or SIT image sensor. Summary of the Invention In order to provide the gate portion of the SIT with selective and sensitive sensitivity characteristics to some specific wavelengths,
SIT photodetection in which an n+ buried layer is provided to limit the thickness ^of the high resistance layer between the gate part and the substrate (n ⁺ drain), and this n ⁺ buried layer is used as the drain region or source region. Configure the vessel. Furthermore, configure the gate part of SIT
The area of the p ⁺ region is divided and the area of the part that selectively receives wavelength λ _i is defined as A(λ _i ), the quantum efficiency required for wavelength λ _i is defined as η(λ _i ), and the SIT If the area of the entire gate is A _tpt , approximately A(λ _i )/A _tpt = e・η(λ _i )・1/1−R(λ _i
) (Here, R(λ _i ) is the reflection coefficient for the wavelength of λ _i , e≈2.718) A(λ _i ) is selected to have an area ratio as expressed by:
Here, A _tpt is the total area of the SIT gate. Furthermore, in order to detect the special wavelength λ _i , a pin diode formed by the SIT gate and the n ⁺ buried layer is connected.
The distance between the junction interface and the surface is designed to be x _i = 1/α _i (λ _i ) (where α _i is the absorption coefficient for wavelength λ _i ), and the depletion layer spreading in the i layer is almost in The impurity density is selected so as to spread from the junction interface toward the surface side, and the thickness W _i of the depletion layer is selected to be approximately given by W _i =x _i (1-1/e). The above conditions impose structural limitations on the depth and area of the SIT gate structure. The thickness of the n ⁺ region that forms the buried layer is selected to the extent that it acts as a filter for infrared light, etc. that is to be removed, and the thickness of the n ⁺ region that forms the buried layer is selected to be sufficient to act as a filter for the infrared light that is to be removed. Among the holes, this n ⁺ buried layer acts as a potential barrier, so SIT
has no effect on the p ⁺ gate. Therefore, it is possible to maximize the sensitivity to a specific wavelength on the short wavelength side. The basic part of the present invention is to realize selective light-receiving sensitivity for a specific wavelength λ _i in the gate portion of the SIT based on the design criteria described above. If the gate section of the SIT is divided and each divided diode section is made to have selective light receiving sensitivity for different wavelengths λ _i using the above design criteria, these divided diodes can be By parallel operation, the SIT as a whole can realize a photodetector that exhibits selective spectral sensitivity characteristics at several wavelengths λ _i . In other words, a single device can realize a photodetector with wavelength sensitivity selective to different wavelengths. If this method is pushed further, the diode portion is finely divided into predetermined area ratios, and each diode portion has selective light-receiving sensitivity for a predetermined wavelength with respect to gate diffusion depth, depletion layer width, etc. By designing in this manner, it is ideally possible to provide a single device with light-receiving sensitivity characteristics that match any required spectral sensitivity characteristics. In the present invention, a structural example of a SIT photodetector having light receiving sensitivity for three wavelengths λ ₁ , λ ₂ , and λ ₃ is shown, and a method for manufacturing such a structure is also shown. A feature of the present invention is that, in addition to the above-mentioned excellent characteristics of high photocurrent gain, high signal-to-noise ratio, wide dynamic range, and high frequency operation, the present invention also provides a SIT photodetector that is selective to some specific wavelengths. By separately optimizing the structure of the gate as a light-receiving part, which has sensitive sensitivity characteristics, and optimizing the amplification characteristics of the SIT, we created an SIT with a light-receiving sensitivity that meets the required spectral sensitivity characteristics as a whole. The purpose of this research is to propose a specific device structure and manufacturing method for realizing a photodetector. The quantum efficiency of the pin diode in the gate part of SIT is less than 1, but
The required sensitivity (A/W) can be obtained depending on the amplification characteristics of the SIT amplifier. The purpose is to optimize the light receiving sensitivity characteristics in accordance with the required spectral sensitivity characteristics for the light receiving part of the SIT gate and the amplification characteristics as the SIT, and to obtain the desired spectral sensitivity characteristics as a whole. A method for determining specific dimensions and structure limitations will be briefly explained together with the principles of the present invention. Generally, when a pn junction semiconductor is irradiated with light, electron/hole pairs are generated, but these carriers are
They are separated by an electric field existing in the depletion layer of the pn junction, and holes flow into the p-type region and electrons flow into the n-type region. A photocurrent is generated by this separated carrier flow. The generation rate (probability) of electron-hole pairs in a semiconductor depends on the wavelength of irradiated light. This is because photon energy has a specific absorption coefficient in semiconductors. As an example, in the case of Si, the relationship between the light absorption coefficient α and the wavelength λ (photon energy) as shown in Figure 2 at 300K,
Alternatively, there is a relationship between the penetration depth x and the wavelength λ.
For irradiation with monochromatic light (hν), the generation rate G(x) of electron-hole pairs is determined by Sze: “Physics of
Semiconductor Devices”p755 (Wiley 1981)
_With reference _to
−R(λ))/Ahν・αexp(−αx)...(1) Here, φ ₀ (λ) is the flux of incident light with wavelength λ, P ₀ (λ) is the light intensity with wavelength λ, R(λ) is the reflection coefficient for light with wavelength λ, and A is the area of the device. It is clear that for light incident with a constant intensity and a constant wavelength λ, the incidence G(x) takes its maximum value within a depth of penetration distance x=1/α(λ) of the wavelength λ. However, the number of carriers generated by light decreases due to recombination, and the recombination rate (probability) U(x) also decreases exponentially in the depth direction of the semiconductor substrate. There is.
Therefore, the photocurrent density J is expressed by the following equation. J=q(G(x)−U(x))·δ (2) Here, δ represents the width of the depletion layer within an infinitely thin range centered on x. A photodiode consisting of a combination of photodiodes whose individual divided areas are A(λ _i ) and whose individual junction depths are x _i =1/α _i (λ _i ) has a total current density J of J ＝ _∞ 〓 ⁱ⁼¹ J _i …(3) A current will flow. Here, the current density flowing through each diode is J _i = q(G(x(λ _i )) − U(x
(λ _i )·δ·A(λ _i )/A _tpt , and A _tpt = _∞ 〓 ⁱ⁼¹ A(λ _i ). Therefore, the quantum efficiency η(λ _i ) for a constant wavelength λ _i
is expressed by the following formula. That is, η(λ _i )=J(λ)A _tpt /P ₀・hν/q=hν・
δ・A(λ _i )/P ₀ (G(x(λ _i ))−U(x(λ _i )
))...(4) The response of the device to light with wavelength λ _i is the area A
It is obtained only in the part (λ _i ),
Other device area portions are adapted to receive light of different wavelengths. Therefore, equation (4) can be rewritten as follows. η(λ)=A(λ)/A _tpt δ(1-R(λ))α
・exp(−αx)−hνδA(λ)/P ₀ U(x(λ))……
(5) Since the term determined by the recombination rate in the second term on the right-hand side is relatively smaller than the first term on the right-hand side, the quantum efficiency for a constant wavelength λ is the area ratio A(λ)/A _tpt It can be considered that it is proportional to. It is thought that a device having such a modern wavelength λ selectivity is composed of a p ⁺ n ⁺ junction consisting of a step junction with high impurity density on both sides. FIG. 3 is a diagram explaining the principle. FIGS. 3a, 3b, and 3c are principle diagrams for explaining the present invention. In order to provide sensitive wavelength selectivity to the pn junction between the gate and drain of the SIT, a modernized p ⁺ Consider an n ⁺ junction diode. Divide the area of these p ⁺ n ⁺ junctions and adjust the position from the surface of the junction surface by 1/1 so that each has a sensitive light receiving sensitivity only for a specific wavelength λ _i .
is made equal to α _i (λ _i ). Figure 3a shows such divided diodes D ₁ , D ₂ , D ₃ ,...,
This is an equivalent diode circuit representation by connecting Di in parallel. Figure 3b shows a typical example of 3.
The light penetration distance x ₁ for the three wavelengths λ ₁ , λ ₂ , λ ₃ ,
The relationship between x ₂ and x ₃ is shown, and p ⁺ n ⁺ in Figure 3c
The distances from the surface of the joints are shown to be x ₁ , x ₂ , x ₃ corresponding to λ ₁ , λ ₂ , λ _{3 ,} respectively. In the above example, if the required quantum efficiency is η(λ _i ), then the area ratio is A(λ ₁ )/A _tpt ≒eη(λ ₁ )1/1−R(λ ₁ ) A(λ ₂ )/A _tpt ≒eη(λ ₂ )1/1−R(λ ₂ ) A(λ ₃ )/A _tpt ≒eη(λ ₃ )1/1−R(λ ₃ ) and A(λ ₁ )+A( By selecting λ ₂ )+A(λ ₃ )=A _tpt and selecting the position of the bonding surface so that x _i =1/α _i (λ _i ), the specific λ ₁ , λ ₂ , λ ₃ can be In principle, a diode with wavelength-sensitive light receiving sensitivity is possible. The distance between the p ⁺ n ⁺ junction plane and the device surface in Figure 3c varies with a function determined by the relationship between any given quantum efficiency η and wavelength λ, and the quantum efficiency η It also depends on other parameters that influence, e.g. A(λ), R(λ). Here R(λ) is the reflectance. Conversely, ideally, the light receiving sensitivity can be adjusted by adjusting the depth of the pn junction for a given η(λ). From equation (5), which ignores the term determined by the recombination rate U(x(λ)), the maximum value of quantum efficiency for monochromatic light irradiation is α=1/x= 1/δ and for the conditions of A(λ)=A _tpt . Even this maximum η is always smaller than 1. That is, η _nax =1/e. However, the desired sensitivity (A/
W). However, in practice, a constant width of the depletion layer should be considered in the pn junction, and a stepped junction cannot be obtained on both sides of the depletion layer. Furthermore, in addition to the carriers generated within the depletion layer, a considerable number of minority carriers also flow in through diffusion, and p
are concentrated in the type and n-type regions. This leads to increased sensitivity for a given wavelength, but with a significant decrease in wavelength-sensitive selectivity, given the quantum efficiency η and the wavelength λ
The reproducibility of the relationship becomes worse. FIG. 4 shows an example of the required functions of η and λ, with the maximum _values η nax and λ on the vertical axis and λ on the horizontal axis, respectively.
Normalized to λ _nax . The required wavelength response of _η with three sensitivity peaks as _shown in Figure 4 is such that i=
A rough approximation can be made by three steps: 1, 2, and 3. The maximum depth x _inax of the depletion layer for detecting the wavelength λ _i corresponds to the maximum penetration depth of the photon energy hν _i , and the width of the depletion layer is similarly determined by Δλ _i . Ru. The pin diode is a convenient structure because the thickness of the depletion layer can be matched to the η-λ curve by appropriately selecting the thickness of the i region. If the p ⁺ region and n ⁺ region are doped to a sufficiently high impurity density, there is very little depletion region penetrating into the p ⁺ and n ⁺ region other than the n ^- region at a diffusion potential or an appropriate reverse bias voltage. . However, as the receiving wavelength becomes longer, the diffusion distance of minority carriers becomes a problem, and minority carriers generated within the diffusion distance of minority carriers from the edge of the depletion layer in the p ⁺ and n ⁺ regions also affect the quantum efficiency of the device. . In particular, as the receiving wavelength becomes longer, the wavelength response of the quantum efficiency of a pin diode, which is designed to have a sharp quantum efficiency only at a specific wavelength, becomes wider. This is due to the following reasons. The surface of the pin diode is
If we consider the case where light enters from the p side perpendicular to the junction surface of the device, the longer the wavelength of the light, the deeper the penetration distance. This is because the number of holes generated within the diffusion distance increases, and these holes increase the quantum efficiency near the wavelength λ. Therefore, in the case of the pin diode mentioned above, the depletion layer width is
x _inax , and the practical limit for the depletion layer thickness W _i is _{W i =} x _inax (1-1/ e) It is expressed by the formula: x _inax is exactly the distance from the device surface to the in-junction interface. The reason why the width W _i of the depletion layer was selected as shown in the above formula is as follows.
This is because while x _inax is the penetration distance of λ _i , the light of λ _i is most effectively and sensitively absorbed in the range from the distance x _inax /e to the position of x _inax . For spectral sensitivity characteristics (η-λ curves) having different maximum values η _i , the area ratio A
(λ _i )/A _tpt must be considered. In the example of FIG. 2, the absorption coefficient α varies within the order of one and a half digits in the visible light range. The probability of carrier occurrence G(x) due to light is proportional to the absorption coefficient α, and the recombination rate U(x) is determined experimentally.
is a valid value reduced by . The wavelength-dependent reflectance R(λ) could similarly be incorporated into the area ratio A(λ _i )/A _tpt according to equation (5). Finally, it is possible to incorporate into the area A(λ _i ) of each divided device the terms that affect the quantum efficiency for all specific wavelengths λ _i other than the diffusion of minority carriers. be. By applying this very simple concept, we can design a device that considers the three spectral responses shown in Figure 5 a, b, and c, and furthermore, from the superposition of these results, we can determine the necessary spectral sensitivity characteristics. This means that it is possible to design a device that has a light-receiving sensitivity that is tailored to the user's needs. As an example, in the case of an n-channel normally-on SIT operated with reverse bias, the potential of the p ⁺ gate region biased to a certain operating point with respect to the drain n ⁺ region is determined by the change in incident light. The potential of the channel at the intrinsic gate point is controlled by the gate potential and, in part, by the drain voltage due to the effect of electrostatic induction, which is the operating principle of SIT. Therefore, light will only indirectly affect potential barrier control through gate potential changes. The photoexcited hole is p ⁺
The potential well of the gate is accumulated at the deepest point, but in order to effectively modulate the multiple carrier (electron) current flowing in the channel by photodetection, the deepest point of the potential well of the gate must be It is better to be located closest to the channel. FIG. 5a shows a cross-sectional structure of a photodetector according to the invention having wavelength selectivity. The central part has an n ⁺ buried layer 51 as a drain region.
A SIT is arranged, and the n ⁺ buried layer 51 is shaped to rise toward the source 64 in the channel portion so that the effective SIT channel 57 is shortened. The n ⁺ regions 52 and 53 are both formed by diffusion from the buried layer 50 to define the thickness of the high resistance n ^- (p ^- , i) layers 55 and 56, respectively, and are connected to the gate of the SIT. The area is also formed from three areas 58a, 58b, and 58c. p ⁺ region 58a is SIT's n ⁺ source 64
It is a region for controlling the current between the n ⁺ drains 51 and 50, and at the same time, the wavelength is, for example,
It plays a role as a light-receiving part for relatively long wavelengths around 660 nm. On the other hand, p region 58b is electrically connected to p ⁺ gate region 58a, but
It serves as a light-receiving part for green light with a shorter wavelength, for example around 550 nm. Furthermore, the p region 58c
Although it is electrically connected to the p ⁺ region 58a and the p region 58b and is part of the gate of the SIT, it can also serve as a light-receiving portion for blue light with a shorter wavelength, for example, around 450 nm. n ⁺ area 52
is a region for limiting the thickness of the high resistance n ^- layer 55, and includes the p region 58b, the n ^- region 55, and the n ⁺ region 5.
The desired wavelength selectivity is achieved by controlling the width of the high resistance layer of the pin diode. At the same time, the thickness of high resistance n ^- layer 56 is also limited by n ⁺ region 53. Wavelength as an example
Table 1 below shows the dimensions of each region when selective light-receiving sensitivity is provided for the three wavelengths of 460 nm, 550 nm, and 660 nm.

[Table] Here, x _inax is the distance from the Si layer surface to the n ^- (p ^- , i) n ⁺ junction interface W _i is the depletion that spreads from the n ^- (p ^- , i) n ⁺ junction interface to the surface side Indicates the layer thickness, W _i = x _inax (1−
1/e). x _jp ⁺ _nax represents the junction depth of the p-type diffusion layer, and −x _j n ⁺ represents the dimension of the rise of the n ⁺ layers 52 and 53. In FIG. 5a, 61 is a gate electrode formed of a p ⁺ polysilicon layer or a transparent electrode,
It is connected to p-type regions 58a, 58b, and 58c. 62 is a V formed by an anisotropic etching process, etc.
This is a groove shaped like a letter and serves as a separation area. 63 is
SiO ₂ film, 64 is an n ⁺ source diffusion region, 65 is a source electrode formed of n ⁺ polysilicon, 66 is
An insulating film such as PSG or CVDSiO ₂ is connected to the source electrode 65 through an Al electrode 67 . FIG. 5b is a plane parallel to the S _i plane, and the area 58a,
It shows the potential distribution for holes in a plane cut through portions 58b and 58c. White circles (○) indicate holes, and arrows indicate the direction in which the holes move.
Differentiating the impurity density within the same p region, selecting the p region of 58a as the highest impurity density, and gradually increasing the impurity density to 58a.
By lowering the impurity densities of p + region 58a and p ⁺ region 58c, the p + region 58a becomes a place where holes excited by light are most likely to accumulate. Figure 5c shows a plan view of figure a. N ⁺ source region 64 is completely surrounded by deep p ⁺ diffusion region 58a. The distance from the end of p region 58c to source region 64 is
The dimensions are chosen to be less than the hole diffusion distance. Gates 58a, 58b, 58c and high resistance layer 5
FIG. 6 shows the impurity density distribution in each part of the pin diode consisting of the pin diode 4, 55, 56 and the n ⁺ layers 50, 52, 53. Acceptor impurity density distribution ( _NA )
is shown by a solid line, and the donor impurity density distribution (N _D ) is shown by a dotted line. Both portions of the n ⁺ regions 50, 52, 53 and the surface P regions 58a, 58b, 58c are
It can be formed using a selective diffusion technique according to the figure. In FIG. 6, the vertical axis shows the impurity density log|N| on a logarithmic scale, and the horizontal axis shows the normalized vertical dimension (diffusion depth) x/x ₀ . Here, as the normalization constant x ₀ , the required η
In the −λ curve, the light penetration depth x=1/α(x)=x ₀ corresponding to the longest wavelength among several wavelengths showing the maximum value of quantum efficiency is selected. This depth x ₀ exactly corresponds to the boundary of the extent of the deepest depletion layer. N _A1 , N _A2 , N _A3 correspond to the impurity density distribution of the p-type diffusion regions 58a, 58b, 58c, respectively, and N _D1 , N _D2 , N _D3 correspond to the impurity density distribution of the n-type region 58, respectively.
This corresponds to impurity density distributions of 0, 52, and 53. The SIT photodetector having wavelength selectivity shown in FIG. 5 can be formed by the following manufacturing process using, for example, S _i material (see steps a to i in FIG. 7). As the substrate, an n ⁺ substrate or a p substrate is selected. However, if a p-substrate is used, by forming a highly concentrated n ⁺ buried layer 71 on the p-substrate 70, holes generated by near-infrared light, which has a long light penetration distance, can be absorbed into this n ⁺ layer. It is convenient because 71 absorbs it. Therefore, by introducing a structure having the buried layer 71, it can be used in place of a commonly used infrared cut filter. FIGS. 7a to 7i show such n ⁺ buried layers 71, 74, 75a, 75.
75b and 75c show the manufacturing process of a SIT photodetector. Figure 7a shows S _b or A _s in a p-type _Si substrate with a buried layer 71 of S _b or A _s formed on the surface.
After removing the glass, a thermal oxide film 72 is placed on a predetermined portion.
and a cross-sectional structure in which a protective film 73 is formed. The thermal oxide film 72 is partially used as a mask for ion implantation. The shaded area in FIG. 7b shows the impurity density distribution when an impurity having a relatively fast diffusion rate, such as p, is ion-implanted into the n ⁺ layer 71. x=0 is S _i
Show the surface. A-A' line in Figure 7a, respectively.
This corresponds to the B-B' line and the C-C' line, and the thermal oxide film is completely removed in the region where it is desired to add the largest amount of impurities. In FIG. 7b _{, the solid line indicates the impurity distribution of As or S b as} the original background. The position showing the maximum value of the impurity density distribution after p ion implantation in the plane along the A-A' line is:
It is better to form it at a position sufficiently deeper than the surface of the n ⁺ buried layer 71. This is to suppress unnecessary autodoping in the subsequent epitaxial growth process. An ion implantation protection film 73 is formed on the thermal oxide film 72 in a portion closest to the channel region of the SIT where the deep gate diffusion region 81 is to be formed. The impurity density distribution in the cross section along the line B-B' is the same as the impurity distribution of As or _Sb as the original _background . C
The impurity density distribution in the cross section along the -C' line shows that a considerable dose of p passes through the thermal oxide film 72.
This figure shows the implantation into an n ⁺ buried layer 71 doped _{with As or S b .} The thickness of the high-resistance layer 78 formed by autodoping is limited in consideration of the dose of p atoms, which have a relatively fast diffusion rate, and the time of the subsequent heat treatment process. P ions other than the p ions implanted into the buried layer 71 remain in the insulator, but the thermal oxide film 72 and the protective film 7
3 is removed by subsequent etching. Therefore,
Three different out-diffusion n ⁺ diffusion regions are defined using only two mask steps. The acceleration energy and dose of the p ion implantation can be calculated from the longitudinal dimensions of the designed device taking into account all subsequent high temperature processes. Thermal oxide film 72
The thickness of is selected to correspond to the difference in thickness of the depletion layer according to FIG. The selectively doped n ⁺ buried layer 71 acts as a finite n ⁺ diffusion source just below the n ^- epitaxial layer 78, where redistribution takes place during epitaxial growth and all subsequent high temperature processes. . The redistribution is determined as a function of the surface concentration of the n ⁺ buried layer and the diffusion constant and diffusion time of each doped impurity. FIG. 7c shows a structure in which a thermal oxide film 76 is formed after growing an n- ^, p- ^, or i high-resistance epitaxial layer 78. FIG. 7d is a cross-sectional view after simultaneously forming the SIT source and deep gate diffusion windows in the thermal oxide film 76 and then growing the n ⁺ doped polysilicon layer 77 by CVD (76a is the thermal oxide film 76). 7
6 shows the state with the window open). This process is SIT
This is a self-alignment process in which the gate and source of the device are defined using the same mask. FIG. 7e shows that the n ⁺ doped polysilicon layer 77 is plasma-etched leaving only the n ⁺ polysilicon region 84, completely exposing the _Si plane in the deep gate diffusion window, and then oxidized. 3 is a cross-sectional view after a deep gate diffusion region 81 is formed by performing boron deposition and dry-bray diffusion in a neutral atmosphere. FIG. At this time, source n ⁺ region 83 is also formed at the same time. 76b is an oxidized layer of the n ⁺ polysilicon layer 84 and a boron glass layer;
These are the same thermal oxide film and boron glass layer. 8
5 is a boron glass layer formed by a boron diffusion process. FIG. 7f is a cross-sectional view after selectively removing the oxide film 76a and performing the first boron ion implantation using the resist layer 79 as a protective mask. Region 80 is the ion-implanted part. Next, the resist layer 79 is removed and a second boron ion implantation is performed to completely dope the gate region (FIG. 7g). This second ion implantation should have short wavelength light receiving sensitivity.
This is for forming the shallowest diffusion region 82, and is intended to cover the deep diffusion region 81 that has already been diffused and the p region formed by the first boron ion implantation.
A second boron implantation layer with the same dose is simultaneously formed in region 80. Next, heat treatment as a final high-temperature process is performed in a non-oxidizing atmosphere to remove damage such as crystal defects caused by ion implantation and form a final impurity distribution within the device. Next, as shown in FIG. 7h, the p ⁺ gate region 81, the p region 80, and the p ⁺
A polysilicon layer 86 is grown by CVD to form a gate electrode. This p ⁺ polysilicon layer 86
Instead, a transparent electrode such as SnO ₂ with good transparency may be used. Next, as shown in Figure 7i,
After a transparent passivation insulating film 87 such as a plasma Si ₃ N ₄ film or a PSG-CVD film is grown over the entire surface, a window for contacting the source polysilicon electrode 84 is opened, and an Al electrode 88 is formed. The above is an example of the method for manufacturing the SIT photodetector shown in FIG. 5, but the separation step is omitted in the steps shown in FIG. In the manufacturing process shown in Figure 7, after the second ion implantation shown in Figure 7g, a Si ₃ N ₄ film or
After forming a SiO ₂ film with a thickness of approximately 400 Å to 1000 Å, a transparent electrode such as SnO ₂ is formed to cover the p ⁺ region 81,
By inserting a step of forming a MIS capacitor structure on p regions 80 and 82, a gate accumulation type SIT image sensor as explained in FIG. 1 can be easily realized. In this case, the n ⁺ buried layers 74, 75a, 75b, and 75c will serve as the source electrode of the SIT, and the n ⁺ diffusion region 83 will serve as the drain of the SIT. The pixels of this SIT image sensor have a specific wavelength, for example, if the dimensions of each part are selected as shown in Table 1, the wavelength is 460 nm,
It has selective light receiving sensitivity at 550 nm and 660 nm. Another method of implementing a pixel of a SIT photodetector or image sensor with selective sensitivity characteristics for some specific wavelengths is shown in FIGS. 8a-d. In the process of FIG. 8, the SIT gate 910 (FIG. 8 d)
The feature is that an insulating film 900 tapered from a thin insulating film to a gradually thicker insulating film is used as a mask for boron ion implantation when forming the insulating film. In the step of FIG. 8, only important process parts for obtaining a selective gate impurity distribution are shown. Although the process related to the impurity distribution in the buried layer as explained in FIG. 7 is not explained, it is of course possible to combine it with the manufacturing method shown in FIG. 8 using the tapered insulating film 900. . FIG. 8a will be explained. After forming a high resistance epitaxial layer 91 on the n ⁺ substrate 90,
A thermal oxide film 93 is formed, a window is opened in the source part, and an insulating film 93 that defines the source part is left.
After removing all the insulating films 93, an n ⁺ doped polysilicon layer 94 is formed on the entire surface. After that, all the n ⁺ doped polysilicon layers 94 are removed, except for the n ⁺ doped polysilicon layer 94 that becomes the source electrode.
After removing, PSG92 with a p content of 6 to 12% is grown on the entire surface by CVD to a thickness of about 4500 Å. As can be seen from FIG. 8a, the area where the gate is to be formed, which will be the light receiving area of the SIT, is entirely covered with a PSG film, and in FIGS. 7d and e, SiO ₂ films 76, 7
The difference is that it is protected by 6a. next,
As shown in FIG. 8b, a window 95 is opened in the area where the deep gate diffusion region of the SIT is to be formed.
Do this. Next, heat treatment for reflow (glass flow) of the PSG film is performed at approximately 700°C. Since the PSG film has a high p content of 6% to 12%, a tapered portion of the PSG film 900 as shown in Figure 8c is formed by short reflow, which also suppresses p diffusion. It is being This reflowed
The PSG film is used as a mask for boron ion implantation or diffusion. Finally, after the boron ion implantation heat treatment or diffusion drive-in, the gate diffusion region 9 of the SIT as shown in Figure 8d.
10 and n ⁺ doped polysilicon 94
An n ⁺ source diffusion region 920 is obtained. In Figure 9A, the vertical axis is the acceptor impurity density N _A expressed on a logarithmic scale, the x-axis is the dimension in the depth direction of the device, and the y-axis is the dimension in the lateral direction parallel to the surface of the device. It shows tertiary coordinates and the acceptor impurity density distribution in the gate portion of the SIT in three different cross sections A, B, and C in the drawing shown in FIG. 9B. At the same time, the diagram of FIG. 9B also shows the potential distribution in the y direction.
This shows that the place where holes excited by light are most likely to accumulate is the p ⁺ region, which is closest to the SIT channel and is most deeply diffused. Ion implantation is performed using the tapered portion 900 of the insulating film as a mask. The distribution of implanted impurities in S _i is
These are shown in the shaded areas of Figures A and B, respectively. The impurity distribution implanted into S _i is redistributed by the drive-in process as shown by the solid lines a, b, and c in Figure 9, and as shown by the dotted line in the x-y plane. . Other ion implanted impurities are
Distributed within the PSG film and removed. After simultaneously forming the gate diffusion region 910 and source diffusion region 920 of the SIT as shown in FIG. 8d, the gate electrode and source electrode are formed by performing the same steps as described in FIG. 7h and i. . Furthermore, another method of realizing pixels of the SIT photodetector or image sensor according to the present invention is shown in FIG. Figure 10 shows S _i
It is characterized by the use of selective etching technology. In this case, the plane orientation of the _Si substrate is off-
Use oriented ones. This is to achieve an etching angle that is adjusted depending on the diffusion depth of the p ⁺ region, the size of the device, and the sensitivity of the receiving wavelength. FIG. 10a shows the SIT gate diffusion region 103 and source diffusion region 104 formed using the self-alignment process explained in FIGS. 7c, d, and e.
After simultaneous formation of n ⁺ doped polysilicon region 1
06 and a cross-sectional view after removing the entire insulating film, leaving an insulating film 104 made of a thermal oxide film and a PSG film. The SIT p ⁺ gate diffusion covers all diffusion regions 103
Impurity diffusion is performed non-selectively and uniformly over the entire region, and determines the thickness of the high-resistance layer 102 and the width of the depletion layer over all the diffusion regions 103. 11A and 11B show the impurity density distribution within the gate 103 of the SIT shown in FIG. 10. n ⁺ as shown in Figure 5 or Figure 7
The method shown in FIG. 10 does not require a process in which the thickness of the high-resistance layer 103 is controlled by selectively doping impurities into the buried layer and utilizing diffusion from the impurities. Next, as shown in Figure 10b,
After p ⁺ drive-in diffusion, the entire surface is oxidized to form a base oxide film 107 with a thickness of approximately 1000 Å.
A Si ₃ N ₄ film 108 is formed. This is the oxide film 10
7 and the Si ₃ N ₄ film 108 as a mask to etch the _Si surface. Next, as shown in FIG. 10c, the S _i surface is etched. Depending on the size of the mask, an etched V-shaped groove 200
The depth of is determined. V-shaped groove 200 has an asymmetrical shape. Effects of the Invention According to the SIT photodetector having the cross-sectional structure shown in FIG. A photodetector with the same characteristics is realized. 7th
, 8 and 10, a specific method for realizing a SIT photodetector having light receiving sensitivity for such a specific wavelength has been described. as a specific wavelength
An X-Y address type image sensor is realized by designing pixels of a SIT image sensor that have selective light-receiving sensitivities for green, rod, and blue light, and combining those 37 pixels into one. It is. Conventionally, attempts have been made to increase the blue sensitivity by shallowing the diffusion depth of the gate of SIT, but in the present invention, simply decreasing the gate diffusion depth is insufficient, and specifically improves the depletion layer. limiting the thickness of the n ⁺ substrate, or n ⁺
This paper explains how to determine the thickness of the high-resistance layer by determining the shape of the buried layer, and shows a specific method for determining the dimensions. Furthermore, by combining such concepts, a method for realizing a photodetector having selective light-receiving sensitivity for several specific wavelengths was disclosed, along with specific dimensions (Table 1) and a manufacturing method. Although the present invention has been described above mainly using _Si , it is also possible to realize a photodetector or imaging device using the same concept in other wavelength ranges by taking absorption curves into consideration. be.

[Brief explanation of the drawing]

FIGS. 1A and 1B show a conventional SIT photodetector or image sensor using a gate accumulation method, and FIG. FIG. 2 is a characteristic diagram for explaining the present invention, showing the relationship between the light absorption coefficient α and penetration distance x of S _i at 300K and the wavelength λ or photon energy Fph (eV). FIG. 3 is a conceptual diagram for explaining the principle of the present invention, in which a is a parallel circuit of gated diodes, b is a schematic diagram of penetration distance and wavelength, and c is an example of the structure of a gated diode. FIG. 4 is an example of a quantum efficiency curve having peak values at wavelengths λ ₁ , λ ₂ , and λ ₃ , and is a diagram for explaining the principle of the present invention. FIG. 5 shows an embodiment of the present invention, in which a is a cross-sectional structural diagram, b is an explanatory diagram showing the potential distribution and carrier movement within the gate, and c is a plan view. Figure 6 shows the fifth
The relationship between the impurity density distribution in the pin diode part of the gate of the SIT shown in the figure is shown. Figure 7 a to i are
An example of a manufacturing method of one embodiment of the present invention shown in FIG. 5 is shown. 8a, b, c, and d show steps of a specific manufacturing method of another embodiment of the present invention different from the structure shown in FIG. 5. FIG. 9A and 9B are diagrams for explaining the impurity density distribution within the gate 910 of the SIT shown in FIG. 8. Figure 10 a, b,
8c shows another embodiment of the present invention, which is different from the structure shown in FIGS. 5 and 8, together with a specific manufacturing method. FIGS. 11a and 11b are diagrams for explaining the impurity density distribution within the gate 103 of the SIT shown in FIG. 10. 50, 51, 52, 53, 71, 74, 75
a, 75b, 75c, 90, 101...n ⁺ substrate or n ⁺ buried layer, 70...p or p ^- substrate,
54, 55, 56, 57, 78, 91, 102...
n ^- or p ^- or i high resistance epitaxial layers, 58a, 58b, 58c, 81, 80, 8
2,910,103...SIT gate region, 61,
86...p ⁺ polysilicon electrode or transparent electrode,
62... Isolation region (insulator), 63... Thermal oxide film, 6
4...n ⁺ source diffusion region, 65...n ⁺ polysilicon layer (source), 67...Al type (source), 66...
PSG or CVDSiO ₂ film, 900... Tapered PSG film portion, 73... Protective film for ion implantation (resist), 85, 95... Gate diffusion window, 1
08...Si ₃ N ₄ film.

Claims (1)

[Claims] 1. In a photodetector made of an electrostatic induction transistor, a limit is imposed on the thickness of the high-low layer i layer between the P ⁺ region constituting the gate portion and the substrate.
An n ⁺ buried layer is provided, and a photodetector is configured using the n ⁺ buried layer as a drain or source region,
When the wavelength of the light irradiated onto the surface of the photodetector is λ _i , its absorption coefficient α _i (λ _i ), and the distance between the in junction of the pin step junction and the surface is x _i , then X _i =1/α _i (λ _i ), and the ratio of the area A (λ _i ) of the gate portion that selectively receives the specific wavelength λ _i and the area A _tpt of the entire gate is A (λ _i )/A _tpt = eη (λ _i )1/1−R(λ _i ) where e: 2.718 η (λ _i ): quantum efficiency required for wavelength λ _i R (λ _i ): reflection coefficient of depletion layer for wavelength λ _i The thickness W _i and the maximum depth X _inax of the depletion layer for detecting the specific wavelength λ _i are selected as follows: _Wi = X _inax (1-1/e) X _inax = 1/α _i (λ _i ) , a photodetecting device comprising a static induction transistor, characterized in that it has selective light-receiving characteristics for a specific wavelength λ _i . 2 When several specific wavelengths are λ ₁ , λ ₂ , λ ₃ , the above A(λ _i )//A _tpt is A(λ ₁ )/A _tpt = eη(λ ₁ )・1/ 1-R(λ ₁ ) A(λ ₂ )/A _tpt = eη(λ ₂ )・1/1− R(λ ₂ ) A(λ ₃ )/A _tpt = eη(λ ₃ )・1/1− R (λ ₃ ) A _tpt = A (λ ₁ ) + A (λ ₂ ) + A (λ ₃ ) For any required spectral sensitivity characteristic, the spectral sensitivity characteristic is determined by the gate structure as the light receiving part. A photodetecting device comprising an electrostatic induction transistor according to claim 1, characterized in that the photodetecting device has a light-receiving sensitivity matching the above. 3. A step of preparing a semiconductor substrate of a predetermined conductivity type,
a step of forming a buried layer 71 on the substrate; a step of forming a thermal oxide film 72 and a protective film 73 on predetermined portions after removing impurities from the buried layer 71; a step of partially using the protective film 73 as a mask; a step of implanting ions, a step of removing the thermal oxide film 72 and the protective film 73 by etching, and then growing a high resistance layer 78 by an epitaxial method to form a thermal oxide film 76 on the surface; Diffusion windows for the source and gate are formed in the N ⁺ doped polysilicon layer 77.
During the CVD growth process, plasma etching is performed to leave only the n ⁺ polysilicon region 84 of the n ⁺ doped polysilicon layer 77, which is to become a source region in a later step, to form a semiconductor layer in the deep gate diffusion window region. After completely exposing the surface, boron deposition and drive-in diffusion are performed in an oxidizing atmosphere to form a deep gate diffusion region 81 and at the same time a source region 83, and the thermal oxide film 76 is selectively removed. After that, a step of performing a first boron ion implantation using the resist layer 79 as a protective mask, a step of removing the resist layer 79 and performing a second boron ion implantation to completely dope the gate region. A method for manufacturing a photodetecting device comprising a static induction transistor, comprising the step of: next growing a P ⁺ polysilicon layer or a tin oxide layer 86 by CVD on the gate region to form a gate electrode. 4. In the method according to claim 3,
After the second boron ion implantation, the entire surface is
Si ₃ N ₄ film or SiO ₂ film with a thickness of approximately 400 Å to 1000
A method for manufacturing an image sensor using a static induction transistor, characterized by adding a step of forming the image sensor within a range of . 5. Forming a high resistance epitaxial layer 91 on a predetermined conductivity type n ⁺ substrate, forming a thermal oxide film 93 on the high resistance epitaxial layer 91, opening a window in the source portion, and simultaneously forming a source A step of removing all the insulating film 93 except for the insulating film 93 that defines the part, a step of forming an n ⁺ doped polysilicon layer 94 on the entire surface of the treated surface, an n ⁺ doped polysilicon layer that will become a source electrode. After removing all the n ⁺ doped polysilicon layers 94 except 94, a PSG film 92 is grown by CVD on the entire surface, and then a window is opened in the PSG film 92 in the area where a deep gate diffusion region is to be formed. A step of performing heat treatment for reflowing the PSG film 92 to form a tapered PSG film 900. A step of performing heat treatment or drive-in after boron ion implantation using the reflowed PSG film as a mask. 1. A method of manufacturing a photodetecting device comprising an electrostatic induction transistor.