JPH051648B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a differential input operational amplifier constructed from CMOS devices, and particularly to an operational amplifier suitable for obtaining high gain and high speed operating characteristics.

[Background of the invention]

The most basic configuration of a CMOS operational amplifier is, for example, IEEE Journal of Solid-State Circuits.
It is shown in Fig. 4 of Vol.SC-17, No.6, December 1982 (referred to as literature) P.971. Figure 1 shows Figure 4 of the above-mentioned document with PMOS and NMOS replaced. In CMOS, the electrical characteristics of PMOS and NMOS are almost symmetrical, so even if this is done, they are functionally equivalent. The differential stage of the operational amplifier is M1
~M5. That is, a differential stage is configured by a common source-connected transistor pair M1 and M2 and these opposite conductivity types M3 and M4,
M5 controls its operating current. The gates of M3 and M4 are commonly connected, and the common gate node is M3.
It is connected to the drain of No. 3 to form a current mirror configuration. Furthermore, the drains of M1 and M3 are
The drains of M2 and M4 are connected, and M3 and M4 are
The active load is 1.M2. The drain of M3 is a reference of a current mirror, and is called an active load control node here. On the other hand, the drain of M4 is an output node that takes out an output signal to the next stage. The AC characteristics of the differential stage can be analyzed using the equivalent circuit shown in FIG. In the figure, the symbol g _M is the drain current amplification factor due to the gate-source voltage, and r is the differential resistance at saturation.
In Fig. 1, M1 and M2, M3 and M4 are transistors of the same size, and in the linear operation region, the potentials V ₁ and V ₂ and the potentials V ₃ and V ₄ can be considered to be approximately equal, so in Fig. 2 In g _M1 = g _M2 , r ₁ =
r ₂ , g _M3 = g _M4 , r ₃ = r ₄ . When solved under these conditions, the gain G becomes the following equation.

G=N ₀ /V ₁ -V ₂ =g _M2 (r ₂ r ₄ )...(1) Also, g _M = (2(W/L)βI) ^1/2 r=(λI) ^-1 . Here, (W/L) is the size of the MOS transistor, β is the channel conductance, λ is the channel length modulation effect coefficient, and I is the drain current. Substituting these values yields the following equation.

Here I=I ₀ /2, β in g _M2 =β _N , W/
L = (W/L), λ at r ₂ = λ _N , λ at r ₄
=λ _P.

On the other hand, the slew rate S is defined as a voltage value that changes per unit time and is expressed by the following equation.

S=I/ _CL ...(3) Here, _CL is the load capacity, and I is the current related to charging and discharging the load. Considering the slew rate for the voltage V ₄ in FIG. 1, it is sufficient to set I=I ₀ /2. Also, if we consider only the self-capacitance of M2 and M4 as the load amount C _L and ignore the loads such as M6, then
_CL becomes as follows.

C _L = C _J L _J・(W ₂ + W ₄ ) ...(4) C _J is the diffusion layer capacitance per unit area, L _J is the width of the diffusion layer, W ₂ and W ₄ are the M2 and M4 channels, respectively. It is the width. Substituting these values yields S=I ₀ /2C _J L _J (W ₂ + W ₄ )...(5). In general, W ₂ >>W ₄ , and setting W ₄ =0 in equation (5) gives the upper limit of the slew rate. When the slew rate S at this time is written as S _n , it becomes S _n =I ₀ /2C _J L _J W ₂ > S (6).

In equation (2), set (W/L) ₂ =W ₂ /L, solve for W ₂ , and substitute into equation (6) to obtain the relationship between the slew rate and gain.

S _n =2β _N /C _J L _J L (λ _P +λ _N ) ² G ² ...(7) In equation (7), the length of the diffusion layer L _J , the capacitance per unit area of the diffusion layer C _J , the channel The long modulation effect coefficients λ _P and λ _N and the channel conductance β _N are constants determined by the process. Further, the minimum dimension of the channel length L is determined depending on the process. Therefore, the maximum value of the slew rate is S _n ∝1/G ² ...(8), and if a gain is to be obtained, the slew rate will drop significantly.

For this reason, for example, in an integrator having a reset circuit as shown in FIG. 3, the reset time is approximately proportional to the reciprocal of the slew rate, so the reset time must be long. Furthermore, in the case of a voltage follower as shown in FIG. 4, the output cannot move faster than the slew rate, resulting in the disadvantage that it cannot follow changes in the input.

A similar problem can be seen in Fig. 18 of P978 of the above-mentioned document, or ISSCC83 Tochical
Figure 2 of Paper FAM17.5 (referred to as literature) P.314
This also occurs in a folded cascode amplifier as shown in . A cascode amplifier is characterized in that it can obtain a high gain without significantly reducing the slew rate compared to the basic amplifier shown in FIG. However, in this case as well, the result is that the slew rate is approximately proportional to the reciprocal of the gain.

Electronics Letters 3rd is a countermeasure to improve the slew rate for such problems.
February1983.Vol.19, No.3 (referred to as literature)
Shown on P92. This circuit is applied to a balanced differential stage, and monitors the two outputs of the differential stage, and when there is a difference in input voltage and one of the two outputs drops, it increases the bias voltage and increases the current. work. As a result, the gain decreases, but the slew rate can be improved.

However, this circuit cannot be applied to a differential stage with unbalanced output. It also had drawbacks such as large circuit scale and slow response when the output load of the differential stage was large.

[Purpose of the invention]

An object of the present invention is to provide an operational amplifier with improved slew rate.

[Summary of the invention]

The present invention incorporates a PMOS into a bias voltage generation circuit that supplies bias voltage to an operational amplifier and a differential stage.
and NMOS transistors connected in parallel, and apply one of the differential stage outputs to each gate, specifically the output of the side that is not connected to the next stage, that is, the output of the active load control node. operates to change the bias voltage in the direction of increasing the current of the differential stage when there is a difference in the input voltage and the output of the differential stage deviates from the operating point,
The present invention provides an operational amplifier equipped with a circuit that improves the slew rate.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. FIG. 5 shows an example in which the bias circuit according to the present invention is applied to the differential stage portion of the conventional circuit shown in FIG. Normally, a bias circuit has M8 and M9 connected directly or stacked in multiple stages. Here PMOS transistor M10 and NMOS
A bias control circuit 1 consisting of transistors M11 connected in parallel is inserted. The resistance of the PMOS transistor M10 becomes low when the voltage _V3 at the active load control node of the differential stage becomes low. On the other hand, the resistance of the NMOS transistor M11 decreases as the voltage _V3 increases. Therefore, the bias control circuit 1 functions as a variable resistor that has a low resistance when the voltage V ₃ becomes higher or lower than the operating point voltage. As a result, the bias voltage V ₆ is low when V ₁ V ₂ and increases as the difference between V ₁ and V ₂ increases, and M5
Increase the current and improve the slew rate. Also, even if there is a large load on the output V ₀ , the output V ₃ will only have a load due to its own capacitance, so
Bias voltage response is fast.

FIG. 6 shows how the bias voltages V ₆ and V ₇ and the current I flowing through the MOS transistor M5 change with respect to the output voltage V ₃ on the active load control node side of the differential stage output. In this example, the operating point voltage of the differential stage output _V3 is around -0.5V, and as it deviates from this, the bias voltage _V6 increases, and it can be seen that the current I flowing through M5 increases. The ratio of the gate voltage (V _P ) and the minimum value (I _P ) to the maximum value (I _M ) of the current that minimizes the bias voltage can be changed depending on the circuit configuration and the size design of each transistor. In the example shown in this figure, I _M /I _P = 3.4, and the slew rate is 3.4.
It turns out that it can be improved twice as much.

FIG. 7 shows a second embodiment in which the bias circuit of the present invention is applied to the differential stage of a folded cascode amplifier. A circuit example of the differential stage of a folded cascode amplifier is shown in Figure 18 on page 978 of the document. FIG. 7 uses a differential stage similar to the one in which the relationship between PMOS and NMOS in the literature diagram is reversed. In other words, the formal loads of the common source-connected transistor pair M1 and M2 are M3 and M4, but as a practical active load, the transistor pair M
8. The cascode type MOS transistor pair in which M9 and the transistor pair M10, M11 are cascode connected is the opposite conductivity type MOS transistor pair M6, M7.
connected via. In this embodiment as well, among the drains of a pair of cascode type MOS transistors that are active loads, the drains are connected not to the drains (the drains of M9) on the side that takes out the output signal to the next stage, but to the gates, and are connected to the nodes for active load control. Voltage of the drain on the other side (drain of M8) V ₆
is used to create a bias voltage for operating current control. In addition, in response to this,
The circuit of the differential stage itself having a folded cascode amplifier configuration is also slightly different from that described in the above-mentioned document.
In the circuit described in the literature, the gate and drain of the transistor corresponding to M11 on the opposite side, rather than M10 in FIG. 7, are connected. Even in this case, the operating point voltage and gain remain the same. However, when trying to apply feedback to the bias control circuit with voltage V ₆ to improve the slew rate, if a circuit equivalent to that in the literature is adopted for the differential stage, the influence of the load on output V ₀ will be routed through M11 and M10. It gets complicated. For this reason, there is a drawback that the response until the bias is changed is slow. On the other hand, if the gate and drain of M10 on the same side as M8 are connected as shown in Figure 7, the effect of the load on the output _V0 will not affect the output _V6 , and the above problem will be solved. Does not occur.

The bias circuit (MB1 to MB5) in Figure 7 is
Bias voltage V _{B1 that determines the current of PMOS transistors M3 and M4, bias voltage V B3} that determines the current of NMOS transistor M5, and voltages _{V 3 and} V ₄
A bias voltage V _B2 is created that determines the operating point voltage of . M5 to increase the slew rate
It is necessary to increase not only the current of M3 and M4 but also the current of M3 and M4. Therefore, at this time the bias voltage
V _B3 must be high and V _B1 must be low. This connects bias control circuit 1 to MB2 as shown in the figure.
This is automatically achieved by inserting it between MB5.

An example of the characteristics of the bias circuit in Fig. 7 is shown in Fig. 8.
As shown in the figure. The input voltage V ₆ to the bias circuit is plotted on the horizontal axis, and the output bias voltages V _B1 , V _B2 , and V _B3 are plotted on the vertical axis. Also, the current flowing through M5 at this time is shown at the same time. In this example, the operating point voltage V _P is −
It is around 1.5V, and the ratio of the minimum value I _P and maximum value I _M of the current
I _M /I _P is 3.8. In other words, it can operate at a slew rate that is up to 3.8 times higher than in normal operation when it deviates from the operating point.

Figure 9 shows the differential stage in Figure 7, a source follower composed of M20, M21, and M22 to M24, an output stage composed of M25, M26, and an MB.
This is a circuit example of an operational amplifier configured by combining a second bias circuit configured from MB6 to MB9. The output V ₇ of the differential stage is connected to M20 and M24 of the next stage, and is fed back from the output V ₀ of the amplifier output stage via a resistor R and a capacitor C. Due to the presence of this feedback path, the load on V ₇ becomes quite large. Therefore, the signal to bias control circuit 1
It is important to separate V ₆ from the influence of V ₇ , and M
Instead of coupling between the gate and source of M11, the coupling must be made on the M10 side as shown in the figure. Note that C and R are provided for phase compensation.

〔Effect of the invention〕

As described above, according to the present invention, when the difference between two input voltages is large, the current in the differential stage can be increased by changing the bias voltage, so that the slew rate can be significantly improved. For this reason, in conventional operational amplifiers, gain and slew rate were in a contradictory relationship, and the gain had to be kept low to ensure a certain slew rate, but by applying the present invention, high gain and high slew rate can be achieved at the same time. This makes it possible to obtain a high-performance operational amplifier.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional CMOS operational amplifier.
Figure 2 is the small signal equivalent circuit, Figure 3 is the connection diagram and output waveform of the integrator with reset, Figure 4 is the connection diagram and output waveform of the voltage follower, and Figure 5 is the differential stage of the conventional amplifier. 6 is the output characteristic of the bias circuit of FIG. 5, FIG. 7 is a circuit diagram of the bias control circuit of the present invention applied to a cascade amplifier, and FIG. 8 is the bias circuit of FIG. 7. FIG. 9 is a circuit diagram of the high performance operational amplifier of the present invention. 1...Bias voltage control circuit.

Claims (1)

[Scope of Claims] 1. A first pair of MOS transistors having common sources connected to each other; a second pair of MOS transistors having common gates connected to each other and serving as an active load for the first pair of MOS transistors;
and a constant current element for controlling the operating current connected to the common source node of the MOS transistor pair,
One drain node of the second MOS transistor pair is used as an output node for taking out an output signal to the next stage, and the other drain node is connected to a common gate node to serve as an active load control node. A CMOS type operational amplifier including a stage includes a bias voltage generation circuit connected to the active load control node and generating a bias voltage for controlling the constant current element according to the voltage of the bias voltage generation circuit, An operational amplifier characterized in that an operating current so large that the voltage of the control node deviates above or below the operating point voltage is applied to the differential stage. 2 The bias voltage generation means mentioned above is PMOS.
2. The operational amplifier according to claim 1, further comprising a circuit configured to connect an NMOS in parallel and to commonly apply the voltage of the active load control node to each gate. 3 The above differential stage is a folded cascode amplifier, which obtains an output signal from one drain node of a pair of cascode MOS transistors to the next stage.
2. The operational amplifier according to claim 1, wherein the voltage fed back to the bias voltage generating means is obtained from the active load control node, which is the drain on the other side connected to the gate node. 4. Claim 3, characterized in that in the first and second stage MOS transistor pairs constituting the cascode type MOS transistor pair, the drains of the MOS transistors on the same side are connected to the gates, respectively. operational amplifier.