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JPH051655B2 - - Google Patents
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JPH051655B2 - - Google Patents

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Publication number
JPH051655B2
JPH051655B2 JP8144085A JP8144085A JPH051655B2 JP H051655 B2 JPH051655 B2 JP H051655B2 JP 8144085 A JP8144085 A JP 8144085A JP 8144085 A JP8144085 A JP 8144085A JP H051655 B2 JPH051655 B2 JP H051655B2
Authority
JP
Japan
Prior art keywords
frequency
circuit
signal
noise
resonant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8144085A
Other languages
Japanese (ja)
Other versions
JPS61240718A (en
Inventor
Akihiro Fujiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP8144085A priority Critical patent/JPS61240718A/en
Publication of JPS61240718A publication Critical patent/JPS61240718A/en
Publication of JPH051655B2 publication Critical patent/JPH051655B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/10Means associated with receiver for limiting or suppressing noise or interference

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は受信機の雑音除去装置に関する。本発
明の受信機の雑音除去装置は、例えばFM方式ラ
ジオ受信機において復調信号に重畳される突発的
なマルチパス雑音やイグニツシヨン雑音等の雑音
の除去あるいは軽減するために用いられる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a noise removal device for a receiver. The receiver noise removal device of the present invention is used, for example, to remove or reduce noise such as sudden multipath noise and ignition noise superimposed on a demodulated signal in an FM radio receiver.

〔従来の技術〕[Conventional technology]

従来、例えばFM方式受信機において復調信号
に重畳される突発的な雑音を除去する方法とし
て、復調信号における雑音の発生区間をゲート回
路等により0ボルトにブランクし、かかる雑音発
生区間がブランクされた波形を直線的に補間する
方法が考案されている。
Conventionally, as a method for removing sudden noise superimposed on a demodulated signal in, for example, an FM receiver, the section where the noise occurs in the demodulated signal is blanked to 0 volts using a gate circuit, etc., and the section where the noise occurs is blanked. Methods have been devised to linearly interpolate waveforms.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の方法による場合、波形を直線的に補間し
ているため、比較的に短時間の雑音に対してしか
有効でない、波形の接続点がいびつになる、補間
部分に前後の信号情報が反映されないなどの問題
点がある。
In the above method, the waveform is interpolated linearly, so it is only effective against relatively short-term noise, the connection points of the waveform are distorted, and the previous and subsequent signal information is not reflected in the interpolated part. There are other problems.

〔問題点を解決するための手段〕[Means for solving problems]

第1図には、上述の問題点を解決するための本
発明に関する受信機の雑音除去装置が示される。
FIG. 1 shows a receiver noise removal device according to the present invention for solving the above-mentioned problems.

第1図において、1は復調信号に重畳される雑
音を検出する雑音検出回路、2は該雑音検出回路
により雑音が検出されている期間に渡り該復調信
号の通過をしや断するゲート回路、3は該ゲート
回路を通過した後の復調信号が通過される共振回
路、4は該復調信号の主たる信号周波数を検出す
る周波数検出回路、5は該雑音検出回路により雑
音が検出されていない期間中は該共振回路の共振
周波数を該復調信号の信号周波数よりも十分に大
とし、雑音が検出されている期間中は該共振回路
の共振周波数を該周波数検出回路により検出され
た信号周波数とするように該共振信号を制御し、
復調信号の主たる周波数信号を抽出すると共に、
ゲート回路にしや断されることにより復調信号の
周波数に重畳する不要周波数成分を除去する制御
回路である。
In FIG. 1, 1 is a noise detection circuit that detects noise superimposed on a demodulated signal; 2 is a gate circuit that prevents passage of the demodulated signal during a period when noise is detected by the noise detection circuit; 3 is a resonant circuit through which the demodulated signal after passing through the gate circuit is passed; 4 is a frequency detection circuit that detects the main signal frequency of the demodulated signal; and 5 is a period during which noise is not detected by the noise detection circuit. The resonant frequency of the resonant circuit is set to be sufficiently higher than the signal frequency of the demodulated signal, and during the period when noise is detected, the resonant frequency of the resonant circuit is set to the signal frequency detected by the frequency detection circuit. controlling the resonance signal to
While extracting the main frequency signal of the demodulated signal,
This is a control circuit that removes unnecessary frequency components that are superimposed on the frequency of the demodulated signal by being cut off by the gate circuit.

共振回路3は例えば第2図に概念的に示される
ように、可変の抵抗器R、インダクタLおよびキ
ヤパシタCで構成することが可能である。この共
振回路3は、第3図に示されるように共振周波数
f(r)に共振峰を持つ周波数特性を持つ低域フイル
タであり、共振周波数f(u)および共振の鋭さQは
それぞれ、 f(r)=1/2π√・ Q=R/2π・f(r)・L により決定される。
The resonant circuit 3 can be composed of a variable resistor R, an inductor L, and a capacitor C, as conceptually shown in FIG. 2, for example. As shown in FIG. 3, this resonant circuit 3 is a low-pass filter with frequency characteristics having a resonant peak at the resonant frequency f(r), and the resonant frequency f(u) and resonance sharpness Q are respectively f Determined by (r)=1/2π√・Q=R/2π・f(r)・L.

また周波数検出回路4は例えば第4図に示され
るようなF−V(周波数−電圧)変換器により構
成することが可能である。このF−V変換器はリ
ミツタ41、微分回路42、検波回路43および
積分回路44により構成される。
Further, the frequency detection circuit 4 can be constructed by, for example, an F-V (frequency-voltage) converter as shown in FIG. This F-V converter is composed of a limiter 41, a differentiation circuit 42, a detection circuit 43, and an integration circuit 44.

〔作用〕[Effect]

第1図装置の動作が第5図〜第11図を参照し
て以下に説明される。
The operation of the apparatus of FIG. 1 will be described below with reference to FIGS. 5-11.

第5図は第1図装置の各部信号波形図であり、
同図中、(a)は復調前の雑音が重畳された受信波S
(1)、(b)は雑音検出回路1からの検出信号S(2)、(c)
は受信波を検波復調した雑音が重畳された復調信
号S(3)、(d)はゲート回路2からの出力信号S(4)、
(e)は共振回路3からの出力信号S(5)の各信号波形
である。
FIG. 5 is a signal waveform diagram of each part of the device shown in FIG. 1,
In the figure, (a) is the received wave S with superimposed noise before demodulation.
(1), (b) are detection signals S(2), (c) from noise detection circuit 1
is the demodulated signal S(3) with superimposed noise obtained by detecting and demodulating the received wave, (d) is the output signal S(4) from the gate circuit 2,
(e) shows each signal waveform of the output signal S(5) from the resonant circuit 3.

受信波に雑音が重畳されたときには信号強度が
変化しかつ高域周波数成分が増加するので、雑音
検出回路1はシグナルレベルの変動の高域成分を
取り出すことによつて雑音を検出し、検出信号S
(2)を出力する。この検出信号S(2)によりゲート回
路2が導通、しや断され、雑音が重畳された復調
信号S(3)の雑音発生区間が除かれてゲート出力信
号S(4)が得られる。この出力信号S(4)は次に共振
回路3に入力される。共振回路3を通過した復調
信号は周波数検出回路4に入力される。周波数検
出回路4は例えばF−V変換器であり、その場合
その検出出力としては第6図に示されるように、
復調信号の成分周波数に正比例して電圧レベルが
増加する検出信号は出力される。
When noise is superimposed on the received wave, the signal strength changes and the high frequency component increases. Therefore, the noise detection circuit 1 detects the noise by extracting the high frequency component of the signal level fluctuation and converts it into a detected signal. S
Output (2). The gate circuit 2 is turned on and off by this detection signal S(2), and the noise generation section of the demodulated signal S(3) on which noise is superimposed is removed to obtain the gate output signal S(4). This output signal S(4) is then input to the resonant circuit 3. The demodulated signal that has passed through the resonant circuit 3 is input to the frequency detection circuit 4. The frequency detection circuit 4 is, for example, an F-V converter, in which case its detection output is as shown in FIG.
A detection signal whose voltage level increases in direct proportion to the component frequency of the demodulated signal is output.

共振回路3は、雑音が発生していない時には第
7図に示されるように、その共振周波数f(r)が復
調信号の成分周波数f(s)よりも十分に高いところ
に設定され、かつ共振の鋭さQが低くなるように
制御回路5により各定数R、L、Cが制御されて
おり、したがつて雑音発生のない時には受信機か
らの復調信号S(3)をすべてそのまま通過させ、通
常の受信状態となる。
When no noise is generated, the resonant circuit 3 has its resonant frequency f(r) set sufficiently higher than the component frequency f(s) of the demodulated signal, as shown in FIG. The constants R, L, and C are controlled by the control circuit 5 so that the sharpness Q of is in the receiving state.

一方、雑音発生が雑音検出回路1により検出さ
れると、その雑音発生区間では共振回路3の周波
数特性は第8図に示されるように、共振周波数f
(r)が周波数検出回路4で検出された復調信号の成
分周波数f(s)と一致し、かつ共振の鋭さQが高く
なるように(例えば、Q≒f(s)/10程度)、周波
数検出回路4の検出出力に基づき制御回路5によ
り共振回路3の各定数が制御される。第9図には
周波数検出回路4からの検出信号電圧レベルに対
してのf(r)とQはともに検出信号電圧レベルに正
比例して増加する特性となつており、それにより
共振周波数f(r)と復調信号の成分周波数f(s)とが
常に一致するようになつている。
On the other hand, when noise generation is detected by the noise detection circuit 1, the frequency characteristics of the resonance circuit 3 in the noise generation section are as shown in FIG.
(r) matches the component frequency f(s) of the demodulated signal detected by the frequency detection circuit 4, and the frequency Each constant of the resonant circuit 3 is controlled by the control circuit 5 based on the detection output of the detection circuit 4. In FIG. 9, both f(r) and Q with respect to the detection signal voltage level from the frequency detection circuit 4 have a characteristic that increases in direct proportion to the detection signal voltage level, so that the resonant frequency f(r ) and the component frequency f(s) of the demodulated signal always match.

このようにして共振周波数f(r)と共振の鋭さQ
が設定された共振回路3を、雑音発生区間が除去
された波形の復調信号S(4)が通過すると、その共
振の効果により除去された雑音発生区間が補間さ
れ、共振回路3からは残音成分が除去された復調
信号S(5)が得られる。また共振周波数f(r)を同時
に共振の鋭さQも高くなるように変化させてお
り、それにより波形の雑音発生区間が長くなるよ
うな場合にも該区間を十分に補間することが可能
となる。すなわち、雑音検出時のゲート回路2遮
断により雑音検出前に復調信号レベルを保持して
いる共振回路3の復調信号の波形は、雑音検出時
には第5図dに示すように、瞬時に零になり、短
時間だけ零レベルが維持され、さらに短時間後に
零レベルから一定レベルに復帰する。この場合の
共振回路3を通過する信号の周波数分布を検討す
ると、この周波数分布は復調信号の周波数に対し
て、第5図dにおける復調信号に段階状の波形変
化による高調波成分が重畳して含でいる。そこで
本願における共振回路3では、共振回路の共振周
波数が周波数検出回路により設定され復調波信号
に重畳した高調波成分が除去され復調波信号のみ
が抽出されることで元波形に近い信号が得られる
ことになる。雑音検出回路1からの検出回路S(2)
がなくなれば周波数特性は第7図の元の状態に戻
る。
In this way, the resonant frequency f(r) and the resonance sharpness Q
When the demodulated signal S(4) of the waveform from which the noise generation section has been removed passes through the resonant circuit 3 where A demodulated signal S(5) from which the components have been removed is obtained. In addition, the resonant frequency f(r) is changed so that the resonance sharpness Q is also increased at the same time, which makes it possible to sufficiently interpolate the noise generation section of the waveform even when the section becomes long. . In other words, the waveform of the demodulated signal of the resonant circuit 3, which maintains the demodulated signal level before noise detection due to the gate circuit 2 being shut off when noise is detected, instantly becomes zero when noise is detected, as shown in FIG. 5d. , the zero level is maintained for a short period of time, and returns to a constant level from the zero level after a further short period of time. Examining the frequency distribution of the signal passing through the resonant circuit 3 in this case, this frequency distribution shows that harmonic components due to stepwise waveform changes are superimposed on the demodulated signal in FIG. 5d with respect to the frequency of the demodulated signal. Contains. Therefore, in the resonant circuit 3 of the present application, the resonant frequency of the resonant circuit is set by the frequency detection circuit, the harmonic components superimposed on the demodulated wave signal are removed, and only the demodulated wave signal is extracted, thereby obtaining a signal close to the original waveform. It turns out. Detection circuit S(2) from noise detection circuit 1
When the frequency characteristic disappears, the frequency characteristic returns to the original state shown in FIG.

第10図には、残音発生持時と雑音発生のない
時との共振周波数f(r)と共振の鋭さQの変化の状
態が示される。この場合、共振周波数f(r)は雑音
発生時に5kHz、雑音のない時に1kHzであり、共
振の鋭さQは雑音発生時に350程度の、雑音のな
い時に0.6程度に設定される。前述の高調波成分
を除去するために、本図に示すように、共振回路
3に雑音発生時の検出された共振周波数の鋭さQ
が設定され、第5図dに示すように、ゲート回路
2により形成される復調波に含まれる高調波成分
が除去される。
FIG. 10 shows how the resonant frequency f(r) and the sharpness of resonance Q change when after-sound is generated and when no noise is generated. In this case, the resonance frequency f(r) is 5 kHz when noise occurs and 1 kHz when there is no noise, and the resonance sharpness Q is set to about 350 when noise occurs and about 0.6 when there is no noise. In order to remove the harmonic components mentioned above, as shown in this figure, the sharpness Q of the resonance frequency detected when noise occurs is applied to the resonance circuit 3.
is set, and the harmonic components contained in the demodulated wave formed by the gate circuit 2 are removed, as shown in FIG. 5d.

第4図に示される周波数検出回路としてのF−
V変換器についてもその動作を説明する。第11
図は第4図装置の各部信号波形図であり、それぞ
れ(a)は共振回路3からの復調信号S(5)、(b)はリミ
ツタ41のリミツト出力信号S(41)、(c)は微分回
路42の微分信号S(42)、(d)は検波回路43の検
波信号S(43)、(d)は積分回路44の積分信号S
(44)の信号波形である。
F- as a frequency detection circuit shown in FIG.
The operation of the V converter will also be explained. 11th
The figure is a signal waveform diagram of each part of the device shown in FIG. The differential signal S(42) of the differentiating circuit 42, (d) is the detection signal S(43) of the detection circuit 43, and (d) is the integral signal S of the integrating circuit 44.
This is the signal waveform of (44).

共振回路3から入力される復調信号S(5)はリミ
ツタ41によりリミツトをかけられてパルス状の
リミツト出力信号S(41)が出力されるが、この
際、微小入力に対しては出力信号S(41)が出力
されないように不感帯が設けられている。出力信
号S(41)は次に微分回路42により微分され、
出力信号S(41)のゼロ交差点付近でパルス状の
微分信号S(42)が出力される。これを検波回路
43で検波整流することにより極性が同一方向の
検波信号S(43)を得、これを積分回路44で積
分する。したがつて結局、積分回路S(44)は入
力された復調信号S(5)のゼロ交差の密度、すなわ
ち周波数に比例した電圧レベルの出力となる。
The demodulated signal S(5) inputted from the resonant circuit 3 is limited by the limiter 41 and a pulse-shaped limit output signal S(41) is output. A dead zone is provided so that (41) is not output. The output signal S (41) is then differentiated by the differentiating circuit 42,
A pulse-like differential signal S (42) is output near the zero crossing point of the output signal S (41). By detecting and rectifying this in the detection circuit 43, a detection signal S(43) having the same polarity is obtained, which is integrated in the integrating circuit 44. Therefore, in the end, the integrating circuit S(44) outputs a voltage level proportional to the density of zero crossings, that is, the frequency, of the input demodulated signal S(5).

〔実施例〕〔Example〕

本発明の一実施例としての受信機の雑音除去装
置が第12図に示される。この実施例装置は本発
明をデイジタル回路で構成した場合の例である。
A receiver noise removal device as an embodiment of the present invention is shown in FIG. This embodiment of the device is an example in which the present invention is implemented using a digital circuit.

第12図において、受信機からの復調信号はま
ずゲート回路を介してAD変換器10に入力され
てデイジタル信号に変換された後に共振回路11
に導かれる。共振回路11は乗算器C0〜4、1
サンプル遅延器D1〜D4、加算器A1〜A3を
含み構成される。ここで乗算器C0〜C4の各係
数はC0〜C4である。また1サンプル遅延器はシ
フト・レジスタで構成される。この共振回路11
における共振周波数をf(r)、共振の鋭さをQとす
ると、乗算器C0〜C4の各係数C0〜C4は、 C0=(T2+2βT)/(T2+4α+2βT) C1=2T2/T2+2βT C2=(T2−2βT)/(T2+2βT) C3=(8α−2T2)/(T2+2βT+4α) C4=(2βT−T2−4α)/ (T2+2βT+4α) (ただし、ここで、α=1/4π2・f(r)2、β=
1/2π・f(r)・Q、Tはサンプリング周期、) で表すことができる。
In FIG. 12, a demodulated signal from a receiver is first inputted to an AD converter 10 via a gate circuit, converted into a digital signal, and then sent to a resonant circuit 11.
guided by. The resonant circuit 11 includes multipliers C0 to C4, 1
It is configured to include sample delay devices D1 to D4 and adders A1 to A3. Here, the coefficients of the multipliers C0 to C4 are C0 to C4 . Further, the 1-sample delay device is composed of a shift register. This resonant circuit 11
Let f ( r ) be the resonant frequency at 2 /T 2 +2βT C 2 = (T 2 - 2βT) / (T 2 + 2βT) C 3 = (8α - 2T 2 ) / (T 2 + 2βT + 4α) C 4 = (2βT - T 2 - 4α) / (T 2 +2βT+4α) (However, here, α=1/4π 2・f(r) 2 , β=
It can be expressed as 1/2π・f(r)・Q, where T is the sampling period.

共振回路11の出力信号はDA変換器12およ
びF−V変換器13に導かれる。F−V変換器1
3はリミツタ131、微分回路132、検波回路
133、積分回路134で構成される。微分回路
132は遅延器D5、係数−1の乗算器K−1、
加算器A4に含み構成される。積分器134は乗
算器K1〜K3、遅延器D1,D2、加算器A
5,A6を含み構成される。乗算器K1〜K3の
各係数はK1〜K3である。F−V変換器13にお
ける積分時定数が1.6ミリ秒である時、乗算器K
1〜K3の各係数K1〜K3は、 K1≒7.8×10-3 K2=1 K3=9.8×10-1 となる。
The output signal of the resonant circuit 11 is guided to a DA converter 12 and an F-V converter 13. F-V converter 1
3 is composed of a limiter 131, a differentiation circuit 132, a detection circuit 133, and an integration circuit 134. The differentiation circuit 132 includes a delay device D5, a multiplier K-1 with a coefficient of -1,
It is included in adder A4. The integrator 134 includes multipliers K1 to K3, delay devices D1 and D2, and adder A.
5, A6. The respective coefficients of multipliers K1 to K3 are K1 to K3 . When the integration time constant in the F-V converter 13 is 1.6 ms, the multiplier K
The coefficients K1 to K3 of K1 to K3 are K1≈7.8 × 10-3 K2 =1 K3 =9.8× 10-1 .

F−V変換器13の出力信号は制御回路14に
導かれる。制御回路14には図示しない雑音検出
回路から雑音検出信号が導かれる。この制御回路
14はマイクロ・コンピユータを含み構成するこ
ともまた完全な論理回路で構成することも可能で
ある。
The output signal of the F-V converter 13 is guided to a control circuit 14. A noise detection signal is introduced to the control circuit 14 from a noise detection circuit (not shown). The control circuit 14 may include a microcomputer or may consist of a complete logic circuit.

第12図の実施例装置の動作を説明すると、こ
れは基本的には第1図装置と同じである。本実施
例装置では、共振回路11の共振周波数f(r)と共
振の鋭さQは、制御回路14からの制御により乗
算器C0〜C4の各係数C0〜C4を変えることに
よつて変化させることが可能である。したがつて
雑音発生時と雑音のない時とで例えば第10図に
示されるような特性でf(r)とQを変化させるべ
く、各係数C0〜C4を前述の式に従つて変えれば
よい。
The operation of the apparatus of the embodiment shown in FIG. 12 will be explained. This is basically the same as the apparatus shown in FIG. In the device of this embodiment, the resonant frequency f(r) and resonance sharpness Q of the resonant circuit 11 are changed by changing the coefficients C0 to C4 of the multipliers C0 to C4 under control from the control circuit 14. It is possible to do so. Therefore, in order to change f(r) and Q with the characteristics shown in FIG. 10 between when noise occurs and when there is no noise, each coefficient C 0 to C 4 should be changed according to the above formula. Bye.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、復調信号の雑音発生区間をブ
ランクして補間する場合にも、共振回路の効果に
より補間部分の波形の接続は滑らかになり、かつ
補間部分にその前後の信号情報が反映されるの
で、ブランク部分の補間の歪は従来方式に比べて
格段に小さくすることができる。
According to the present invention, even when interpolating by blanking the noise generation section of the demodulated signal, the effect of the resonant circuit makes the waveform connection of the interpolated part smooth, and the signal information before and after it is reflected in the interpolated part. Therefore, the distortion of interpolation in the blank portion can be significantly reduced compared to the conventional method.

また雑音発生時に共振の鋭さQを高めることに
より、ブランク時間が長くなつても共振回路の特
続性によつて十分に補間が可能である。さらにF
−V変換器の積分時定数を大きく取ることにより
長時間に渡る復調信号の平均周波数を検出するこ
とができ、したがつて、それにより良好なまるめ
を行うことができる。
Furthermore, by increasing the resonance sharpness Q when noise occurs, sufficient interpolation is possible due to the characteristics of the resonant circuit even if the blank time becomes long. Further F
By setting a large integration time constant of the -V converter, it is possible to detect the average frequency of the demodulated signal over a long period of time, and therefore to perform better rounding.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に関する受信機の雑音除去装置
のブロツク図、第2図は第1図における共振回路
を概念的に表した図、第3図は第2図の回路の周
波数特性図、第4図は第1図における周波数検出
回路の一構成例を示すブロツク図、第5図は第1
図装置の各部信号波形図、第6図は第4図回路の
入出力特性図、第7図、第8図は雑音がある時と
ない時との共振回路の周波数特性図、第9図は第
4図回路出力に対するf(r)とQの変化特性図、第
10図は雑音のある時とない時のf(r)とQの変化
を示す図、第11図は第4図の各部信号波形図、
第12図は本発明の一実施例としての受信機の雑
音除去装置のブロツク図である。 1……雑音検出回路、2……ゲート回路、3…
…共振回路、4……周波数検出回路、5……制御
回路、10……AD変換器、11……共振回路、
12……DA変換器、13……F−V変換器、1
4……制御回路。
FIG. 1 is a block diagram of a receiver noise canceling device according to the present invention, FIG. 2 is a diagram conceptually representing the resonance circuit in FIG. 1, and FIG. 3 is a frequency characteristic diagram of the circuit in FIG. Figure 4 is a block diagram showing an example of the configuration of the frequency detection circuit in Figure 1, and Figure 5 is a block diagram of the frequency detection circuit in Figure 1.
Figure 6 is the input/output characteristic diagram of the circuit shown in Figure 4. Figure 7 and Figure 8 are frequency characteristics diagrams of the resonant circuit with and without noise. Figure 4 shows the change characteristics of f(r) and Q with respect to the circuit output. Figure 10 shows the changes in f(r) and Q with and without noise. Figure 11 shows each part of Figure 4. Signal waveform diagram,
FIG. 12 is a block diagram of a receiver noise removal device as an embodiment of the present invention. 1...Noise detection circuit, 2...Gate circuit, 3...
... Resonance circuit, 4 ... Frequency detection circuit, 5 ... Control circuit, 10 ... AD converter, 11 ... Resonance circuit,
12...DA converter, 13...F-V converter, 1
4...Control circuit.

Claims (1)

【特許請求の範囲】 1 復調信号に重畳される雑音を検出する雑音検
出回路、 該雑音検出回路により雑音が検出されている期
間に渡り該復調信号の通過をしや断するゲート回
路、 該ゲート回路を通過した後の復調信号が通過さ
れる共振回路、 該復調信号の主たる信号周波数を検出する周波
数検出回路、および、 該雑音検出回路により雑音が検出されていない
期間中は、該共振回路の共振周波数を該復調信号
の信号周波数よりも十分に大とし、雑音が検出さ
れている期間中は該共振回路の共振周波数を該周
波数検出回路により検出された信号周波数とする
ように該共振信号を制御し、復調信号の主たる周
波数信号を抽出すると共に、ゲート回路にしや断
されることにより復調信号の周波数に重畳する不
要周波数成分を除去する制御回路、 を備える受信機の雑音除去装置。
[Claims] 1. A noise detection circuit that detects noise superimposed on a demodulated signal; a gate circuit that prevents passage of the demodulated signal during a period during which noise is detected by the noise detection circuit; and the gate. A resonant circuit through which the demodulated signal passes after passing through the circuit, a frequency detection circuit that detects the main signal frequency of the demodulated signal, and a frequency detection circuit that detects the main signal frequency of the demodulated signal; The resonant frequency is set to be sufficiently higher than the signal frequency of the demodulated signal, and the resonant signal is set so that the resonant frequency of the resonant circuit is set to the signal frequency detected by the frequency detection circuit during a period in which noise is detected. A noise removal device for a receiver, comprising: a control circuit that controls and extracts a main frequency signal of a demodulated signal, and removes unnecessary frequency components that are superimposed on the frequency of the demodulated signal by being cut off by a gate circuit.
JP8144085A 1985-04-18 1985-04-18 Noise eliminator of receiver Granted JPS61240718A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8144085A JPS61240718A (en) 1985-04-18 1985-04-18 Noise eliminator of receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8144085A JPS61240718A (en) 1985-04-18 1985-04-18 Noise eliminator of receiver

Publications (2)

Publication Number Publication Date
JPS61240718A JPS61240718A (en) 1986-10-27
JPH051655B2 true JPH051655B2 (en) 1993-01-08

Family

ID=13746452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8144085A Granted JPS61240718A (en) 1985-04-18 1985-04-18 Noise eliminator of receiver

Country Status (1)

Country Link
JP (1) JPS61240718A (en)

Also Published As

Publication number Publication date
JPS61240718A (en) 1986-10-27

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