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JPH0516656B2 - - Google Patents
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JPH0516656B2 - - Google Patents

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Publication number
JPH0516656B2
JPH0516656B2 JP61123173A JP12317386A JPH0516656B2 JP H0516656 B2 JPH0516656 B2 JP H0516656B2 JP 61123173 A JP61123173 A JP 61123173A JP 12317386 A JP12317386 A JP 12317386A JP H0516656 B2 JPH0516656 B2 JP H0516656B2
Authority
JP
Japan
Prior art keywords
substrate
stage
voltage
electrode
energy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61123173A
Other languages
Japanese (ja)
Other versions
JPS62279626A (en
Inventor
Keiki Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMU SETETSUKU KK
Original Assignee
EMU SETETSUKU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EMU SETETSUKU KK filed Critical EMU SETETSUKU KK
Priority to JP12317386A priority Critical patent/JPS62279626A/en
Publication of JPS62279626A publication Critical patent/JPS62279626A/en
Publication of JPH0516656B2 publication Critical patent/JPH0516656B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体基板に対しプラズマにより
不純物のドーピングを行なう不純物ドーピング方
法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an impurity doping method for doping a semiconductor substrate with an impurity using plasma.

〔従来の技術〕[Conventional technology]

半導体の低温プロセスは熱変成や不純物分布の
変化、ライフタイムの変化を抑制する上から従来
型デバイス製造の工程でも要望されていたが、特
に最近台頭している3次元ICの場合に、上層の
デバイスを製造する際既に形成されている下層デ
バイスに対する悪影響を避けるため欠くことので
きない技術として、半導体デバイス微細化の傾向
とともに一層渇望されている。
Low-temperature processing of semiconductors has been required in conventional device manufacturing processes because it suppresses thermal metamorphosis, changes in impurity distribution, and changes in lifetime. It is an indispensable technology for avoiding adverse effects on the underlying devices that have already been formed during device manufacturing, and is becoming more and more sought after as semiconductor devices become smaller.

半導体基板に対する不純物の導入は現在熱拡散
法に代りイオン注入法が主流となりつつあるが、
特に軽い元素のボロンの場合は深く注入され易く
浅いP領域を作ることは困難であつた。
Currently, ion implantation is becoming the mainstream method for introducing impurities into semiconductor substrates, replacing thermal diffusion.
In particular, boron, which is a light element, is easily implanted deeply and it is difficult to form a shallow P region.

しかし、これも10kev程度までエネルギーを下
げれば可能であるが、この場合はビーム電流が低
下するので処理時間が長くなり量産性が落ちる問
題がある。また、注入後の不純物の活性化とダメ
ージ回復のため比較的高温の熱処理が必要となる
等基板の深さ方向の微細化に対して種々の問題が
あつた。
However, this is also possible if the energy is lowered to about 10 keV, but in this case, the beam current decreases, which increases processing time and reduces mass productivity. Furthermore, there are various problems with miniaturization in the depth direction of the substrate, such as the need for heat treatment at a relatively high temperature for activation of impurities after implantation and damage recovery.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のように、半導体基板に対する不純物の導
入は、軽い元素のボロンの場合浅いP領域を作る
ことが困難であり処理に長時間を要しあるいは高
温の熱処理を必要とするなど多量生産に適さない
各種の問題があつた。
As mentioned above, when introducing impurities into a semiconductor substrate, it is difficult to create a shallow P region in the case of boron, which is a light element, and the process takes a long time or requires high-temperature heat treatment, making it unsuitable for mass production. Various problems arose.

この発明はこのような問題点を解決するために
なされたもので不純物の浅い領域を作ることが容
易であり比較的短時間に行なうことができしかも
高温の熱処理を必要としない多量生産に適した半
導体基板に対する不純物のドーピング方法を提供
することを目的としている。
This invention was made to solve these problems, and is suitable for mass production because it is easy to create a shallow region of impurities, can be done in a relatively short time, and does not require high-temperature heat treatment. It is an object of the present invention to provide a method for doping impurities into a semiconductor substrate.

〔問題点を解決するための手段および作用〕 この発明のドーピング方法は、プラズマ発生装
置のステージ上に半導体基板を配置するとともに
ドープする元素と同じ元素を含むシリコン電極を
対向電極として設け、前記ステージと対応電極の
間にステージ側を負として印加した直流電圧を極
性転換して与えることによりプラズマを発生させ
イオン注入により不純物の注入を行なうことを特
徴とし、電圧の極性を反転させることによりエネ
ルギーをもつた電子を基板に照射しそのエネルギ
を基板格子に与えることにより不純物原子の拡散
を促するものである。この加速電圧を制御するこ
とにより所望の深さまでの拡散を行なう。
[Means and effects for solving the problems] In the doping method of the present invention, a semiconductor substrate is placed on a stage of a plasma generation device, and a silicon electrode containing the same element as the element to be doped is provided as a counter electrode, and the stage The method is characterized in that plasma is generated by applying a DC voltage with the stage side being negative between the electrode and the corresponding electrode with the polarity reversed, and impurities are implanted by ion implantation.By reversing the polarity of the voltage, energy is released. The diffusion of impurity atoms is promoted by irradiating the substrate with the retained electrons and imparting the energy to the substrate lattice. Diffusion to a desired depth is achieved by controlling this accelerating voltage.

〔実施例〕〔Example〕

以下図面を参照してこの発明の一実施例を説明
する。
An embodiment of the present invention will be described below with reference to the drawings.

この実施例はN型基板にボロンを拡散する場合
を示すものである。
This embodiment shows the case where boron is diffused into an N-type substrate.

第1図において、1は平行平板型のプラズマ発
生装置であり、2はそのステージであり、3は対
向電極、4はヒータを示している。
In FIG. 1, 1 is a parallel plate type plasma generator, 2 is its stage, 3 is a counter electrode, and 4 is a heater.

ステージ2の上にシリコンのN型単結晶基板5
を載置してこれを負極とし、その上部50mmに設け
られた対向電極3にP型の比抵抗0.05Ωの単結晶
で作られたものを配設する。ステージ2はヒータ
4により200〜400℃に加熱しておく。プラズマ発
生装置1中に、H2をベースとするB2H62000ppm
の希釈ガスを圧力2〜4.5Torrで封入し、ステー
ジ2と対向電極3の間に400〜600Vの直流電圧を
印加し、プラズマ放電を行なう。
A silicon N-type single crystal substrate 5 is placed on the stage 2.
was placed and used as a negative electrode, and a P-type single crystal with a specific resistance of 0.05 Ω was placed on the counter electrode 3 provided 50 mm above the negative electrode. Stage 2 is heated to 200 to 400°C by heater 4. In the plasma generator 1, B 2 H 6 2000ppm based on H 2
diluent gas is sealed at a pressure of 2 to 4.5 Torr, and a DC voltage of 400 to 600 V is applied between the stage 2 and the counter electrode 3 to generate plasma discharge.

なお、図中6は直電源、7は極性転換器を示し
ている。
In the figure, 6 indicates a direct power supply, and 7 indicates a polarity converter.

すなわち、第3図に示すように、30分間ステー
ジ2の側したがつてN型単結晶基板5が負となる
ように電圧を印加しその後極性を反転し10分間電
子入射を行なうサイクルを2回実施した時の拡散
層の拡がり抵抗は第2図に示す通りで拡散深さは
0.1μであつた。
That is, as shown in FIG. 3, a cycle was repeated twice in which a voltage was applied for 30 minutes so that the N-type single crystal substrate 5 became negative on the side of the stage 2, and then the polarity was reversed and electron injection was performed for 10 minutes. The spreading resistance of the diffusion layer during the test is as shown in Figure 2, and the diffusion depth is
It was 0.1μ.

なお、この極性転換は第3図のように拡散深さ
によつてサイクルと正負電圧の絶体値を適当に選
ぶものである。
Incidentally, this polarity change is carried out by appropriately selecting the cycle and the absolute values of the positive and negative voltages depending on the diffusion depth, as shown in FIG.

かくして、その後のランプアニールでも特性の
変化はなく、不純物は充分活性化していることが
明らかとなつた。またDLTSによるデープレベル
の測定においても格子欠かん及び重金属による準
位も見られなかつた。
Thus, it was revealed that the characteristics did not change even after the subsequent lamp annealing, and that the impurities were sufficiently activated. In addition, no lattice defects or heavy metal levels were observed in deep level measurements using DLTS.

なお、プラズマ中の陰極降下は数十ボルトで、
これによる正イオンの衝撃は低エネルギーである
が衝突断面は大きいためごく表面に限られるが欠
かんや表面粗れが発生する。
Note that the cathode fall in the plasma is several tens of volts,
Although the impact of positive ions caused by this has low energy, the impact cross section is large, so although it is limited to the surface, surface roughness will inevitably occur.

これらの欠かんは基板原子の移動、原子配列の
乱れ、原子空孔や格子間原子の対をも生ずるもの
と考えられる。
These defects are thought to cause movement of substrate atoms, disorder of atomic arrangement, and pairs of atomic vacancies and interstitial atoms.

次にエネルギーをもつたボロンイオンはこの原
子空孔と位置交換を繰返したまた格子間にある原
子は格子点にある原子と玉突きで位置交換してそ
れぞれ拡散する。
Next, energetic boron ions repeatedly exchange positions with these atomic vacancies, and interstitial atoms exchange positions with atoms at lattice points and diffuse respectively.

このように結晶中に発生した点欠かんが関与し
たVacancy機構とINTERSTITIALCY機構で拡
散するものと推察される。
It is inferred that the diffusion occurs through the Vacancy mechanism and INTERSTITIALCY mechanism involving the dot holes generated in the crystal.

しかし、この拡散は入射エネルギーが少ないた
め基板表層下部の構成格子に与えるエネルギーが
小さいのと格子に置き変えられたボロン原子は負
のアクセプタイオンとなつているため外部電界に
より反撥され内部への拡散は難しい。
However, since the incident energy for this diffusion is low, the energy imparted to the constituent lattice at the bottom of the surface layer of the substrate is small, and the boron atoms replaced by the lattice become negative acceptor ions, so they are repelled by the external electric field and diffuse into the interior. is difficult.

そこで、ある程度表面層に高濃度のボロンがト
ープされた時点で印加電圧の極正を反転する。
Therefore, the polarity of the applied voltage is reversed when the surface layer is doped with boron at a high concentration to some extent.

これによつて基板にはエネルギーをもつた電子
が照射されることになるが、この加速電圧を制御
することによつて所望の拡散深さまでの基板格子
に電子の保有するエネルギーを与え、しかも反転
によつて基板側が正極となるので基板正面に局在
していたアクセプタイオンのボロンはこの電界の
ドリフトにより拡散を加速されることになる。
As a result, the substrate is irradiated with energetic electrons, and by controlling this accelerating voltage, the energy possessed by the electrons is applied to the substrate lattice up to the desired diffusion depth, and the energy is reversed. Since the substrate side becomes the positive electrode, the boron acceptor ions localized in front of the substrate are accelerated to diffuse due to the drift of this electric field.

このように極正反転作用により拡散が容易とな
るため印加電圧も比較的低くてすむのでマスク材
および多層構造の絶縁膜にかかるストレスも低減
できる利点がある。また、この場合電子照射によ
るアニール作用も考えられる。
Since diffusion is facilitated by the positive polarity reversal effect, the applied voltage can be relatively low, which has the advantage of reducing stress on the mask material and the insulating film of the multilayer structure. Further, in this case, an annealing effect due to electron irradiation is also considered.

この電子線による格子に対するエネルギの付与
は、基板物質の電気的および光学的特性などによ
つて変らず、また干渉効果もないので特定の場所
だけにエネルギーを放出されることもなく平面的
に見た場合のドープの均一性が得られるものであ
る。
The energy imparted to the lattice by the electron beam does not change depending on the electrical and optical properties of the substrate material, and there is no interference effect, so the energy is not emitted only in a specific place and can be seen from a two-dimensional view. The uniformity of the doping can be obtained when

また活性化が入射電子のエネルギーにより行な
われるため、準安定な固溶限以上の高濃度不純物
の凍結現象が起こり再分布もなく表面高濃度が保
持される。
Furthermore, since activation is performed by the energy of incident electrons, a freezing phenomenon of high concentration impurities exceeding the metastable solid solubility limit occurs, and a high surface concentration is maintained without redistribution.

なお入射電子のSi原子に対する臨界変位エネル
ギは125kevと高いので、この発明の方法の如く
低エネルギーの場合はこれによる格子欠かんは全
く発生しないと見ることができる。
Note that the critical displacement energy of incident electrons for Si atoms is as high as 125 keV, so when the energy is low as in the method of this invention, it can be seen that no lattice defects will occur due to this.

次に一般のプラズマプロセスにもいえることで
あるが、器壁、電極などによる貴金属汚染の問題
である。特に、この発明の方法のようにプラズマ
を用いたドーピング方式では、深い不純物準位を
形成するFe、Niなどは格子間機構で拡散するた
め、ボロン等に比べ拡散係数は著しく大きく無視
できない問題である。
Next, as is the case with general plasma processes, there is the problem of precious metal contamination from vessel walls, electrodes, etc. In particular, in doping methods using plasma such as the method of this invention, Fe, Ni, etc., which form deep impurity levels, diffuse through an interstitial mechanism, so the diffusion coefficient is significantly larger than that of boron, etc., and is a problem that cannot be ignored. be.

例えばSUS(ステンレス スチール)電極を用
いた場合、基板にはFe、Cr、Niによる0.35ev〜
0.55evのテープレベル準位が見られライフタイム
も減少する。
For example, when using SUS (stainless steel) electrodes, the substrate contains Fe, Cr, and Ni of 0.35ev~
A tape level level of 0.55ev is seen and the lifetime is also reduced.

この現象は、SUS陽極、基板陰極の場合にも
見られるが、特に極性転換した場合のSUS陰極
における金属飛沫作用が大きく利いている。
This phenomenon is also seen in the case of SUS anodes and substrate cathodes, but the metal splash effect on the SUS cathode is particularly effective when the polarity is reversed.

このため、この発明の実施例においては汚染防
止上対向電極3にドープしようとする元素と同じ
元素を高濃度に含んだ単結晶のシリコン電極を用
いることによつてこの問題を解決している。
Therefore, in the embodiment of the present invention, this problem is solved by using a single crystal silicon electrode containing a high concentration of the same element as the element to be doped into the counter electrode 3 to prevent contamination.

なお、この発明は上記の実施例に限定されるも
のではなく要旨を変更しない範囲において異なる
構成をとることができる。
It should be noted that the present invention is not limited to the above-described embodiments, and may have different configurations without changing the gist.

〔発明の効果〕〔Effect of the invention〕

以上述べたようにこの発明によれば、不純物の
浅い領域を作ることが容易であり比較的短時間に
行なうことができしかも高温の熱処理を必要とし
ない多量生産に適した半導体基板に対する不純物
のドーピング方法を提供することができる。
As described above, according to the present invention, it is easy to create a shallow region of impurities, it can be done in a relatively short time, and it does not require high-temperature heat treatment, making it suitable for mass production. method can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例の概略的構成図、
第2図は同実施例の表面からの深さに対する拡散
層の拡がり抵抗の特性を示す曲線図、第3図は同
実施例においてステージと対向電極の間に印加す
る電圧を示す波形図である。 1……プラズマ発生装置、2……ステージ、3
……対向電極、4……ヒータ、5……N型単結晶
基板、6……直流電源、7……極性転換器。
FIG. 1 is a schematic diagram of an embodiment of the present invention;
FIG. 2 is a curve diagram showing the characteristics of the spreading resistance of the diffusion layer with respect to the depth from the surface in the same example, and FIG. 3 is a waveform diagram showing the voltage applied between the stage and the counter electrode in the same example. . 1... Plasma generator, 2... Stage, 3
...Counter electrode, 4...Heater, 5...N-type single crystal substrate, 6...DC power supply, 7...Polarity changer.

Claims (1)

【特許請求の範囲】[Claims] 1 プラズマ発生装置の一方電極を形成するステ
ージ上に半導体基板を配置するとともにドープす
る元素を含むシリコン電極を対向電極として設
け、前記ステージと対向電極の間にステージ側を
負とする直流電圧を第1の所定時間印加してプロ
ズマ放電を行い、その後前記直流電圧を転極して
第2の所定時間の間前記基板内に、発生したドー
プ元素イオンの注入を行なうことを特徴とする半
導体用基板に対する不純物のドーピング方法。
1. A semiconductor substrate is placed on a stage that forms one electrode of a plasma generator, and a silicon electrode containing an element to be doped is provided as a counter electrode, and a direct current voltage with the stage side being negative is applied between the stage and the counter electrode. A substrate for a semiconductor, characterized in that the DC voltage is applied for a predetermined period of time to cause plasma discharge, and then the polarity of the DC voltage is reversed to implant generated dope element ions into the substrate for a second predetermined period of time. impurity doping method for.
JP12317386A 1986-05-27 1986-05-27 Impurity doping method for semiconductor substrate Granted JPS62279626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12317386A JPS62279626A (en) 1986-05-27 1986-05-27 Impurity doping method for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12317386A JPS62279626A (en) 1986-05-27 1986-05-27 Impurity doping method for semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS62279626A JPS62279626A (en) 1987-12-04
JPH0516656B2 true JPH0516656B2 (en) 1993-03-05

Family

ID=14853991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12317386A Granted JPS62279626A (en) 1986-05-27 1986-05-27 Impurity doping method for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS62279626A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0220018A (en) * 1988-07-08 1990-01-23 M Setetsuku Kk Electrode structure for plasma processor
JP6143440B2 (en) * 2012-11-22 2017-06-07 住重試験検査株式会社 Semiconductor device manufacturing method and substrate processing system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5328378A (en) * 1976-08-27 1978-03-16 Handotai Kenkyu Shinkokai Method of plasma etching
JPS554937A (en) * 1978-06-27 1980-01-14 Fujitsu Ltd Dry etching method
JPS56138921A (en) * 1980-03-31 1981-10-29 Fujitsu Ltd Method of formation for impurity introduction layer
JPS57106120A (en) * 1980-12-24 1982-07-01 Fujitsu Ltd Manufacture of semiconductor device
DE3118785A1 (en) * 1981-05-12 1982-12-02 Siemens AG, 1000 Berlin und 8000 München METHOD AND DEVICE FOR DOPING SEMICONDUCTOR MATERIAL
JPS57202726A (en) * 1981-06-05 1982-12-11 Mitsubishi Electric Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS62279626A (en) 1987-12-04

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