JPH0516667B2 - - Google Patents
Info
- Publication number
- JPH0516667B2 JPH0516667B2 JP60273369A JP27336985A JPH0516667B2 JP H0516667 B2 JPH0516667 B2 JP H0516667B2 JP 60273369 A JP60273369 A JP 60273369A JP 27336985 A JP27336985 A JP 27336985A JP H0516667 B2 JPH0516667 B2 JP H0516667B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- wiring board
- silicone resin
- leads
- filled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
- H10W76/42—Fillings
- H10W76/47—Solid or gel fillings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/654—Top-view layouts
- H10W70/656—Fan-in layouts
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子装置等に使用されるパツケージに
係わり、特に信号等を授受する入出力ピンを配線
基板に設け電子部品を実装してシリコンコーテイ
ングされたパツケージに関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to packages used in electronic devices, etc., and in particular, the present invention relates to packages used in electronic devices, etc., and in particular, the invention relates to packages used for electronic devices, etc., and in particular, by providing input/output pins for transmitting and receiving signals, etc. on a wiring board, mounting electronic components, and applying silicon coating. This is related to the package that was created.
従来、この種のパツケージは、第２図に示すよ
うに内部に複数層の導体配線層１を有し裏面に入
出力ピン２が設けられた配線基板３上に電子部品
４が実装され、リード５を介して前記導体配線層
１に接続されて電子部品４の周辺部はシリコン樹
脂６により被覆されている（例えば、Brad
Older and Richard A.、“Non−hermetic
packaging techniques for hybrids”、
Electronic Packaging and Production、June、
1979、P137〜139）。
Conventionally, as shown in FIG. 2, in this type of package, electronic components 4 are mounted on a wiring board 3 that has a plurality of conductor wiring layers 1 inside and has input/output pins 2 on the back side. The electronic component 4 is connected to the conductor wiring layer 1 through the conductor wiring layer 1 and its peripheral portion is covered with a silicone resin 6 (for example, Brad
Older and Richard A., “Non-hermetic
packaging techniques for hybrids”
Electronic Packaging and Production, June;
1979, P137-139).
上述した従来のパツケージでは、電子部品４の
交換時に、リード５と電子部品４と配線基板３と
で囲まれた領域に充填されたシリコン樹脂６の除
去が困難であり、特にリード５が微細化したり、
電子部品４がフエイスダウン実装となると、リー
ド５と電子部品４の配線基板３とで囲まれた領域
が狭くなり、シリコン樹脂６が除去できず、また
シリコン樹脂を溶解させる有機溶剤への浸漬時に
シリコン樹脂６の膨張でリード５が切断された
り、配線基板１からリード５が剥れたりするなど
の問題があつた。
In the conventional package described above, when replacing the electronic component 4, it is difficult to remove the silicone resin 6 filled in the area surrounded by the lead 5, the electronic component 4, and the wiring board 3, and especially when the lead 5 is miniaturized. Or,
When the electronic component 4 is mounted face-down, the area surrounded by the leads 5 and the wiring board 3 of the electronic component 4 becomes narrow, making it impossible to remove the silicone resin 6, and when immersing the silicone resin in an organic solvent that dissolves the silicone resin. There were problems such as the leads 5 being cut due to the expansion of the silicone resin 6 or the leads 5 being peeled off from the wiring board 1.
本発明によるパツケージは、配線基板上に実装
された電子部品とこの電子部品のリードとで囲ま
れた領域に紫外線照射により未硬化ないし半硬化
する第１の紫外線硬化形シリコン樹脂を充填し、
この第１の紫外線硬化形シリコン樹脂上に弾性力
のあるゲル状に硬化する第２の紫外線硬化形シリ
コン樹脂を充填するものである。
In the package according to the present invention, an area surrounded by an electronic component mounted on a wiring board and the leads of the electronic component is filled with a first UV-curable silicone resin that is uncured or semi-cured by UV irradiation.
This first ultraviolet curable silicone resin is filled with a second ultraviolet curable silicone resin that hardens into an elastic gel-like state.
第１のシリコン樹脂が硬化されていないので、
有機溶剤に溶解される。
Since the first silicone resin is not cured,
Dissolved in organic solvents.
〔実施例〕
次に、本発明について図面を参照して説明す
る。[Example] Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す縦断面図であ
り、前述の図と同一部分には同一符号を付してあ
る。同図において、配線基板１の表面にはリード
用パツド８が、その裏面には入出力ピン２がそれ
ぞれ設けられており、このリード用パツド８と入
出力ピン２とは配線基板３内で導体配線層１によ
り電気的に接続されている。また、この配線基板
１上には図示しないが例えばエポキシ樹脂などの
接着剤によりスペーサ９が固定配置され、さらに
このスペーサ９上には電子部品４がフエースダウ
ンで接着配置され、電子部品４のリード５が配線
基板３上のリード用パツド８に電気的に接続され
ている。また、この配線基板３上にはその周辺部
に枠体１０が図示しないが接着剤により取付固定
されている。そして、この枠体１０内には紫外線
硬化形のシリコン樹脂が充填され、上方側から紫
外線を照射することにより、電子部品４および電
子部品４のリード５の影になる部分が未硬化ない
しは半硬化状態となる第１のシリコン樹脂１１が
形成され、その周辺部および上部には弾力性のあ
るゲル状に硬化する第２のシリコン樹脂１２が形
成されている。また、枠体１０の開口部には電子
部品４と図示しない熱伝導性コンパウンドで接触
してキヤツプ１３が図示しないが接着剤により取
付固定されている。このキヤツプ１３は、ヒート
シンク等の放熱部品を接着、半田付けまたは熱伝
導性コンパウンドによる接続等により、電子部品
４で発生する熱を外部に導く機能を有しており、
空冷するためのヒートシンクまたは水冷するため
の冷却板と一体化しても良い。また、スペーサ９
は、絶縁性であれば配線基板３と電子部品４との
接着剤も絶縁性であることが望ましいが、電子部
品４のスペーサ９との接する面が絶縁されていた
り、配線基板３のスペーサ９との接する面が絶縁
されていれば、スペーサ９および接着剤は導電性
でも良い。また、配線基板３の枠体１０との接す
る部分が絶縁されていれば、枠体１０および接着
剤は導電性でも良い。さらに配線基板３の枠体１
０と接する部分が絶縁され、かつその上に専用の
金属層を設ければ、金属の場合の枠体１０と配線
基板３とを半田付けできる。 FIG. 1 is a longitudinal sectional view showing one embodiment of the present invention, and the same parts as in the previous figures are given the same reference numerals. In the figure, a lead pad 8 is provided on the front surface of the wiring board 1, and an input/output pin 2 is provided on the back surface of the wiring board 1. They are electrically connected by a wiring layer 1. Further, although not shown, a spacer 9 is fixedly arranged on the wiring board 1 with an adhesive such as epoxy resin, and furthermore, an electronic component 4 is adhesively arranged face-down on the spacer 9, and the leads of the electronic component 4 are arranged face-down. 5 is electrically connected to a lead pad 8 on the wiring board 3. Further, a frame 10 is attached and fixed to the peripheral portion of the wiring board 3 using an adhesive (not shown). The frame 10 is filled with an ultraviolet curing type silicone resin, and by irradiating ultraviolet rays from above, the electronic component 4 and the portions of the electronic component 4 that are in the shadow of the leads 5 are left uncured or semi-cured. A first silicone resin 11 is formed, and a second silicone resin 12 that hardens into an elastic gel-like state is formed around and above the first silicone resin 11. Further, a cap 13 is attached and fixed to the opening of the frame 10 by an adhesive (not shown) in contact with the electronic component 4 using a thermally conductive compound (not shown). This cap 13 has the function of guiding heat generated in the electronic component 4 to the outside by bonding, soldering, or connecting a heat sink or other heat dissipating component with a thermally conductive compound.
It may be integrated with a heat sink for air cooling or a cooling plate for water cooling. Also, spacer 9
If the adhesive between the wiring board 3 and the electronic component 4 is insulating, it is desirable that the adhesive between the wiring board 3 and the electronic component 4 is also insulating. The spacer 9 and the adhesive may be conductive as long as the surfaces in contact with the spacer 9 are insulated. Furthermore, the frame 10 and the adhesive may be conductive as long as the portion of the wiring board 3 that contacts the frame 10 is insulated. Furthermore, the frame 1 of the wiring board 3
If the portion in contact with 0 is insulated and a dedicated metal layer is provided thereon, the frame 10 made of metal and the wiring board 3 can be soldered.
このような構成によれば、電子部品４等を交換
する場合、まず第２のシリコン樹脂１２を剥が
し、次に第１のシリコン樹脂１１を有機溶剤に浸
漬することにより、溶解され、容易に除去するこ
とができる。 According to such a configuration, when replacing the electronic component 4, etc., the second silicone resin 12 is first peeled off, and then the first silicone resin 11 is immersed in an organic solvent, so that it is dissolved and easily removed. can do.
以上説明したように本発明によれば、配線基板
上に実装された電子部品とこの電子部品のリード
とで囲まれた領域に硬化しない第１の紫外線硬化
形シリコン樹脂を充填したことにより、電子部品
の交換時に電子部品のリードの外側の第２の紫外
線硬化形シリコン樹脂のみを剥離し、第１のシリ
コン樹脂を有機溶剤に浸漬することにより、溶解
され、容易に除去されるので、電子部品のリード
の切断および配線基板からの剥れ等を確実に防止
することができるという極めて優れた硬化が得ら
れる。
As explained above, according to the present invention, the area surrounded by the electronic component mounted on the wiring board and the leads of the electronic component is filled with the first ultraviolet curable silicone resin that does not harden. When replacing parts, only the second UV-curable silicone resin on the outside of the leads of the electronic component is peeled off, and the first silicone resin is immersed in an organic solvent, which dissolves and easily removes the electronic component. This results in extremely excellent curing that can reliably prevent lead breakage and peeling from the wiring board.
第１図は本発明によるパツケージの一実施例を
示す縦断面図、第２図は従来のパツケージを示す
縦断面図である。
１……導体配線層、２……入出力ピン、３……
配線基板、４……電子部品、５……リード、８…
…リード用パツド、９……スペーサ、１０……枠
体、１１……第１のシリコン樹脂、１２……第２
のシリコン樹脂、１３……キヤツプ。
FIG. 1 is a longitudinal sectional view showing an embodiment of a package according to the present invention, and FIG. 2 is a longitudinal sectional view showing a conventional package. 1... Conductor wiring layer, 2... Input/output pin, 3...
Wiring board, 4...Electronic component, 5...Lead, 8...
... Lead pad, 9 ... Spacer, 10 ... Frame, 11 ... First silicone resin, 12 ... Second
silicone resin, 13...cap.
Claims (1)
と、前記配線基板上に取付固定された枠体と、前
記電子部品と電子部品のリードと配線基板とで囲
まれる領域に充填された硬化しない第１の紫外線
硬化形シリコン樹脂と、前記電子部品の周辺部お
よび上部に充填された弾力性のあるゲル状に硬化
する第２の紫外線硬化形シリコン樹脂とを具備す
ることを特徴としたパツケージ。1. A first non-hardening agent filled in an area surrounded by a wiring board on which an electronic component having a lead is mounted, a frame mounted and fixed on the wiring board, the electronic component, the leads of the electronic component, and the wiring board. 1. A package comprising: an ultraviolet curable silicone resin; and a second ultraviolet curable silicone resin that cures into an elastic gel-like form and is filled in the periphery and upper part of the electronic component.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60273369A JPS62133742A (en) | 1985-12-06 | 1985-12-06 | Package |
| US06/900,532 US4709301A (en) | 1985-09-05 | 1986-08-26 | Package |
| EP86112244A EP0214621B1 (en) | 1985-09-05 | 1986-09-04 | A package comprising a substrate and at least one electronic component |
| DE86112244T DE3688164T2 (en) | 1985-09-05 | 1986-09-04 | Pack with a substrate and at least one electronic component. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60273369A JPS62133742A (en) | 1985-12-06 | 1985-12-06 | Package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62133742A JPS62133742A (en) | 1987-06-16 |
| JPH0516667B2 true JPH0516667B2 (en) | 1993-03-05 |
Family
ID=17526940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60273369A Granted JPS62133742A (en) | 1985-09-05 | 1985-12-06 | Package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62133742A (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59171343U (en) * | 1983-04-28 | 1984-11-16 | 株式会社デンソー | Hybrid integrated circuit device |
| JPS60116151A (en) * | 1983-11-28 | 1985-06-22 | Matsushita Electric Works Ltd | Sealing method of electronic parts |
| JPS6120771U (en) * | 1984-07-09 | 1986-02-06 | 日本フエラス工業株式会社 | Installation equipment for sash frame |
-
1985
- 1985-12-06 JP JP60273369A patent/JPS62133742A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62133742A (en) | 1987-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100694739B1 (en) | Ball grid array package with multiple power / ground planes | |
| EP0421005B1 (en) | Process of assembling an electronic package | |
| GB2286084A (en) | Electronic package with thermally conductive support | |
| US4709301A (en) | Package | |
| JP2004158753A (en) | Lead frame material and its manufacturing method, and semiconductor device and its manufacturing method | |
| JP3251323B2 (en) | Electronic circuit device | |
| JP3542297B2 (en) | Semiconductor device package and method of manufacturing the same | |
| JP3239640B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JPH0521342B2 (en) | ||
| JPH0516667B2 (en) | ||
| KR20040075683A (en) | Power semiconductor mudule package and method for fabricating the same | |
| JPS58122753A (en) | High density chip carrier | |
| KR100319400B1 (en) | Semiconductor Package and Manufacturing Method | |
| KR100197876B1 (en) | Semiconductor package and method of manufacturing the same | |
| JPS6239036A (en) | Hybrid ic | |
| JPS63244631A (en) | Manufacture of hybrid integrated circuit device | |
| JPH11233673A (en) | Semiconductor device, method of manufacturing the same, and electronic device | |
| KR100520443B1 (en) | Chip scale package and its manufacturing method | |
| JP2541494B2 (en) | Semiconductor device | |
| KR100406499B1 (en) | equipment for molding of semiconductor package and molding method using it | |
| KR19980068016A (en) | Ball Grid Array (BGA) Semiconductor Package Using Flexible Circuit Board and Manufacturing Method Thereof | |
| KR100320729B1 (en) | Semiconductor chip module and method for manufacturing the same | |
| KR100419950B1 (en) | manufacturing method of ball grid array semiconductor package using a flexible circuit board | |
| JP2532543B2 (en) | Semiconductor device | |
| JP2523641B2 (en) | Semiconductor device |