JPH0516796B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a pixel clock extraction device for a video signal, and more particularly to a pixel clock extraction device for a video signal suitable for the video signal format of an electronic still camera system.

Background technology As is well known, in electronic still camera systems,
The video signal is FM modulated and recorded on a magnetic disk. In hard copy forming devices that reproduce video signals recorded on such magnetic disks and record them as visible images on video recording media such as photographic paper, digital image processing is used to obtain clear reproduced images. requires a high-precision pixel clock.

However, when reproducing video signals from a magnetic disk, jitter in the reproducing mechanism is unavoidable. Therefore, in order to form a high-quality reproduced image even when such jitter occurs, it is required that the pixel clock used for the reproduction operation itself be synchronized with such jitter.

For this purpose, in devices that use conventional video signals in the NTSC standard color television format, a clock is created from a horizontal synchronization signal separated by the video signal, and this is synchronized in phase with the color burst signal of the same video signal. In comparison, there was one that formed a pixel clock synchronized with the horizontal synchronization signal and color burst. For example, in one method, a clock with a frequency 12 times the subcarrier that follows the horizontal synchronization signal of the video signal input in NTSC format is created, and then when this clock is stepped down to 1/3, the clock is The color burst signal is phase-compared with a frequency signal obtained by downgrading the same clock to 1/12, and the phase of the 1/3 down-down clock is modulated with a voltage corresponding to the error. A pixel clock synchronized with the burst is obtained.

However, since the video signal of an electronic still camera does not have such a color burst signal, this
NTSC system circuits cannot be applied.

OBJECTS In view of these demands, it is an object of the present invention to provide a pixel clock extraction device for a video signal that can obtain a highly accurate pixel clock from a video signal of an electronic still camera system.

DISCLOSURE OF THE INVENTION According to the present invention, a sync chip detection means receives a video signal in which at least a luminance signal is frequency modulated, demodulates the video signal and detects the timing of a sync chip portion of the luminance signal; A pixel clock extraction device for a video signal is provided, which includes phase locked loop means for extracting a frequency signal of a sync chip portion from a video signal at a timing detected by the sync chip detection means and outputting a pixel clock locked to this frequency signal. Ru.

DESCRIPTION OF EMBODIMENTS Next, embodiments of a pixel clock extraction device for a video signal according to the present invention will be described in detail with reference to the accompanying drawings.

The device of this embodiment has a signal input terminal 10 into which an FM modulated video signal is input, and this is connected to an amplifier (AMP) 12 and an FM demodulator 14. In this embodiment, the video signal input to the terminal 10 is FM in the frequency band shown in FIG.
A modulated color video signal format is advantageously applied. In this video signal standard for electronic still cameras, a chroma signal occupies a band of 2.5 MHz or less, and includes color difference signals RY and BY. Also,
The brightness signal occupies a band of 2.5MHz or more, and is specified to be modulated with a SYNC TIP level of 6MHz and a white level of 7.5MHz.

The output 16 of the amplifier 12 is connected to one input of the phase comparator 18, and the output 19 of the phase comparator 18
is a loop filter 20, a sample/hold circuit (S/H) 22, a voltage controlled oscillator (VCO) 2
4 and a loop counter 26 to form a phase-locked loop (PLL), which is fed back to the other input 28 of the comparator 18. This PLL loop is
For example, a phase-locked loop used in an NTSC burst control oscillation circuit is advantageously applied.

The loop filter 20 is a reduction filter,
The output of the loop counter 26 constitutes an integrator that defines the responsiveness of the system so as to lock this phase-locked loop within the sync chip period T2 (FIG. 3). More specifically, as shown in FIG.
The filter characteristics that define the response are designed according to the number of phase comparisons performed by the phase comparator 18 during the sync chip period T2, the magnitude and period of time-base fluctuations (jitter) of the input FM modulation signal 10, and other conditions. Ru.

In this embodiment, the voltage controlled oscillator 24 is a variable frequency oscillator that generates at an output 46 a frequency signal based on a frequency twice the sync chip frequency. The counter 26 is a counter that steps down the frequency signal of the output 46 of the voltage controlled oscillator 24 by half.

The FM demodulator 14 is a demodulation circuit that demodulates the FM modulated video signal of the input 10 and outputs a video signal including a color difference signal, a luminance signal, and a synchronization signal to the output 30. The output 30 includes an amplifier 32, a clamp circuit (CLAMP) 34, a sample and hold circuit 36,
and analog/digital conversion circuit (A/D)
38 to a digital image data output 40. The clock inputs of the sample and hold circuit 36 and the analog-to-digital conversion circuit 38 are supplied with the pixel clock PC from the output 46 of the voltage controlled oscillator 24.

The video signal (FIG. 3A) at the output 30 of the FM demodulator 14 is amplified by the amplifier 32, and the pedestal level of the video signal is clamped by the clamp circuit 34. The clamped video signal still has an analog waveform, which is sampled by the clock PC in the sample and hold circuit 36 and converted to corresponding digital image data by the analog-to-digital converter 38. .

The output 33 of the amplifier 32 is also connected to the gate input 44 of the sample and hold circuit 22 through a sync separation circuit 42 . Synchronous separation circuit 4
Reference numeral 2 denotes a circuit that separates the horizontal synchronizing signal from the video signal of the input 33, detects the sync chip included therein, and gates the sample/hold circuit 22 at a timing synchronized with this.

For example, an FM modulated video signal read from a magnetic disk for an electronic still camera and supplied to the terminal 10 is demodulated by the demodulator 14, and is then demodulated by a clamp circuit 34, a sample and hold circuit 36, and an analog/digital converter 38. The digital image data is outputted from the output 40 as digital image data.
This is later used for digital image processing and reproduction as a hard copy on an image recording medium such as photographic paper.

The sample/hold circuit 22 is gated in synchronization with the sync chip detection signal on the signal line 44 which is separated from the demodulated video signal by the sync separation circuit 42 and detected. As a result, the sample-and-hold circuit 22 cuts out the sync chip portion of the FM modulation signal input to the input 10 and outputs an output voltage corresponding to that frequency signal to the output 23, which means that the next sync chip is detected. In other words, it is maintained for one horizontal scanning (1H) period of the video signal.

In other words, during the sync chip period T2, the sample/hold circuit 22 outputs the signal output from the loop filter 20 as it is to the input 23 of the voltage controlled oscillator 24, and at the end of the sync chip period T2, for example at time t1 in FIG. The level of the output signal of the loop filter 20 is held and thereafter maintained until the arrival of the next sync chip period T2.
Therefore, the output 2 of the sample-and-hold circuit 22
The voltage No. 3 has a level corresponding to the sync chip frequency of around 6MHz.

Of course, since the FM modulated video signal supplied to the input terminal 10 usually contains jitter within an acceptable range, the voltage at the output 23 may also vary accordingly.
Therefore, the oscillation frequency of the voltage controlled oscillator 24 is
A value related to the FM signal frequency of the sync chip portion, in this embodiment, is fixed at a value of around 12 MHz over the next effective video period T1. In this way, the oscillation frequency of the voltage controlled oscillator 24 can vary every 1H period.

This frequency output of the voltage controlled oscillator 24 is stepped down by 1/2 in the loop counter 26 to obtain a frequency of around 6MHz, and this signal is used as the FM modulation signal and the phase comparator 18.
By circulating through this phase-locked loop, the output 4 of the voltage controlled oscillator 24 is
The clock PC 6 locks to the sync chip frequency of the video signal. As shown in FIG. 3E, in this embodiment, the phase comparator 18 performs phase comparison at the zero crossing point of the output 28 of the loop counter 26 of the same D.

In this way, the clock PC that drives the sample-and-hold circuit 36 and the analog-to-digital converter 38 receives the signal from the input terminal 1, which may contain jitter.
It sufficiently follows the sync chip frequency signal of the FM modulation signal of 0 and has high accuracy. Since the sync chip period T2 includes several tens of periods of the sync chip frequency signal, the phase comparator 18 can perform phase comparison about 20 to 30 times during one horizontal synchronizing signal period. This responsivity of the phase-locked loop is defined by the loop filter 20.

By the way, another method for obtaining a pixel clock from an input video signal is to extract a horizontal synchronization signal from the video signal, compare the phase of this with a horizontal synchronization signal created from the clock, and obtain a pixel clock that is locked to the horizontal synchronization signal. Other methods are also possible.

Comparing this method with this embodiment, since this method uses a horizontal synchronization signal, in order to take advantage of the long period, the PLL loop counter must have a large frequency division ratio of, for example, 1/800 or 1/900. It is necessary to have However, in this embodiment, the loop counter 26 with a small frequency division ratio is sufficient as described above. Furthermore, in this embodiment, since the number of phase comparisons during the 1H period is large as described above, the pixel clock PC can be locked with high accuracy.
In the method that uses the horizontal synchronization signal mentioned above, various processing is required before extracting the horizontal synchronization signal from the FM modulated video signal, so errors are likely to be mixed into the horizontal synchronization signal due to these processes. However, in this embodiment, since the FM modulation signal can be used as is, the reliability of the signal supplied to the phase comparator 18 is high. Therefore, this embodiment has the feature that a highly accurate pixel clock can be extracted with a relatively simple device configuration.

Effects As described above, according to the present invention, a loop counter with a small frequency division ratio is used, the number of phase comparisons during 1H period is large, and a highly reliable signal can be used in the phase-locked loop. Therefore, a highly accurate pixel clock can be obtained with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a pixel clock extraction device for a video signal according to the present invention, and FIG.
FIG. 3 is a waveform diagram showing examples of signal waveforms appearing in each part of the device shown in FIG. 1. FIG. . Explanation of symbols of main parts, 14...FM demodulator,
18... Phase comparator, 20... Loop filter,
22...Sample/hold circuit, 24...Voltage controlled oscillator, 26...Loop counter, 42...
Synchronous separation circuit.

Claims (1)

[Scope of Claims] 1. sync chip detection means that receives a video signal in which at least a luminance signal is frequency modulated, demodulates the video signal, and detects the timing of a sync chip portion of the luminance signal; A pixel clock for a video signal, comprising phase locked loop means for extracting a frequency signal of the sync chip portion from the video signal at the timing detected by the sync chip detection means and outputting a pixel clock locked to the frequency signal. Extraction device. 2. The device according to claim 1, wherein the phase-locked loop means includes a phase-locked loop consisting of a phase comparator, a loop filter, a voltage controlled oscillator, and a loop counter, and one input of the phase comparator is The video signal is input, the pixel clock is output from the output of the voltage controlled oscillator, and between the loop filter and the voltage controlled oscillator,
The sync chip portion of the video signal is taken in through the loop filter at the timing detected by the sync chip detection means, and the control voltage related to the sync chip portion of the taken video signal is controlled until the next timing is detected by the sync chip detection means. A pixel clock extraction device characterized by being provided with a sample and hold circuit for feeding an oscillator.