JPH0517733B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic frequency control device for stabilizing frequencies in satellite communications and the like.

[Conventional technology]

In satellite communications, due to the nature of satellite repeaters,
A frequency offset occurs in the reception frequency on the ground, and the amount of offset is about ±40kHz. Therefore, it is necessary to correct this offset at the ground receiver. A conventional offset correction circuit that corrects such an offset is composed of a frequency conversion circuit, a frequency discrimination circuit, a VCO, etc., and adjusts the oscillation frequency of the first local oscillation circuit of the receiver according to the offset amount of the reception frequency. It is automatically changed and corrected.

In order to stabilize the transmission frequency, conventionally, a crystal oscillator equipped with a constant temperature oven is generally used.

[Problems to be Solved by the Invention] As described above, the conventional offset correction circuit as described above is constructed entirely of analog circuits, has a large number of parts, and lacks reliability.

Furthermore, the constant temperature bath used in the transmitter has problems such as high manufacturing cost, large volume, and large power consumption.

This invention has been made to solve such problems, and provides an automatic frequency control device that can easily correct the offset of the reception frequency and stabilize the transmission frequency without using a thermostatic oven. It is an object.

[Means to solve the problem]

The automatic frequency control device according to the present invention takes advantage of the fact that the frequency f _k of the clock signal is accurately maintained when transmitting a digital signal, and uses the fact that the frequency f _k of the clock signal is accurately maintained to The multiples of f _k for each f _s are measured, and if these multiples deviate from the normal values stored in advance, the respective VCOs are feedback-controlled using the value of the deviation, and the first local oscillation circuit is Sweep the oscillation frequency over the entire receiving frequency range,
By passing the output of the first frequency conversion circuit of the receiving device through a narrowband bandpass filter, the receiving frequency is searched and frequency pull-in is ensured, and furthermore, the frequency of the receiving device and the frequency of the transmitting device are It was decided that they would be digitally controlled by the same CPU (central processing unit).

[Effect]

Since the frequency f _k of the clock pulse can be accurately reproduced, it becomes possible to easily control f _i and f _s to accurate frequencies.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a frequency conversion circuit, 2 is a first
VCO, 3 is a band pass filter (hereinafter abbreviated as BPF), 4 is a carrier detection circuit, 5 is a carrier regeneration circuit, 6 is a signal demodulation circuit, 7 is a clock regeneration circuit, 8 is a control CPU, 9 is a first Digital to analog converter (hereinafter abbreviated as D/A), 1
0 indicates the second D/A, 11 indicates the second VCO, and CD indicates the detection signal from the carrier detection circuit 4.

Assuming that the carrier frequency of the received PSK signal is f _r , its clock frequency is f _k , and the output frequency of VCO 2 is f _v , the intermediate frequency carrier f _i that is the output of the frequency conversion circuit 1 is, for example, f _i = f _r −f _v .

CPU8 sweeps the oscillation frequency f _v of VCO2 via D/A9, and BPF3 sweeps the center frequency f _i0
However, by sweeping f _v and therefore f _i , f _i
When =f _i0 , f _i passes through BPF3. The carrier detection circuit 4 detects this and outputs a detection signal CD to the CPU 8. In CPU8, this detection signal
Stop VCO2 sweep with CD.

And carrier regeneration circuit 5 from the output of BPF3
An intermediate frequency carrier is regenerated, and a signal is demodulated from the output of the BPF 3 by the signal demodulation circuit 6 using the regenerated carrier. A clock pulse is then extracted from the demodulated signal by a clock recovery circuit 7.

FIG. 2 is a block diagram illustrating the operation of the CPU 8 shown in FIG. 1, in which the same reference numerals as in _{FIG .}
83 is a memory for storing the value of f _i during one period of f _k
84 is a counter 83 that measures the wave number of
85 is a first subtraction circuit, and 86 is a selector.

While CD is below a predetermined value, the selector 81 gives the output of the sawtooth wave generating circuit 81 to the D/A 9, sweeps the oscillation frequency of the VCO 2, and f _i
When f _i0 approaches, the output of the BPF 3 increases, and therefore the CD from the carrier detection circuit 4 increases, and the selector 86 outputs the output from the subtraction circuit 85 to the D/A 9.
give to That is, the circuit of D/A9-VCO2-frequency conversion circuit 1-BPF3-carrier regeneration circuit 5-counter 83-latch 84-subtraction circuit 85-selector 86-D/A9 performs feedback control so that f _i =f _i0 . be done.

Further, 87 is a memory that stores the value of f _s0 /f _k (where f _s0 is the specified value of f _s ), 88 is a counter that measures the wave number of f _s during one cycle of f _k , and 89 is a counter that the counter 88 counts. Indicates a latch to latch the value at the end of the process. Then, in this circuit, feedback control is performed so that f _s =f _s0 by the same operation as in the case of f _i above.

As described above, the first local oscillation frequency of the receiving device and the reference frequency of the transmitting device can be simultaneously stabilized by the single CPU 8.

〔Effect of the invention〕

As explained above, the present invention has the effect of simultaneously stabilizing the first local oscillation frequency of the receiving device and the reference frequency of the transmitting device with a simple circuit, and realizing reliable frequency pull-in with less malfunction through digital control. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram explaining the operation of the CPU shown in FIG. 1. 1 is the frequency conversion circuit, 2 is the first VCO, 3 is the
BPF, 4 is a carrier detection circuit, 5 is a carrier regeneration circuit, 6 is a signal demodulation circuit, 7 is a clock regeneration circuit, 8 is a CPU, 9 is a first D/A, 10 is a second D/A
D/A, 11 is the second VCO. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In an automatic frequency control device used in a communication device that modulates and transmits a carrier wave using a digital signal capable of regenerating a clock frequency, the received frequency is converted to an intermediate frequency (this frequency is referred to as f _i ). a first voltage _- controlled oscillator (VCO) that supplies a local oscillation voltage to this frequency conversion circuit; A bandpass filter (BPF) having a frequency band, a carrier regeneration circuit that regenerates the intermediate frequency f _i that has passed through this BPF from the output of this BPF, and a signal that demodulates a signal from the output of this carrier regeneration circuit and the output of the BPF. A demodulation circuit, a clock regeneration circuit that extracts a clock pulse (this frequency is f _k ) from the output of this signal demodulation circuit, a carrier detection circuit that detects whether the output of the BPF is above a predetermined value, and used in a transmitter. Input each frequency of f _i , f _k , f _s to the second VCO that oscillates the reference frequency f _s , calculate the values of f _i /f _k and f _s /f _k , and calculate these values. memorize in advance
Difference between f _i0 /f _k and f _s0 /f _k (f _s0 is the specified value of f _s ) Δf _i
,
A CPU that calculates Δf _s ; when the output of the carrier detection circuit is below a predetermined value, a sawtooth wave voltage is sent from the CPU to the first VCO via the first digital-to-analog converter (D/A); In addition, when the output of the carrier detection circuit exceeds the predetermined value, the value of Δf _i is
input to the D/A, and the output of the above first
means for _feedback controlling the VCO;
An automatic frequency control device comprising means for feedback controlling a VCO.