JPH0518068B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pattern generator that generates a mixture of test patterns for logic ICs and memory ICs in real time.

[Background of the invention]

In recent years, logic ICs equipped with memory, such as one-chip microcomputers, have appeared, and a pattern generator that can generate both logic IC and memory IC patterns is needed as a test pattern generator. It's getting better. As such a pattern generator, one disclosed in Japanese Unexamined Patent Publication No. 52967/1983 is known. As shown in FIG. 1, this consists of a memory IC test pattern generator consisting of a sequence controller 9, an instruction memory 3, and an exerciser 5, and a logic system consisting of an address generator 8 and a pattern memory 12.
The output of the IC test pattern generator is switched and outputted by a multiplexer 13. That is, in the pattern generator for memory IC, an instruction is read from the address of the instruction memory 3 specified by the sequence controller 9, and according to the instruction, the exerciser 5 performs the memory test of the IC element under test. patterns (test data, memory addresses, control signals, etc.) are generated. On the other hand, the logic IC pattern generator reads out the address pattern input from the address generator 8 from the logic test pattern memory 12 and outputs it. In order to switch between the two patterns in a desired sequence, each pattern start signal and pattern end signal are transmitted between the sequence controller 9 of the memory IC test pattern generator and the address generator 8 of the logic IC test pattern generator. Make a delivery. By exchanging this signal, the generation of the two patterns is synchronized and the switching time is shortened. However, in such a pattern generator, the overall amount of hardware increases, and in order to generate one mixed test pattern, a sequence program loaded into the sequence controller 9 and a sequence program loaded into the address generator 8 are required. In addition, it is necessary to refer to each other's start and end signals in both programs, and there is a concern that it will take time and effort to create the program.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern generator for generating mixed test patterns that requires less hardware and allows easy creation of sequence programs.

[Summary of the invention]

The present invention focuses on the similar functions of an address generator for logic test patterns and a sequence controller for memory test patterns, and in order to realize these two functions with one address generator, as shown in FIG. One address generator 14 accesses both the pattern memory 18 for logic testing and the instruction memory 19 for memory testing, and the addresses output by the address generator 14 are directed to the pattern memory 18. or the instruction memory 19.
5, operation control circuits 16 and 17 for activating or inhibiting the operation of the exerciser or the like according to the output of the means 15, and a multiplexer 13 for switching the output pattern.

[Embodiments of the invention]

Examples will be described in detail below with reference to FIGS. 3 and 4. FIG. 3 is a block diagram showing one embodiment of the present invention, including one address generator 14 and a code register 15 (shown in FIG. a clock control circuit 16 that passes the clock to a test pattern generator designated by the code register 15;
17 (corresponding to the operation control circuit in FIG. 2), a logic test pattern generator 18, a memory test pattern generator 19, and a multiplexer 13 for selectively outputting test patterns.

A clock is given to address generator 14, code register 15, and clock control circuits 16 and 17, and the entire circuit operates based on this clock. The clock control circuit 16 makes the clock pass when code 3 is input, and the clock control circuit 17 makes the clock pass when code 0 is input.

FIG. 4 is an example of a time chart specifically showing the operation of the embodiment shown in FIG.
The operation of this embodiment will be explained using figures. In FIG. 4, the code register 15 takes in the code 3 given in advance from the address generator 14 by the first clock cycle, and at the same time, the address generator 14 outputs the address ABCD and the code 0. This address ABCD is given to the address register 21 and instruction memory 23. However, since the code register 15 outputs the fetched code 3 as a code for identifying the other party, when the second clock is input, the clock control circuit 16 detects this code 3 and passes the clock. Therefore, the address given to address register 21 by this clock
ABCD is taken into address register 21.
At the same time, the clock that has passed through the clock control circuit 16 also serves as a set signal for the switching flip-flop 28, so from the second clock, the output of this flip-flop 28 is also turned on, and the multiplexer 1
3 selects the pattern memory 22 output. Next, the address register 21 is the fetched address.
Since ABCD is given to the pattern memory 22, the pattern memory 22 gives the multiplexer 13 a test pattern 1010 corresponding to this address. Since the multiplexer 13 selects this A input side as described above, this test pattern 1010 is applied to the device under test. Also, by the second clock, the code register 15 takes in the code 0 given by the first cycle clock, and at this time, the address generator 14 takes in the code 0 given by the first cycle clock.
22 and code 3 are output. Of these, address 2222 is given to address register 21 and instruction memory 23. Of these, the instruction memory 23 outputs an operation code 000 and an operand 0101 corresponding to the output address 2222 of the address generator 14. The decoder 24 decodes that the operation code 000 is an LDR (load register), outputs an operand capture signal to the arithmetic unit 25, and outputs a data load enable signal to the register 26. Arithmetic unit 25 takes in operand 0101 and outputs it to register 26. When this operation is completed, the third clock is input, but since the code register 15 contains code 0 at this time, the clock control circuit 17 allows this clock to pass, and this is applied to the register 26, which registers the third clock. 26 takes in data 0101 and outputs it. Also, since the clock passed through the circuit 17 is applied as a reset signal to the switching flip-flop 28, the output Q of this flip-flop 28 becomes 0 and the B input side of the multiplexer 13 is selected. Therefore, test pattern 0101 set in register 26 is applied to the device under test through multiplexer 13. By repeating similar operations, a test pattern is applied to the device under test.

As described above, according to this embodiment, by providing one address generator 14, a code register 15 as a means for determining the other party which is a simple circuit, and clock control circuits 16 and 17 as operation control circuits. Since two pulses can be generated, the amount of hardware is small and only one sequence program needs to be created.

[Summary of the invention]

According to the present invention, it is possible to realize a pattern generator for generating mixed test patterns that requires a small amount of hardware and can easily create a sequence program.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional pattern generator.
FIG. 2 is a diagram showing an outline of the pattern generator of the present invention, FIG. 3 is a block diagram showing an embodiment of the invention, and FIG. 4 is an example of an operation time chart of the embodiment of FIG. 13... Multiplexer, 14... Address generator, 15... Code register, 16, 17...
Clock control circuit, 18... test pattern generator for logic IC, 19... test pattern generator for memory IC. 28...Switching flip-flop.

Claims (1)

[Claims] 1 Arithmetic pattern generating means for an arithmetic unit to arithmetic and output a digital pattern according to control data read out from a control storage device in accordance with a given address; A memory pattern generating means for reading and outputting, an address to the arithmetic pattern generating means and the memory pattern generating means in a desired order according to a given program, and a code indicating which of the above pattern generating means the address is addressed to. and an operation control means for starting the operation of one of the arithmetic pattern generation means or the storage pattern generation means and prohibiting the operation of the other by determining the code. A pattern generator featuring: