JPH0518128B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clock switching control system, and particularly to a clock switching control method in a system including multiple devices or units each operated by a clock whose cycle does not switch in conjunction with each other. Regarding control method.

[Conventional technology]

A clock margin test, along with a voltage margin test, is an extremely important test in evaluating the operating margin of an information processing device or the like that operates in synchronization with a clock. As is well known, the clock margin test examines the operating limits of the device by increasing or decreasing the clock cycle from the rated value, and measures against fluctuations in the clock cycle due to environmental changes such as temperature or aging. This is an attempt to evaluate the stability of motion.

On the other hand, devices with complex configurations (hereinafter referred to as systems), such as information processing devices, are often divided into several sub-devices or units to facilitate design and maintenance. In many cases, devices are realized as a system by exchanging data between these sub-devices or units in a timely manner, and each sub-device or unit generally does not switch its clock cycle in conjunction with each other. It operates in response to the clock.

In this type of conventional clock switching control method, when there is a request to switch the clock cycle, regardless of the execution status of the data transfer as described above, that is, regardless of whether data transfer is being performed or not. A forced clock cycle switching instruction is issued to the clock supply source.

[Problem that the invention seeks to solve]

When switching the clock to a clock with a different cycle, for example, as shown in FIG. 5A, if clock A is switched to clock B with double the cycle using switching signal P, the resulting clock C will have a difference depending on the switching timing. Eventually, “beards” appear, and
As shown in FIG. 5B, in a device that operates only with clock D or clock E, which has a clock cycle ratio of 4:3, when switching from clock D to clock E, the clock cycle differs from the above-determined clock cycle. may appear temporarily. In the conventional system, even when such "whiskers" or phase differences appear, data is exchanged and read, so system operation is not guaranteed by the "whiskers" and phase differences of clocks C and F. There is a problem in that there are cases where it is no longer possible to perform a correct clock margin test.

These problems are caused by “whiskers” in the clock supply circuit.
Although this can be solved by adding means to suppress the occurrence of this problem and to compensate for the disturbance in the phase relationship, this would require a large amount of hardware.

[Means for solving problems]

The method of the present invention is a method for controlling clock switching in a system including multiple devices each operated by a clock whose cycle does not switch in conjunction with each other. Monitoring means for monitoring the state of system operations that may be adversely affected by the phenomenon; deterrent means for checking that the above-mentioned operations are not taking place based on the results of this monitoring, and then suppressing these operations; The present invention is characterized by the provision of instruction means for instructing the clock cycle switching to the clock supply source when the above-mentioned operation is inhibited, and release means for canceling all inhibition after this instruction.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the invention, and FIG. 2 shows the hardware environment of the invention.

First, referring to FIG. 2, the hardware environment of this embodiment includes an operation panel 1, a processor 2,
It consists of a clock supply unit 3 and three information processing units 4, 5 and 6.

Information processing units 4 and 5 each receive clocks 34 and 3 from clock supply unit 3, respectively.
5, and the information processing unit 6 is operated by a clock from a built-in oscillator. In the process of this operation, data is exchanged between the information processing units 4 and 5 and between the information processing units 4 and 6 in a timely manner, but the former data exchange is performed by the hardware of the information processing unit 4. Furthermore, the latter data exchange is controlled to be started or stopped by the software of the processor 2, respectively.

The information processing unit 4 includes an information processing unit 5.
A communication display flag 41 that indicates whether data is being exchanged (logic "1") or not (logic "0") and the information processing unit 5. A communication inhibition flag 42 indicating inhibition of data exchange is provided, and each is set or reset by the core part of the information processing unit 4. Note that similar functions for data exchange between the information processing unit 4 and the information management unit 6 are incorporated into the program executed by the processor 2.

Next, the operation of the first embodiment shown in FIG. 1 will be explained.

FIG. 1 shows the information processing unit 4 in FIG.
This is a flowchart of the operation of the embodiment when performing a clock margin test, and such functions are realized by a program executed by the processor 2.

When the operation panel 1 instructs the processor 2 to change the cycle of the clock 34, the operation shown in FIG. 1 starts. First, processor 2
reads the communication display flag 41 and simultaneously sets the communication inhibition flag 42 to logic "1" (step in FIG. 1). As a result of this, any requests for data exchange with the information processing unit 5 will be suppressed from now on.

If the communication display flag 41 read in step is logic "1" and communication is in progress (step), it becomes logic "0" (that is, data exchange is completed).
Then, if the communication display flag 41 read in step is logic "0" (step), the process immediately moves to step.

In the step, it is checked whether data is being exchanged with the information processing unit 6 in the program executed by the processor 2, and the same measures as in the step are taken to determine whether or not data is being exchanged with the information processing unit 6. (step).

In this way, the information processing unit 4 is connected to the information processing unit 5, and the information processing unit 4
After inhibiting the exchange of data with the information processing unit 6, the processor 2 instructs the clock supply unit 3 to switch the cycle of the clock 34 (step), and then sets the communication inhibition flag 4.
2 to logic "0" to cancel the inhibition of data exchange with the information unit 5, and also cancel the inhibition of data exchange with the information processing unit 6 performed by the program in step (step). .

As explained above, the first embodiment is realized by a program executed by the processor 2, but
It is also possible to implement a similar function using hardware and eliminate the need for the processor 2. FIG. 3 shows a block diagram of such hardware as a second embodiment of the invention.

Referring to FIG. 3, this embodiment is a differential circuit DIF
and two flip-flops FF1 and FF2
, 3-input AND gate AD1, and latch circuit
LAT, selector SEL, and two inverter IVs
1 and IV2.

A communication display signal 40 is input to the inverter IV1, and this communication display signal 40 is a logic "1" when the information processing unit 4 is exchanging data with the information processing unit 5 or 6, and a logic "0" otherwise. “It’s getting better.

FIG. 4 is a time chart showing the operation of this embodiment.
becomes logic "1" (timing T ₀ ), the clock 100 is switched to the clock 200 with a different period, and the clock switching signal 10 becomes logic "1".
The diagram shows important waveforms when switching from clock 200 to clock 100 when the clock becomes logic "0" (timing T _s ).

At timing T ₀ , clock switching signal 1
The rising edge of 0 is differentiated by the differentiating circuit DIF into a differential wave 20, which is used to set the flip-flop FF1. Output 30 of flip-flop FF1 (timing T ₁ )
is inverted in phase by inverter IV2 and serves to suppress data exchange requests.

Now, if the communication display signal 40 is logic "1", the inverter IV1 acts so as not to satisfy the AND condition in the AND gate AD1, so the output 30 of the flip-flop FF1 is
Since it cannot be used to set FF2 and therefore no enable signal 60 to latch circuit LAT is generated, selector SEL continues to select clock 100 and the clock does not switch.

When the communication display signal 40 becomes logic "0" (timing T ₂ ), the AND condition is satisfied in the AND gate AD1, so the AND gate AD1 accepts the output 30 of the flip-flop FF1, and outputs the output 50 of the AND gate AD1 (timing T _{2 )} . ) is used to set flip-flop FF2. The positive output 60 (timing T ₃ ) of flip-flop FF2 is routed to the reset terminal of flip-flop FF2 to reset flip-flop FF2 with a delay of one clock, and this result generates the enable signal 60 for one clock (timing T 3 ). _T3 ).

The enable signal 60 enables the latch circuit LAT to accept the clock switching signal 10 such that the output 90 (timing T ₃ ) of the latch circuit LAT becomes a logic "1" and the selector SEL
is used to select clock 200.
In this manner, as shown in the flowchart of FIG. 1, the clock is switched after checking that no data is being exchanged and inhibiting further data exchange.

Enable signal 60 is flip-flop FF1
Reset. As a result of this, the suppression of data exchange is lifted.

Next, at timing _T5 , when the clock switching signal 10 becomes logic "0" and switching from the clock 200 to the clock 100 is requested, the differential wave 20 with respect to the falling edge of the clock switching signal 10
occurs and flip-flop FF1 is set.
At this point, the communication display signal 40 has become logic "0", indicating that the information processing unit 4 is not exchanging data with either the information processing unit 5 or the information processing unit 6.
At T ₆ the output 50 of the AND gate AD1 and therefore at the timing T ₇ the enable signal 60 is generated. As a result, the output 90 of the latch circuit LAT becomes logic "0" at timing _T7 , causing the selector SEL to select the clock 100.

〔Effect of the invention〕

According to the present invention, as described above, there is provided a means for monitoring the operational status of a system that may be adversely affected by clock "whiskers" or phase difference transient phenomena that occur when switching clock cycles;
Means for suppressing the above operation after checking that the above operation is not performed based on the result of this monitoring, and means for instructing the clock supply source to switch the clock cycle when all the above operations are suppressed. This instruction is followed by means for releasing all of the above-mentioned inhibitions, so that the clocks are switched at a time when no system operations are taking place that could be adversely affected by transients that occur at the time of clock switching. Therefore, even if a transient phenomenon occurs during clock switching, the operation of the system is not guaranteed. Moreover, this effect is achieved with a small amount of hardware.

[Brief explanation of the drawing]

1 and 2 are a first embodiment of the present invention, FIG. 3 is a second embodiment of the present invention, FIG. 4 is a time chart for the second embodiment, and FIGS. 5A and 5B. The figure is a diagram showing a transient phenomenon at the time of clock switching. 1...Operation panel, 2...Processor, 3...
Clock supply unit, 4, 5, 6... Information processing unit, 41... Communication display flag, 42... Communication inhibition flag, DIF... Differentiating circuit, FF1, FF2
...Flip-flop, AD1...AND gate, IV1, IV2...Inverter, LAT...Latch circuit, SEL...Selector.

Claims (1)

[Scope of Claims] 1. In a clock switching control method in a system including a plurality of devices each operated by a clock whose cycle does not switch in conjunction with each other, when there is a request to switch the clock cycle, the clock cycle occurs at the time of switching the clock cycle. monitoring means for monitoring the state of the operation of the system that may be adversely affected by transient phenomena; and deterrent means for suppressing the operation after confirming that the operation is not performed according to the result of the monitoring; A clock comprising: instructing means for instructing the clock cycle switching to the clock supply source when all the operations are inhibited; and canceling means for canceling all the inhibits after the instruction. Switching control method.