JPH0518149B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high-density printed wiring method used in a pattern layout apparatus for printed wiring boards.

[Technical background of the invention and its problems]

In recent years, there has been an increasing demand for higher density printed wiring boards. Therefore, the following two methods have been considered in order to increase the density of printed wiring.

By narrowing the conductor width of the signal lines, the maximum number of signal lines that can be arranged in one grid interval (for example, 0.1 inch) is increased.

By reducing the land diameter of random through holes, the maximum number of signal lines that can be arranged between one grid is increased.

However, printed wiring boards made using this method have an extremely large number of random through holes with small land diameters and signal lines with narrow conductor widths (hereinafter referred to as wiring patterns) that require advanced manufacturing technology. Although it is possible to increase the density of printed wiring, it has the disadvantage of lowering manufacturing yield. For this reason, DA (Design
Automation) In automatic wiring using the program,
The step of removing unnecessary through holes, which follows the step of wiring processing, is designed to reduce as much as possible random through holes randomly placed during wiring by improving the route of the wiring pattern. However, even in this case, there are many random through holes with small random diameters.

Therefore, Japanese Patent Application No. 58-201309,
Using the high-density printed wiring method shown in No. 138842, random through holes randomly placed during wiring can be used to create lines in the wiring pattern by automatically wiring, removing unnecessary through holes, increasing the diameter of lands, etc. It is important to reduce grid offset as much as possible through improvements, as shown in Figure 1 (during wiring, the width shown by the dotted line is processed, and the offset value up to the width shown by the solid line is stored in the database. When creating materials (for example, drawing tape), the offset value is taken into account and the wiring pattern is placed along the solid line path. The route is changed as shown by the solid line) to improve clearance.

However, even with such processing, there are many wiring patterns with narrow conductor widths, and a substantial decrease in manufacturing yield is unavoidable.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide a high-density printed wiring method that can increase the density of printed wiring without sacrificing manufacturing yield.

[Summary of the invention]

In the present invention, after a wiring pattern is formed with a predetermined allowable wiring density (number of lines between pins) with a thin line width, if each wiring pattern is smaller than the allowable number of lines, the line width of the pattern is changed to a thick line. Process and thicken the wiring pattern within the allowable range,
This improves the manufacturing yield of high-density printed wiring boards.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 3 to 9. FIG. 3 is a block diagram showing the configuration of a computer system (automatic wiring processing device) according to an embodiment of the present invention. In the figure, 30 is a CPU that forms the center of the system, and according to an automatic wiring program 32 stored in a main memory 31, a printed wiring board is automatically manufactured using a design file (database) 34 stored in an external storage device 33. Perform wiring processing. Reference numeral 35 denotes an input/output control device that performs data input/output control between input/output devices such as the external storage device 33 and the CPU 30 (main memory 31).

FIG. 4 is a flowchart showing the procedure of automatic wiring processing according to an embodiment of the present invention realized by the apparatus shown in FIG. 3 above. In Figure 4, S1 is a step to perform rough wiring, S2 is a step to delete unnecessary through holes by changing the wiring pattern layer, and S3 is a step to change the land diameter of a random through hole by changing the route of the wiring pattern. step to enlarge, S4 is a step to perform fine wiring in consideration of improving the tight clearance as much as possible, S5 is a step to extract the wiring pattern for which the fine route has been determined in S4, S6 is to process all wiring patterns. Step to check if S7 is S5
Step to extract wiring information around the wiring pattern (position and size of forbidden zone, pin, through hole, position and thickness of wiring pattern running around the area), S8 can increase the conductor width. Step S9 is a step to increase the conductor width of the wiring pattern.

5 to 9 are for explaining the wiring processing operation of the above embodiment, respectively, and FIG. 5 shows a basic lattice and two types of quasi-lattices, which are wiring units on a printed wiring board. Figures 6 and 8 are diagrams showing the rough wiring patterns during automatic wiring processing where the conductor width is subject to change, and Figures 7 and 9 are the same as those shown in Figures 6 and 8, respectively. FIG. 5 is a diagram showing an example of a pattern obtained by performing the thick line pattern processing shown in FIG. 4 above on the pattern shown in the figure; In the figure,
51, 62, 72, 83, 93 are basic grids in which pins and random through holes can be set (can be used as wiring paths), 52, 63, 73, 84, 9
5 is a quasi-lattice obtained by dividing the basic lattice into eight equal parts, which can be used as a wiring path. Numerals 53 and 94 are quasi-lattices obtained by dividing the basic lattice into five equal parts, which can be used as wiring paths. 61,7
1, 81, 91 are pins or random through holes with the same land diameter as the pins, 82, 92 are random through holes with small land diameters where the land diameter could not be increased, and 64, 85, 97 are the conductor widths used during wiring. The thin wiring patterns 74 and 96 are wiring patterns whose conductor widths have been made thicker (thickened) by the steps shown in the flowchart of FIG.

On the wiring board, as shown in FIG.
and can be represented by two types of quasi-lattices 52 and 53.

Among these grids 51, 52, 53, the basic grid 5 is used for wiring steps S1 and S4 shown in FIG.
1. The quasi-lattice 52 is used as a wiring path. or,
Pins and random through holes 61, 71, 8
1, 82, 91, and 92 are located on the basic lattice 51. Furthermore, the random through holes 61, 71, 81, 91 with large pin and land diameters make it impossible to use two quasi-gratings 52 and one quasi-grating 53 between the basic lattices. Furthermore, the random through holes 82 and 92 with small land diameters make it impossible to use one quasi-lattice 52 between the basic lattices.

In the wiring process, first, in step S1, the land diameter is Perform rough wiring using small random through holes and wiring patterns with narrow conductor widths. Thereafter, in step S2, unnecessary through holes are deleted by changing the wiring pattern layer. Furthermore, in step S3, the land diameter is increased by changing the route of the wiring pattern, and then in step S4,
Perform detailed wiring to improve tight clearances. In the wiring pattern that has undergone such processing, as shown in Figures 6 and 8, there are places where the conductor width of the wiring pattern can be increased (for example, the thickness used in the proven two-pin wiring). may exist. Therefore, in step S5,
Extract position information for one wiring pattern. Furthermore, in step S7, wiring information around this wiring pattern is extracted. Based on this information, it is checked in step S8 whether the conductor width can be increased (whether the conductor width set with three pins between the pins can be changed to the conductor width set with two pins). As a result of checking in step S8, if it is possible to make the conductor thicker, the conductor width is increased in step S9. Figure 7 is the 6th
9 shows a case in which the conductor width is increased by using quasi-gratings 52 in the pattern shown in the figure, and FIG. 9 shows a case in which the conductor width is increased by using quasi-gratings 52 and 53 in the pattern in FIG. 8. There is.

By such thickening processing, it is possible to minimize the number of wiring patterns having narrow conductor widths and poor manufacturing yield.

〔Effect of the invention〕

As detailed above, according to the high-density printed wiring method of the present invention, the number of signal lines with thin conductor widths that are difficult to manufacture can be minimized without reducing the wiring density, and the manufacturing yield can be further improved. .

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the grid offset means, FIG. 2 is a diagram for explaining the bending processing means, and FIG. 3 is a block diagram showing the hardware configuration in one embodiment of the present invention. 4 is a flowchart showing the automatic wiring processing means in the above embodiment, FIG. 5 is a diagram for explaining the grid in the above embodiment, and FIGS. 6 to 9 are a flow chart showing the automatic wiring processing means in the above embodiment, and FIGS. It is a figure which shows the example of a pattern for demonstrating the pattern processing operation in an example. 30...CPU, 31...Main memory, 32...
Automatic wiring program, 33...external storage device, 3
4...Design file (database), 35...
Input/output control device, 51... Basic grid, 52, 53
... Quasi-lattice, 64, 74, 85, 96, 97...
wiring pattern.

Claims (1)

[Claims] 1 In automatic wiring processing equipment for printed wiring boards,
Wiring pattern position information and wiring pattern information are provided for patterns that have been wired under preset pattern layout conditions, including the positions of through-holes with land and landless, and the number of pins arranged in a certain grid unit. , the peripheral information of each wiring pattern is extracted for each wiring, and when it is confirmed that the number of inter-lattice wiring is less than the allowable number indicated by the pattern layout conditions above, the conductor width is determined for the wiring pattern. A high-density printed wiring method that changes the conductor width to be thicker than the conductor width set for the above-mentioned allowable number.