JPH0518262B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a programmable semiconductor device having a semiconductor body comprising an electrically insulating region formed by cutting a single crystal semiconductor region and an adjacent single crystal semiconductor region. the single-crystal semiconductor region has programmable cells disposed along its upper surface in laterally separated groups, each cell having a first PN junction in the single-crystal semiconductor region; a second PN junction corresponding thereto and substantially parallel to said surface;
The 1PN junction and the 2nd PN junction relate to a programmable semiconductor device that forms a pair of PN junction diodes connected oppositely to each other.

BACKGROUND OF THE INVENTION Programmable semiconductor devices, particularly programmable read-only memories (PROMs), have become increasingly important in applications as programmable electronic memories. Of particular importance among these applications are PROMs of the type having a matrix arrangement of memory cells, each memory cell having a pair of back-to-back connected PN junction diodes. Of these diodes in each cell, the first diode acts as an array element that electrically isolates the cell, and the second diode selectively breaks down the diode to create a logic "0" or logic value within the cell. This is for forming "1". This programmable diode can be permanently broken down and shorted by forcing a sufficiently large reverse current through its PN junction.

Back-to-back Conventional PROMs using diode-connected circuits use insulating materials, such as silicon dioxide, to laterally separate the memory cells. British Patent No. 2005079 “Programmable Read-Only Memory Cell”
In , M. Moussie disclosed such a PROM, in which each array
The diode is a vertical diode with a PN junction located horizontally within a single crystal silicon region of the semiconductor body, with its lateral sides contacting a silicon dioxide region that is entirely recessed (notched) into the semiconductor body. are doing. Each programmable diode is a diode having a PN junction whose upper surface is located in a region in polycrystalline silicon adjacent to the single crystal region. PN of each programmable diode
The junction extends generally perpendicular to the lower surface of the semiconductor body. Such PROMs are manufactured by forming an N-type epitaxial layer on the upper surface of a P-type substrate, and then forming a P-type epitaxial layer on top of this epitaxial layer. A deeply recessed N-type region is formed surrounding both epitaxial layers and contacts the lower surface of the recessed oxide region that constitutes the array diode. P in each cell
A hole is provided through which an insulating layer covering the mold epitaxial layer passes. Programmable diode PN
Junctions are formed in the polysilicon layer deposited on top of this insulating layer and on the portions of the P-type epitaxial layer exposed by the holes in the mask. this
Programming a PROM requires only a relatively small current, about 20 ma, but the horizontal diode increases its cell area. This is the conventional
This is a major drawback of PROM.

DISCLOSURE OF THE INVENTION The present invention provides a programmable semiconductor device having a semiconductor body comprising an electrically insulating region cut in a single crystal semiconductor region and the single crystal semiconductor region adjacent thereto. a single-crystalline semiconductor region having programmable cells disposed along its upper surface in laterally separated groups, each cell associated with a first PN junction in the single-crystalline semiconductor region; a second PN junction substantially parallel to said surface;
In a programmable semiconductor device in which a 1PN junction and a second PN junction form a pair of PN junction diodes connected to face each other, the second PN junction is formed within a region of a polycrystalline semiconductor provided on the surface. and said first and second
The term "substantially horizontal" for a PN junction is characterized in that the entire edges of the two PN junctions are in contact with the insulating region. This means that it is in a plane parallel to . Each PN junction is defined as "substantially horizontal" even if it is slightly upwardly or downwardly curved where it meets the insulating oxide region. With this configuration, both diodes within each PROM cell form a vertical diode. The lower diode formed by the first PN junction is usually used as an array element,
The upper diode formed by the second PN junction is usually a programmable element. By having both PN junctions in each cell completely adjacent to the insulating oxide region, the PROM according to the present invention occupies a very small area. The memory element within each cell is approximately
It occupies an area of 2.25 μm ² as standard,
This has the great advantage of being much smaller compared to conventional devices.

The lower cell region immediately below the first PN junction is the first
conductivity type, and the intermediate cell region is of the opposite conductivity type.
It is conductive type. Typically these cells are formed on top of a substrate region of the second conductivity type. This creates an inherent problem in that the substrate region acts as a collector for the parasitic transistors. The lower region of each cell acts as a base of this parasitic transistor, and the adjacent intermediate cell region acts as an emitter. When dielectrically breaking down the second PN junction of this cell, the first PN junction applies a bias in the passing direction. This turns on the corresponding parasitic transistor. The current injected into the substrate region by this parasitic transistor will induce a significant voltage in this substrate region, the value of which will exceed the PN junction between the substrate and the lower cell region of other cells in the same column. This value is sufficient to provide a bias in the passing direction. If such a situation occurs, there is a risk of deteriorating the second PN junctions of these other cells.

The present invention avoids these problems by providing a composite buried layer and providing intermediate electrical connections to the lower cell area. The buried layer has a plurality of highly doped buried regions of a first conductivity type directly below the lower cell region. Each buried region is adjacent to an insulating oxide region along the entire lower edge of the lateral periphery of one or more corresponding lower cell regions.
By contacting the buried region with the insulating oxide region in this manner, the amplification factor of each parasitic transistor can be significantly reduced, most typically by a factor of about 100. be able to. As a result, during the programming process for one cell, the voltage induced in the substrate area is significantly reduced, protecting it from undesired destruction of the programmable diodes of other cells in the same column. do.

The aforementioned composite buried layer includes a highly doped buried web of a second conductivity type that laterally surrounds each buried region. This buried web forms a low resistance path for removing the charge carriers injected into the substrate area by the parasitic transistors during this programming process, thereby better preventing the substrate potential from rising. can do.

The buried web is separated on its sides from the buried layer by a lightly doped region that includes the substrate region and extends upwardly toward the insulating oxide region. This lightly doped region is the PN of the substrate.
This serves to increase the breakdown voltage of the junction to an acceptable value.

An important advantage of the programmable semiconductor device according to the invention is that it is extremely insensitive to drawbacks caused by many materials or methods. These problems are limited to the actual memory element area of each cell that causes these defects, and this area is extremely small. The connections through the insulating oxide region to the composite buried layer are extremely insensitive to most of these defect-causing factors, while the majority of each PN junction is At least partially or completely protected. For this purpose, the PROM according to the present invention
is particularly suitable for manufacturing very large capacity memory arrays.

Example Embodiments of the present invention will be described below with reference to the drawings.

In each drawing, the same reference numerals are used for the same parts. Furthermore, the drawings do not correspond to the scale of the actual device, and some parts are enlarged and exaggerated to facilitate understanding of the explanation.

FIG. 1 shows a PROM implementation having a group of identical programmable read-only memory cells (hereinafter sometimes abbreviated as PROM cells), each consisting of a pair of oxide barrier vertical diodes in a back-to-back arrangement. An example cross-sectional layout is shown. FIGS. 2a and 2b are longitudinal side views of FIG. 1, respectively, seen from a direction perpendicular to each other, in a semiconductor body having a flat bottom surface 10.
This shows the structure of RROM. As shown in FIGS. 2a and 2b, the cross section in FIG.
The figure is cut along plane 11 parallel to .
Each element indicated by a dotted line in FIG. 1 is located below this plane 1-1. In the following descriptions, "lower side", "bottom", "upper side", "top", "bottom", "
Up",
"Vertical", "horizontal" and "lateral" are defined for convenience to describe the positional relationship of the semiconductor when surface 10 is parallel to ground level.
PROM cells shall be arranged in an array of rows and columns. The rows are approximately 20 μm apart.

In Figure 1, there are six PROM cells 12 _B , 12 _D , 12
_F , 12 _B ', 12 _D ', and 12 _F ' are shown. cell 1
2 _B , 12 _D , 12 _F are in one row, and cells 12 _B ′, 12 _D ′, 12 _F ′ are arranged in the immediately adjacent row. By making this arrangement, each suffix "B", "D", and "F" represents a particular column, of which the ones without a darts indicate the rows shown in Figure 2a, and the ones with a darts indicate the rows shown in Figure 2a; The rows that are next to this represent the rows that are adjacent to it. Some of the areas within the columns and some of the centers of the areas within the columns are designated using different suffixes "A", "C", "E", and "G". Cells 12 _B , 12 _D , 12 _F , 12 _B ', 12 _D ',
12 _F ' when looking at any of these elements or the different elements in the columns distinguished by the suffixes "B", "D" or "F", or the suffixes "A", "C", "E", and their symbols. Although a region with "G" is described, a region with "A" ~
Those marked with a "G" and those marked with a dash are shown with their full symbols in the drawings, but may be omitted from the following description. Further, some of the components of the cell 12 are omitted from illustration or only partially shown in the drawings in order to avoid complicating the drawings if all symbols are attached. For example, in FIGS. 2a and 2b, only cell _12D is fully labeled with the symbols of each component.

The lower portion of the cell 12 is formed within a doped single crystal silicon region of the semiconductor body, the sides of the upper surface 14 of the single crystal region being selectively buried within the body relative to adjacent portions. They are separated from each other by recessed web-like insulating oxide regions 16. The single crystal region of FIGS. 2a and 2b is the portion between the bottom surface 10 and the surface 14, excluding the insulating oxide region 16. The center-to-center spacing of the insulating dioxide regions 16 on both sides of all cells 12 is approximately
It is 11 μm. This oxide region 16 has a protruding portion 18 shaped like a bird's beak, which extends into the single crystal region so that each cell 12 is divided into a narrow net shape below the surface 14. , its cross-sectional area is approximately 2.25 μm ² . The crest-shaped portion of the oxide region 16 is approximately 0.4μ
m is exposed on the surface 14. The lowermost surface of this oxide region 16, measured from surface 14, lies within the body approximately.
Contains 1.1μm.

Each cell 12 consists of a lower array diode and an upper programmable diode. The array diode includes a lower N region 20, a P region 22 in the single crystal region, and a polycrystalline silicon P region adjacent to the P region 22 and along the surface 14.
A vertical PN junction element formed by a composite intermediate P region consisting of region 24. The common interface between the N area 20 and the P area 22 has a lateral area of approximately
^4μm2 , and the breakdown voltage is approximately
A first PN junction 26 of 20V is formed. Each P area 24
are each a part of the corresponding polycrystalline silicon region,
The remaining portion is the upper N+ polycrystalline region 28. The programmable diode is a vertical PN junction element formed by composite P regions 22 and 24 and N+ region 28, the common interface of which has a lateral area of about 8 μm ² and a breakdown voltage of about 8 V. This is a second PN junction 80. The large area of the first PN junction 26 prevents the quality of the programmable diode from being degraded when the programmable diode is programmed.

P region 22 is completely adjacent to the recessed sidewall of insulating oxide region 16, so that first PN junction 26 is also completely adjacent to this sidewall. Similarly, the P region 24 is completely adjacent to the beak-shaped raised portion 18, and therefore
It is completely adjacent to the insulating oxide region 16 of the 2PN junction 30. Each of these PN junctions 26 or 3
0 is mostly horizontal, but the oxide region 16
On the other hand, near the adjacent location, it may curve upward or downward as is conventional practice. Each of these
The center part of PN junction 26 or 30 is on the lower surface 1
0 and these junctions 26 or 3
These joints 26 or 30 are appropriately defined as "substantially horizontal" as long as the curve above or below 0 is extremely small.

The upper part of the structure of the cell 12 is connected to the lower N region 20.
It must be formed to provide electrical connections between the PROM cell column lines. The lower portion of the structure consists primarily of a lightly doped P-type semiconductor substrate. In the absence of a buried layer of highly doped N-type and P-type regions, each P region 22 (and 2
4) acts as the emitter of a vertical parasitic PNP transistor whose base is the adjacent N region 20 and whose collector is the remaining lightly doped P-type part of the substrate.

When programming a cell, the potential of all N+ regions 28 for a particular column is
8 by increasing the potential of the column conductor connected to 8. For example, when programming a specific cell 12, such as cell _12D , a current is forced to flow in the P region _22D (and _24D ) through the PN junction _26D , which is biased in the direction of its passage. 30 _D causes dielectric breakdown. This allows the parasitic PNP transistor associated with cell _12D to be turned on. The base-collector junction of this vertical parasitic transistor is
This becomes the base-emitter junction of the lateral parasitic PNP transistor. The base-collector junction of this lateral PNP transistor is connected to the remaining lightly doped PNP transistor.
Belonging to the same column as the mold board part, for example cell 12 _D
' is formed by the N regions 20 of all other cells 12 such as '.

When the parasitic PNP transistor saturates, its base-collector junction is biased in the pass direction, raising the substrate voltage and turning on the lateral NPN transistor. As a result, the voltage in the N region _20D decreases to approximately the same level as the voltage in the N region _20D , and
It may also damage the joint _30D . This is because the potential of the N+ region _28D ' is approximately the same as that of the N+ region _28D . To explain this simply, parasitics attached to cell 12 when programming
The action of the PNP transistor may damage the programmable diodes of other cells 12 in the same column. To avoid this problem, the present invention utilizes a composite buried layer for PROM cell 12 to provide an intermediate electrical connection to the word conductor.
It also provides electrical insulation between columns.

A portion of this composite buried layer is comprised of a respective set of buried N+ regions 32 directly beneath lower N regions 20 and contacting the lower surface of insulating oxide region 16. Each buried area (or tab) 32 is located in the lower area 2
It is advantageous to provide consecutive numbers for each of the four 0's. However, due to reasons shown in the drawing,
Buried area (tab) in figure and figures 2a and 2b
32 is provided continuously with respect to the two lower regions 20. For example, the buried area _32C is shown as being continuous with the lower areas _20B and _20D . This results in these buried areas (tab)
32 each of these buried areas (tabs) 32
The insulating oxide region 16 abuts the entire lateral periphery of each lower region 20 that is continuous with the
adjacent to the lower edge of.

The average net dopant concentration within this buried region 32 is approximately 1.6×10 ¹⁸ atoms/cm ³ . The lower N region 20 has a relatively uniform net dopant concentration of about 8
x10 ¹⁵ atoms/cm ³ , which is where the buried region (tab) 32 meets the oxide region 16 which contacts the N region 20 approximately 1.0 μm below the upper surface 14 . Buried region 32 extends approximately 4 μm below surface 14 into the body.

Each buried region (tab) 32 extends into a lightly doped P-type substrate region 34 bounded on the underside by surface 10 to form a respective insulating PN junction 36 therein. . This isolated PN junction 36 is normally reverse biased. P- region 34 has a relatively uniform net dopant concentration of approximately ^{1.times.10.sup.17} atoms/ ^cm.sup.3 . This is due to the N-
It is also the type dopant concentration.

Isolated PN junction 36 is the base-collector junction of the parasitic PNP transistor that is turned on during programming. Each buried region 32 is completely adjacent to the adjacent oxide region 16 surrounding the corresponding cell 12, so that this buried region (tab) 3
A part of the base of a parasitic PNP transistor is formed in the N+ part of 2. This means that the current amplification factor of about 10 without such a buried area (tab) 32 is about 0.1.
decrease to When programming one of the cells 12, this reduced amplification factor reduces the voltage developed in the substrate region 34 and prevents it from degrading the programmable diodes of other cells 12 in the same column. do.

A corresponding buried area 3 is formed by a composite N+ area 38 consisting of a lower N+ area 40 and an upper N+ area 42.
2 to the upper surface 14. The combination of N+ regions 32 and 38 provides the necessary intermediate connection between lower cell region 20 and column conductors. The highly doped content of each buried region 32 acts to reduce the series resistance between its connecting N+ region 38 and the corresponding lower cell region 20. Connection N+ region 38 provides a low resistance path to surface 14 to reduce parasitic voltage drops that occur during cell programming operations.

The other portion of the composite buried layer is a buried P+ web 44 that laterally surrounds each buried N+ region 32.
It is. This buried P+ web 44 is connected to the insulating region 16
adjoins the lower surface of and partially rises above its sidewalls. The average net dopant concentration of P+ web 44 is approximately 7×10 ¹⁷ atoms/cm ³ . Buried web 44 has a net dopant concentration of approximately 1×10 ¹⁷ atoms/cm ³ in contact with the lower surface of oxide region 16 and has a P-type dopant concentration approximately 3.5 μm below surface 14 of the substrate. It decreases in region 34.

An embedded P+ web 44 connects a plurality of complex low resistance P+ regions 46 on its upper surface 14 and extends along the rows of PROMs. The buried web 44 combined with the P+ region 46 forming the connection and the insulating oxide region 16 are connected to all the cells 12 of the tab formed by each buried region 32.
are electrically insulated from the cells 12 of the tabs in other regions 32. Therefore, the above combination insulates each row from each other. P forming a connection with web 44
The combination with + region 46 forms a low resistance path for transporting holes collected by PNP parasitic collector region 34 during cell programming. This ensures that when programming any cell 12, other cells 12 in the same column are programmed.
prevent damage to the programmable diode of the device.

The buried N+ region 32 forming each tub is connected to a corresponding portion of the lightly doped region formed by the P-type substrate region 34 and to an epitaxial layer located between the lower surface of the oxide region 16. It is separated from the buried web 44 by a round N region 48 . Each N region 48 has a relatively uniform net dopant concentration of approximately ^{8.times.10.sup.15} atoms/ ^cm.sup.3 . Due to the combination of relatively lightly doped P-type substrate region 34 and epitaxial N region 48, substrate insulating junction 36 has a sufficiently high breakdown voltage. (This voltage is typically about 30V.) Placing the connecting conductors completes the PROM. An N+ layer 50 of polycrystalline silicon is disposed over each N+ region 42. On N+ regions 28, 50 and P
A pattern of conductive lines 54 made of aluminum with approximately 1% silicon is placed over the + region 46. Conductive wires 54 _B , 54 _D , and 54 _F are column conductive wires. All conductors 54 other than conductor 54 _C and its counterpart connecting the row conductors are shown in FIG. 2b as conductor 54 _D , which extends along the columns.

A second intersecting conductor path of the same conventional design is provided to form the row conductors and complete the connection arrangement. The cross figure of the second conducting wires is omitted from illustration to avoid making the drawing too complicated. Second
To provide the conductor pattern, a layer of phosphorous-doped silicon dioxide (Vapox) is provided over the conductive lines 54 and over the portions of the insulating oxide region 16 between the conductive lines 54. The intersection shape of this conductor is
Made of pure aluminum on a Vapox layer,
Connections are made using aluminum filled vias extending through the Vapox layer to conductor _54C and its counterpart.

To program this PROM, a reverse current of approximately 40 mA is forced through each PN junction 30 to be destroyed. For example, when attempting to destroy a PN junction 30 _D , conductor 54 _C is most typically used for a suitable length of time, less than 1 microsecond (μS).
and 54 _D to create an avalanche breakdown in the programmable diode, allowing the reverse current described above to pass. This programmable diode is heated until it reaches the aluminum-silicon eutectic temperature of approximately 577°C. At this eutectic temperature, the programmable _diode is
8 _D into P region 24 _D and is permanently shorted to form an ohmic contact. This location will be either a logic "0" or a logic "1" within the cell _12D depending on the system used; programmable cells 12 that are not processed in this manner will have the opposite logic state.

Figures 3a-3m show the manufacturing process of the PROM shown in Figures 1, 2a and 2b. P to create various P-type conductivities within each manufacturing process.
Boron is used as a mold impurity. Unless otherwise indicated, this boron is introduced by ion implantation in the B+ form. Phosphorus, arsenic and antimony are selectively used as complementary N-type dopants. Unless otherwise specified, these are introduced by ion implantation in the form of P ⁺ , As ⁺ and Sb ^{+ ,} respectively. Other suitable impurities can also be used in place of these dopants. In many ion implantation processes, impurities can also be introduced into the wafer by diffusion rather than ion implantation.

Conventionally known cleaning and photoresist mask techniques are used to fabricate the various insulating regions, P-type regions, and N-type regions; however, in the following description, for the sake of simplicity, cleaning steps, photoresist mask manufacturing steps, Also, explanations regarding techniques that are very well known in semiconductor technology have been omitted. Unless otherwise specified below, the silicon dioxide etch step shall be carried out with a buffered etchant consisting of 40% ammonium fluoride, 7 parts, and about 1 part 49% hydrofluoric acid.

The first step in the manufacturing method is to connect the N+ region 32 and the P+
2. Positioning the composite buried layer consisting of the web 44. In FIG. 3a, the starting material is a semiconductor wafer having a P-type single crystal substrate 60 with a resistivity of about 7-21 Ωcm and a thickness of about 500 μm. 1000
Place this wafer in an oxidizing atmosphere of oxygen and hydrogen at
After leaving it for 360 minutes, the upper surface of this substrate 60 has a thickness of approximately
A layer 62 of 1.2 μm silicon dioxide is grown. A photoresist mask 64 having openings is formed on oxide layer 62 approximately above the locations where buried N+ region 32 and web 44 are to be provided. This oxide layer 62
An 18-minute etching process is applied to the exposed areas of the mask, and a thick layer of silicon dioxide is applied to the open areas within the mask.
800 to 1400 Å remains.

After removing the mask 64, the N
A non-critical photoresist mask 66 having a nominal thickness of approximately 7000 Å with openings substantially above the desired portions of the mold area is formed on the top surface of the wafer as shown in FIG. 3b. The remaining exposed portions of oxide layer 62 are etched for three minutes to reach the silicon of substrate 60. The mask 66 is then implanted with antimony at a rate of 2×10 ¹⁵ ions/cm through the remaining open area of the oxide layer 62 at 50 kiloelectron volts (KEV) to form the N+ region. Form 68.

After mask 66 is removed, the wafer is exposed to nitrogen at 1000°C for 20 minutes, oxygen and hydrogen at 1000°C for 13 minutes, and nitrogen at 1200°C for 75 minutes. As a result, a layer 72 of silicon dioxide having a thickness of about 2400 Å is formed on the exposed area of the substrate 60, thereby forming a depression 70 for registration. Due to the high temperature in this process, the arsenic in the region 68 penetrates further into the lower interior (and sides) of the substrate 60. a photoresist mask 74 having a reference thickness of 1.2 μm on the top surface of the wafer and which does not need to be strictly specified;
A photoresist having a web diameter opening is formed above a desired position of the embedded web 44. The remaining exposed portion of oxide layer 62 is 3.5
By etching for a minute, it is removed until it reaches the silicon in the substrate 6. 2×10 ¹⁴ ions/cm ² and 180KEV with mask 74 in place
Boron is implanted into the substrate 60 with an energy of .times.3 to form a P+ region 76.

After removing mask 74, the wafer is etched for 20 minutes to remove oxide layer 72 and the remaining portions of oxide layer 62, as shown in FIG. 3d. An arsenic-doped epitaxial layer 78 having a resistivity of about 0.7 ohm-cm is grown on the exposed upper silicon surface to a thickness of about 1.75 .mu.m by a known silane process. Areas 68 and 76 are created by the previous steps.
is embedded and formed within the structure.

An insulating oxide region 16 is then formed. A layer 80 of silicon dioxide is first grown about 300 Å along the upper surface of epitaxial layer 78. This can be formed by exposing the wafer to dry oxygen at 1000° C. for 11 minutes. A layer 82 of silicon nitride having a thickness of approximately 1200 Å is deposited over oxide layer 80 using a conventional low pressure chemical vapor deposition process. The wafer is then exposed to a mixture of oxygen and hydrogen at 1000 DEG C. for 120 minutes to form a thin layer 84 of silicon dioxide on the upper surface of nitride layer 82. As shown in FIG. 3d, each registration recess 70 is
8, 80, 82 and 84 are similarly formed. A photoresist mask 86 having openings on the web at locations corresponding to desired locations of insulating oxide region 16 is formed on oxide layer 84 . Oxide layer 8
Remove the exposed portion of 4 by etching for 1.5 minutes.

After removing the mask 86, the nitride layer 82 is
As shown in the figure, etching is performed using high temperature phosphoric acid at 165° C. for 35 minutes to remove down to the oxide layer 80. The oxide layer 8 is then etched for one minute.
The exposed portions of 0 are removed down to epitaxial layer 78. The exposed portion of epitaxial layer 78 is etched away by approximately 6500 Å on the underside, leaving trench 8.
7 is formed. This is 70% nitric acid, 250 parts, 49
By using an etchant consisting of 40 parts of % hydrofluoric acid and 1000 parts of acetic acid saturated with iodine for 25 minutes at 23°C.

By exposing this wafer to oxygen and hydrogen at 1000° C. for 360 minutes, an insulating oxide region 16 having a depth of about 1.25 μm is formed along the groove 87 as shown in FIG. 1f.
is formed. This insulating oxide region 16 is
Since it does not extend into 0, portion 48 of N-type epitaxial layer 78 lies directly below the lower surface of the oxide region. During this high temperature treatment step, the boron in region 76 diffuses downward toward substrate 60 and upward toward epitaxial layer 78, forming a P+ web 44 that extends to the sidewalls of oxide region 16. . Similarly, antimony in region 68 also
The N+ buried region 32 is diffused downwardly into the epitaxial layer 78 and upwardly to form the N+ buried region 32. Especially tab 3
The cross section of the lower surface of the oxide region 16 on the upper side of 2 is
Registration recess 70 is approximately 1000 Å lower than the rest of the lower surface of oxide region 16. Buried region 32 extends upwardly enough to at least touch the bottom surface of oxide region 16.

The remaining N-type portions of epitaxial layer 78 that laterally contact oxide region 16 are used for cell 12 and are used to connect regions 38 and 46. Each of these N-type single crystal portions used for the cell 12 is formed from a bird's beak portion 18.
It has dimensions of about 2 μm on the lower side.

The remaining portion of oxide layer 84, which has grown slightly from the previous high temperature process, is removed by etching for 1.5 minutes, as shown in Figure 3g. The remaining portion of nitride layer 82 is also removed by etching with hot phosphoric acid at 165° C. for 35 minutes. The remaining portion of oxide layer 80 is also removed by a 1 minute etch. An insulating layer 88 of silicon dioxide having a thickness of approximately 1000 Å is formed along the exposed portions of epitaxial layer 78 by placing the wafer in oxygen and hydrogen at 900° C. for 26 minutes. Since this oxidation step is performed at a relatively low temperature, the tab-shaped buried region 32 and the web 4
No particular rearrangement of impurities within 4 occurs. The formation of the tab-shaped buried region 32 and the buried web 44 is almost completed.

Next, the regions of the connecting conductive lines 38, 46 and the transistors of the peripheral circuit are formed. A photoresist mask 90 is formed on the top of the wafer, having an opening at a position planned as the region of the connecting conductive wire 38 and having a standard thickness of about 8000 Å, which does not need to be particularly strictly defined. A two minute etch removes the exposed portions of oxide layer 88. With mask 90 in place, phosphorus is also dosed into the exposed portions of epitaxial layer 78 at 3×10 ¹⁵ ions/cm ² .
Implantation is performed with energy of 180KEV to form N+ region 92.

After removing the mask 90, it is annealed at 1000° C. for 120 minutes to repair damage to the latisse structure. The wafer is then placed in contact with oxygen and hydrogen at 900 DEG C. for 31 minutes to grow silicon dioxide having a thickness of approximately 1400 Å on the exposed portions of epitaxial layer 78, as shown in FIG. 3h. During this oxidation step, oxide layer 88 increases in thickness by approximately 1000 Å. area 92
The phosphorus within is relocated and expands this region downward, and the boron within the buried web 44 diffuses upward slightly. During this treatment step, the arsenic within the tab-shaped buried region 32 does not undergo any significant rearrangement.

A photoresist mask 96 is formed on the top of the wafer, having an opening at a desired location in the region of the P+ connection conductor 46 and having a standard thickness of 1.2 μm. This photoresist mask 96 does not need to be particularly precisely aligned with the area of the P+ connection conductor 46. With photoresist mask 96 in place, a double implantation of boron is performed into lower epitaxial layer 78 through exposed portions of oxide layer 88 to form P+ regions 98. The first implantation step was performed at 1×10 ¹³ ions/cm ^{2 .}
The second implantation step is carried out with an energy of 180 KEV and a dosage of 1.5×10 ¹⁴ ions/cm ² and an energy of 75 KEV.

After removing the photoresist mask 96, a photoresist mask 10 having a nominal thickness of 8000 Å and having openings at desired positions relative to the area of the connecting conductor 38 is removed.
0 is formed on top of the wafer as shown in Figure 3i. The mask 100 does not need to be particularly strict in the region of the conductive wire 38. Oxide layer 94 is removed by etching for 4 minutes. First, add 1 arsenic
Implantation was performed with an energy of 180 KEV in a dosing chamber of ×10 ¹⁵ ions/cm ² , followed by 2
N+ region 42 is formed in the upper portion of region 92 by shallow implantation of arsenic at x10 ¹⁵ ions/cm ² and an energy of 50 KEV.

The wafer is annealed in nitrogen at 1000° C. for 60 minutes to repair damage to the lattice structure created by the implantation and to redistribute the arsenic boron within regions 42 and 98. As shown in FIG. 8j, the area 42 moves downward. The boron within the buried web 44 expands slightly outward, and the area 98 moves downwardly and joins the web 44 to form the area of the P+ connecting conductor 46. Areas 32 and 92 also grow slightly.

The diode within cell 12 is then formed. For this purpose, a photoresist mask 102 having a standard thickness of 1.2 μm and having an opening at a desired position relative to the lower portion of the cell 12, which does not require particularly strict alignment, is formed on the top of the wafer. oxide layer 8
The exposed portions of 8 are removed down to the underlying epitaxial layer 78, exposing a portion of the upper surface 14. With mask 102 in place, boron is implanted into epitaxial layer 78 with an appropriate dose and energy to form P-type region 22 and form PN junction 26. During this implantation, the sidewalls of insulating oxide region 16 act as a mask to control the lateral spread of the boron impurity, thereby defining the lateral location of PN junction 26.

After removing mask 102, a layer of intrinsic (undoped) polycrystalline silicon is deposited on top of the wafer along surface 14 over areas 22 and 42 to a suitable thickness, e.g.
Form into Å. The N-type impurity, such as arsenic, is implanted at a dose and energy such that a final depth of about 500 Å is present on surface 14 and a PN junction 30 is formed. A photoresist mask 104 is formed above this polycrystalline layer so that the photoresist is substantially located on regions 22 and 44 using polymer. The exposed portions of the polycrystalline layer are etched away using a conventionally known etching agent such as phosphorous hydroxide.
A composite polycrystalline region is left along surface 14 on each region 22 and 42 as shown. Each composite polycrystalline layer consists of a lower intrinsic (undoped) polycrystalline portion 106 and an upper N+ polycrystalline portion 108.

After mask 104 is removed, it is annealed at a relatively low temperature, e.g., 950° C., in an inert atmosphere, e.g. Form a region. During this annealing step, some of the boron in region 22 migrates sufficiently upward into the polycrystalline silicon above it, and
The arsenic within 8 is reached, as shown in Figure 3l.
A PN junction 30 is formed. The lower portion of the polycrystalline silicon in this case is the P region 24, and the upper portion thereof is the N+ region 28. Some of the phosphorus in region 42 also migrates into the overlying polycrystalline silicon and reaches the arsenic in overlying region 108, forming composite N+ region 50. The arsenic within the original 108 region does not migrate significantly downward. This annealing step extends P region 22 downwardly to its final location, leaving region 20 in place as the remaining portion of N-type epitaxial layer 78 within cell 12. Regions 42 and 92 also expand slightly downward and occupy their final positions, with region 92 being the N+ region 4.
0, which extends to the corresponding buried area 28. Region 46 similarly moves slightly downwards and assumes its final position. This annealing process is performed on the PROM cell 12.
Completed the manufacturing of the diode inside, and also connected the connecting conductor 3.
Complete the manufacturing of areas 8 and 46.

In this state, the wafer is ready for placement of connecting conductors to areas 28, 50, 46 for making electrical contacts on the top of the wafer. A photoresist mask 1 having an opening above the P+ region 46 on the top of the wafer and which does not require particularly strict alignment.
form 10. Oxide region 88 is removed to area 46 in a 4 minute etch step using a suitable etchant.

After mask 110 is removed, a layer of aluminum is deposited on top of the wafer and including the tops of monocrystalline regions 42, polycrystalline regions 28 and 50 to a suitable thickness, such as 7000 Å. A photoresist mask 112 is placed on top of this aluminum layer.
patterning the aluminum layer by forming a photoresist so that the polymer of the photoresist is on the aluminum above regions 28, 50, 46, and then etching the exposed aluminum with a suitable etchant; A connecting conductor 54 is formed as shown in FIG. 3m. The mask 112 is then removed and FIG. 2a (and FIG. 2b)
The structure shown in is completed.

As mentioned above, the second layer of aluminum conductors is formed by any suitable conventional method. This involves evaporating and depositing a Vapox layer approximately 9000 Å thick on top of the wafer.
Using a suitable photoresist mask, etch down to the bottom of the conductor 54 to be selected.
A layer of pure aluminum is deposited over the Vapox and over the selected conductive lines 54, and another photoresist mask is used to pattern the aluminum layer, thereby forming the PROM.

Although the present invention has been described with reference to a specific embodiment, this embodiment is just one example for ease of understanding, and it is understood that the present invention is not limited thereto. For example, the connection area for a composite buried layer is
It can also be provided after the diodes in the PROM cell are formed. Alternatively, the composite buried layer of the PROM cell and the connection area for the diode can be provided at once by performing the same extensive implantation or diffusion process. Furthermore, the materials and dopants used in each of the steps described above may be of the opposite conductivity type. That is, many modifications can be made by those skilled in the art without departing from the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of a PROM according to the present invention, taken along the plane-line of FIGS. 2a and 2b. Figure 2a shows
Figure 1 is a vertical side view taken along the line 2a-2a, Figure 2b is a side view taken along the line 2b-2b in Figure 1, and Figures 3a-3m are the 1st and 2nd lines.
2a and 2b are longitudinal sectional side views illustrating each process for manufacturing the embodiment shown in FIGS. 2a and 2b, the cross sections of which correspond to the cross sections of FIG. 2a. 10...Bottom surface, 12...PROM cell, 14...
...upper surface, 16... insulating oxide region, 20...
Lower N area, 22nd, 24th... P area, 26th...
1PN junction, 28...N+ polycrystalline region, 30...
2nd PN junction, 32... Buried N+ area (or tab), 38, 40, 42... N+ area, 44...
P+ web, 46...P+ region, 50...polycrystalline N+ layer, 54...conducting wire.

Claims (1)

[Scope of Claims] 1. A programmable semiconductor device having a semiconductor body comprising an electrically insulating region formed in a cut shape in a single crystal semiconductor region and the single crystal semiconductor region adjacent to the electrically insulating region, the programmable semiconductor device comprising: The monocrystalline semiconductor region has programmable cells along its upper surface in groups laterally separated from each other, each cell having a plurality of programmable cells located in the monocrystalline semiconductor region.
1PN junction and a corresponding second PN junction substantially parallel to the surface, the first PN junction and the second PN junction forming a pair of PN junction diodes connected to each other in a facing manner. In the programmable semiconductor device, the second PN junction is provided on the surface,
A programmable semiconductor device, characterized in that the programmable semiconductor device is present in a region of a polycrystalline semiconductor, and is in contact with the insulating region at all edges of the first and second PN junctions. 2. The semiconductor device according to claim 1, wherein in each programmable cell, a boundary between a lower region of the first conductivity type and an upper region of the second conductivity type forms the first PN junction. , a number of more highly doped buried regions of a first conductivity type are laterally spaced from each other, each of said buried regions being associated with at least one said lower region; A programmable semiconductor device characterized in that the side region is continuous with the upper region, and the entire lower edge of the side edge of each corresponding lower region is in contact with an insulating region. 3. The programmable semiconductor device of claim 2, wherein each of a plurality of similar connection regions of a first conductivity type extends above a different one of said buried regions. 4. The programmable semiconductor device according to claim 3, wherein a buried web of a second conductivity type opposite to the first conductivity type surrounds each buried region laterally. 5. Claims in which a lightly doped region continuous with the buried region and the buried web extends along all their sides to an upper insulating region, separating the buried web from the buried region. The programmable semiconductor device according to scope 4.