JPH0519743B2 - - Google Patents

Description

[Detailed description of the invention] Technical field of invention The present invention relates to a dual processor system.

Background of the Technology In order to increase the reliability of computer-controlled systems, it is common practice to duplicate processors. That is, an active processor and a standby processor are installed together, and when a failure occurs in either one, the system is switched to the other to prevent the system from going down. In this case, since the terminal systems controlled by these processors are usually not duplicated, a line switching device is provided between these processors and the communication lines connected to these terminal systems. The present invention mainly refers to this line switching device.

Prior Art and Problems FIG. 1 is a block diagram showing an outline of a general duplex processor system. In this figure, 1
1-0 is a 0-system processor, that is, an active system processor, and 11-1 is a 1-system processor, that is, a standby system processor. One of the processors is selected by the line switching device 12, connected to the communication line 13, and exchanges data with various terminals (not shown). In the dual processor system shown in this figure, all switching control of the device 12 is performed from the processor side. Furthermore, the switching control is performed with the help of the operation monitoring device 14. In this case, the operations handled by the processor require fairly complex software and complex hardware to support it. Therefore, the original role played by the processor itself is reduced to accommodate the above-mentioned operations. This is the problem.

Purpose of the Invention Therefore, in view of the above-mentioned problems, it is an object of the present invention to propose a duplex processor system that can significantly reduce the burden on each processor required for line switching. be.

Structure of the Invention In order to achieve the above object, the present invention provides that both the active and standby processors periodically transmit first information indicating the first logic level to the first processor in the line switching device as long as they are normal. It is equipped with a status notification unit that sends information to the register. The line switching device further includes a second register that stores the line connection state;
a logic judgment control unit that determines the line connection state, and this logic judgment control unit includes a first register and a second register.
The contents of the register are periodically read and the line connection state is determined from the logical pattern. Furthermore, the logic judgment control unit periodically writes the first register using a signal of a second logic level different from the first logic level, in synchronization with the periodic write timing of the first information, and with a shift from the timing. I am trying to clear the contents of.

Embodiment of the Invention FIG. 2 is a block diagram used to explain the principle of a duplex processor system based on the present invention.
3A and 3B are time charts used to explain the operation of the duplex processor system of FIG. 2. FIG. In FIG. 2, 21-0, 21-1, and 22 correspond to the active processor, standby processor, and line switching device shown in FIG. 1, respectively. No changes have been made to the communication circuit 13 and the terminal (not shown) connected thereto. Each processor 21-
0 and 21-1 are provided with status notification units 23-0 and 23-1. Each status notification unit 23-0,
23-1 sends out first information indicating that its own processor is in operation. This is done periodically. On the other hand, the line switching device 22
It has a first register 24 for storing information. Logic "1" is periodically written to this first register 24, and its contents are periodically cleared. An example of a series of operations is shown in FIG. Figure A shows the relationship between the processor 21-0, the first bit of the first register 24, and the line switching device 22, and Figure B shows the relationship between the processor 21-1, the second bit of the first register 24, and the line switching device. 22 relationships are shown. When the entire system starts up (time t0), the device 22
first writes logic "1" to both bits of register 24. After that, at time t1, for example, processor 2
If 1-0 rises first, the status notification unit 23-0 writes the first information (logic "0") to the first bit of the register 24. Then time t2
The device 22 again writes logic "1" to both bits of the first register 24 within itself. Furthermore, the same process is performed for the processor 21-1 after the processor 21-1 starts up after time t3. Note that the processor starts up means that the processor actually enters the operating state or can enter the operating state at any time. As described above, as long as both processors are normal, the logic “0” is periodically output.
The first information is written to the first register 24, and at the same time, a logic "1" is written to the first register 24 from the device 22, while shifting the timing. Ru. After all, if the bit becomes a logic "0" when a logic "1" is written from the device 22, it is determined that the processor is operating normally. Here, if a failure occurs in the processor 21-0 at time t4 (see FIG. 3A), the first information of logic "0" will no longer be supplied from the failed processor 21-0.
Then, at time t5, the device 22 registers the register 2.
When writing a logical ``1'' to 4, it is discovered that the bit remains ``1''. At this point, the device 22 becomes aware of the occurrence of a failure and begins a predetermined line switching operation.

FIG. 4 is a block diagram showing a specific example of a duplex processor according to the present invention. Components that have already been described are indicated with the same reference numerals. Status notification unit 2 in processors 21-0 and 21-1
3-0 and 23-1 are each timer 41
-0 and 41-1 and write control units 42-0 and 42-1, and as long as these processors are in normal operation, the first register 2 in the device 22
The first information of logic "0" is periodically written to the corresponding bit at 4 (Write in the figure). Note that the periodicity is defined by the interrupt (Int in the figure) of the timer (41-0, 41-1).

The first register 24 has logic “1” as described above.
is written periodically, and this writing is performed by the logic judgment control section 43 via the signal line S1. Prior to this write, the control unit 43 sets the content of the first register 24 to logic “0”.
It is necessary to check whether the
The contents of the first register 24 are read (Read) via the signal line S2. Note that the information read from the first register 24 becomes important information for logical judgment described later.

In order to make the above logical judgment, in addition to the above first information, the second
Information is required (more on this later). This second information is periodically read out from the second register 44 via the signal line S3 and is used for logical judgment by the control section 43. The second information is a switch section 45 in the device 22.
represents the line connection status. That is, the communication line 13 is connected to either processor (21-0 or 21-0).
1-1). In addition, for reading the first information and the second information described above, the signal line S
All writing of logic "1" by 1 is performed periodically, and therefore a periodic interrupt (Int) is generated by the timer 46. Thus, the logical judgment control section 4
After making a predetermined logical judgment, 3 gives a switching instruction signal SW to the switch section 45 via the signal line S4 to set it in a predetermined line connection state. At this time, the second information indicating the line connection state is written to the second register via the signal line S5.

FIG. 5 is a logic pattern diagram for explaining the logic judgment operation of the logic judgment control section 43 of FIG.
In this figure, the left column shows the contents of the first register 24 (the left is bit B0 for the active processor 21-0,
On the right is bit B1 for standby processor 21-1)
The upper column shows the contents of the second register 44.
This means that the switch section 45 is not connected (00) (1st bit is 21-0 system, 2nd bit is 21-1 system), active system (0 system) is connected (10), and standby system (1 system) is connected. It can be divided into three states (01). The way to read this logic pattern diagram is to read the logic pattern at the intersection of any one of the first registers 24 and any one of the second registers 44. For example, if the content of the first register 24 is (10) (I ), if the content of the second register 44 is (10) (b in the figure), a switching instruction signal SW of the content (01) shown in c in the figure is sent to the switch unit 45. (01) in this C represents switching the connection to the 1st system. In other words, in this case, a failure has occurred in the processor 21-0,
Since the switch unit 45 is currently connected to the processor 21-0, this indicates that the line connection should be switched to the processor 21-1. Similarly, (01) in D indicates that the processor 21-1 should be switched to, and (10) in E, H, and G indicate that the processor 21-0 should be switched. Other locations without the symbols A, B, and C indicate that the line connection is left as is (does nothing). Note that if both processors are at fault ((11) shown in Figure 1), the line connection status is set to (00), ie, not connected. The logical judgment control section 43 controls the switch section 45 based on the above-mentioned logical judgment.

6A and 6B are flowcharts showing the line connection control procedure of the logic judgment control section 43 of FIG. 4. However, the content of this flowchart is almost the same as the above explanation. In step (a), the first information of each bit of the first register 24 is read out. In step (b), the state in which the contents of the first register 24 are (00) can be detected by calculating the logical sum of the 0 series and the 1 series (see FIG. 5). In other words, if the value of the logical sum is "0", the first register 24
The content of is (00), and the process moves to step (c). If the value is “1”, the first register 24
The content of is (10), (01), or (11). In this case, proceed to step (g). In step (c), the second register 4
Read the 0 series bits (left side bits) of 4, and if the value is "0", proceed to step (d), and then read the 1 series bits (right side bits) of the second register 44, and if this value is "0", Connect the switch section 45 to the 0 system (or keep it as the 0 system) and proceed to step
In (e), the line connection status (10) is written into the second register 44. On the other hand, if the value is "1", the switch unit 45 is connected to the 1st system (or maintained as 1st system), and the line connection status (01) is stored in the second register 44 in step (f). Write.

Even when the read value in step (c) above is “1”,
Move to step (e).

If the logical sum value in step (b) is "1", then in step (g), the 0 series and 1 series of the first register 24 are
Take the logical product of the system. If this value is "1", it corresponds to H in FIG. Conversely, if the value is "0", it is I or N in Figure 5, and if it is A, connect to the 1 system (or keep it as 1), and if it is N, connect to the 0 system. (or keep it as 0 system), and at step,
A value obtained by inverting the contents of the first register 24 is written to the second register 44.

Effects of the Invention As explained above, according to the present invention, the active processor and the standby processor only need to be provided with simple status notification units 23-0 and 23-1.
The burden on these processors required for line monitoring is considerably reduced. Further, the line switching device 22 only needs to be provided with the first and second registers 24, 44 and a relatively simple logic judgment control section 43, and does not require advanced processor functions or complicated hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of a general duplex processor system, FIG. 2 is a block diagram used to explain the principle of a duplex processor system based on the present invention, and FIGS. 3A and B 2 is a time chart used to explain the operation of the duplex processor system shown in FIG. 2, FIG. 4 is a block diagram showing a specific example of the duplex processor system according to the present invention, and FIG.
6A and 6B, which are logic pattern diagrams for explaining the logic judgment operation of the logic judgment control unit 43 shown in the figure, are flowcharts showing the line connection control procedure of the logic judgment control unit 43 of FIG. 4. 13... Communication circuit, 21-0... Active system processor, 21-1... Standby system processor, 22... Line switching device, 23-0, 23-1... Status notification section, 24
...First register, 43...Logic judgment control unit, 44...
Second register, 45...switch section.

Claims (1)

[Scope of Claims] 1. An active processor 11-0 and a backup processor 11-1, and the active or backup processors 11-0, 11.
-1, and a line switching device 22 including a switch section 45 that selectively switches and connects the communication circuit 13 connecting these processors and the terminal to which data is to be exchanged to either the active system or the standby system processor. In a duplex processor system comprising: the active and standby processors 11-0,
11-1 each include a status notification unit 23-0, which periodically sends first information indicating a first logic level to the line switching device 22 as long as it is normal.
23-1, and the line switching device 22 is further provided with an information holding means and logic judgment control section 43, wherein the information holding means is connected to the active system and standby system processors 11-0, 11-1. a first register 24 in which each of the first information from each of the status notification sections 23-0 and 23-1 is written; and a second register 44 in which second information indicating the line connection state in the switch section 45 is written. The logic judgment control unit 43 periodically writes the first information in the first register 24 in synchronization with the writing timing of the first information in the first register 24 and while shifting the timing. clearing the logic level of the logic level to a second logic level different from the first logic level, and fixing the first information to the second logic level by periodically reading the first information. is detected, the occurrence of a failure in the active or standby processor is detected, and based on each logical pattern of the first and second information periodically read from the first and second registers 24 and 44, respectively. The line connection state in the switch section 45 is periodically determined, and the second information corresponding to the determined line connection state is transmitted to the second
A dual processor system characterized in that writing is performed in a register 44.