JPH0519826B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improvements in substrates for configuring MIS transistor logic circuits.

Background of the Invention As a cutting board for configuring MIS transistor logic circuits,
Conventionally, when a semiconductor substrate 1 is divided into a large number of element regions each having a square or rectangular shape, as shown in FIG. S and drain region D are formed with a required inner distance maintained between them, and an element region is formed integrally with the source region S in a band shape in a direction perpendicular to the arrangement direction of the source region S and drain region D. A wiring layer Y consisting of a region similar to the source region S extending to the outside.
2 is formed on the semiconductor substrate 1, and on the other hand, a gate electrode G is formed on the semiconductor substrate 1, facing the region between the source region S and the drain region D, with an insulating film (not shown) interposed therebetween; A structure has been proposed in which a wiring layer Y2 made of a conductive layer similar to that of the gate electrode G is formed integrally with the gate electrode G and extends in the extension direction of the gate electrode G to the outside of the element region. .

According to the MIS transistor logic circuit configuration board having such a configuration, as shown in FIG.
An interlayer insulating film (not shown) is formed on the semiconductor substrate 1 by embedding the gate electrode G and the wiring layer Y2, and the interlayer insulating film (not shown) is formed on the interlayer insulating film so as to face the source region S and the drain region D and to form a region between the regions S and D. A wiring layer X is formed facing the region, perpendicular to the gate electrode G, and extending to the outside of the element region Q, and the wiring layer X and the drain region D are extended through an interlayer insulating film. As shown in FIG. 3, wiring layers X and Y2 are connected by contact C,
A logic circuit having a MIS transistor T accessed by the wiring layer Y1 can be configured.

However, in the case of the conventional MIS transistor logic circuit configuration board shown in FIG.
However, the semiconductor substrate 1 is integrally connected to the source region S.
Reasons include that the wiring layer Y2 is the same region as the source region S that is formed extending into the gate electrode G, and that the wiring layer Y2 is a conductive layer similar to the gate electrode G that extends integrally with the gate electrode G. Therefore, programmable logic arrays, read-only memory circuits, etc., together with their peripheral circuits, can be made small and compact, and the resistance of the source region S and drain region D and the resistance of the wiring layers X, Y1, and Y2 are small.
There is a limit to the configuration in which the capacitance associated with the wiring layers X, Y1, and Y2 is small.

DISCLOSURE OF THE INVENTION The present invention therefore seeks to propose a novel substrate for configuring MIS transistor logic circuits, which does not have the above-mentioned drawbacks.

According to the substrate for configuring an MIS transistor logic circuit according to the present invention, (i) when a semiconductor substrate is divided into a large number of element regions having square or rectangular shapes, a square or rectangular shape is formed in each element region from the main surface side. Only a drain region and a source region whose width is approximately equal to that of the drain region and whose length is longer than that of the drain region are the same as those of the element region, with the length direction of the source region being the length direction of the element region. (ii)
A first conductive layer portion is provided on the semiconductor substrate and extends in the width direction of the element region, facing the region between the source region and the drain region with an insulating film interposed therebetween; from one end side of the conductive layer part to one side in the length direction of the element region,
A gate electrode comprising a second conductive layer portion extending in one length direction of the element region to a length shorter than the source region when viewed from the side edge of the source region on the drain region side. only is formed,
and (iii) a region on the semiconductor substrate in which a wiring layer extends from an extended edge of the gate electrode of the source region to a side opposite to the drain region side, with an interlayer insulating layer interposed therebetween. facing each other and mutually extending in the width direction of the element formation region, and (iv) the wiring layer;
A region of the source region that extends from the extended edge of the gate electrode to the side opposite to the drain region is located at a position where they face each other,
They are connected to each other via contacts that cross the interlayer insulating layer.

According to the MIS transistor logic circuit configuration board according to the present invention having such a configuration, a programmable logic array, a read-only memory circuit, etc. can be mounted together with their peripheral circuits in a small and dense manner, and the resistance of the source region and drain region can be reduced. or,
It is possible to easily and flexibly configure a structure in which the resistance of the wiring layer is low and the wiring capacitance is small.

Embodiments of the Present Invention Next, embodiments of the MIS transistor logic circuit configuration substrate according to the present invention will be described.

FIG. 4 shows an embodiment of a substrate for configuring an MIS transistor logic circuit according to the present invention. When the semiconductor substrate 1 is divided into a large number of square or rectangular element regions Q, the main From the surface side, only the square or rectangular drain region D and the source region S, which has a width approximately equal to that of the drain region D and is longer than the drain region D, are connected to each other in the length direction of the source region S. The region Q is formed with a required inner distance maintained in the length direction of the element region Q.

Further, an insulating film (not shown) is provided on the semiconductor substrate 1.
A first conductive layer portion g1 extending in the width direction of the element region Q, facing the region between the source region S and the drain region D, and a first conductive layer portion g1 of the first conductive layer portion g1, From one end side, bend in one direction in the length direction of the element region Q, and extend the length shorter than the source region S in one direction in the length direction of the element region Q, as viewed from the side edge of the source region S on the drain region D side. A gate electrode G consisting of a second conductive layer portion g2 extending at
only is formed.

Furthermore, it has the configuration described below.

That is, as shown in FIG.
A first interlayer insulating film (not shown) is formed above the gate electrode G, and a source region S is formed on the first interlayer insulating film, facing the drain region D.
A wiring layer X1 extending to the outside of the element region Q in a direction perpendicular to the arrangement direction of the drain region D is formed. Further, a wiring layer X2 is formed on the first interlayer insulating film, facing the conductive layer portion g2 of the source region D and the gate electrode G, and extending parallel to the wiring layer X1 to the outside of the element region Q. ing. Further, on the first interlayer insulating film, the source region S faces the drain region D side in a region opposite to the wiring layer X1 and X2, and extends to the outside of the element region Q. Layer X3 is formed.

Further, a second interlayer insulating film (not shown) is formed on the first interlayer insulating film by burying the wiring layers X1, 2, and X3, and a wiring layer is formed on the second interlayer insulating film. A region not facing the drain region D of X1 and a region not facing the source region S of the wiring layer X3, and overlapping and facing the conductive layer portion g2 of the gate electrode G and the wiring layer X2. Thus, a wiring layer Y1 is formed which is perpendicular to the wiring layers X1, X2, and X3 and extends to outside the element region. Also,
A layer is formed on the second interlayer insulating film, overlapping and facing the wiring layer X1 and the drain region D, facing the conductive layer part g1 of the gate electrode G, and overlapping with the wiring layer X2 and the source region S. A wiring layer Y1 faces and overlaps and faces the wiring layer X3 and the source region S.
A wiring layer Y extending parallel to the element area Q to the outside of the element region Q
2 is formed.

Furthermore, the wiring layer X1 and the wiring layer Y1 are connected to a contact C1 extending through the second interlayer insulating film.
1. Further, the wiring layer X1 and the drain region D are connected by a contact C12 extending through the first interlayer insulating film. Further, the wiring layer X2 and the gate electrode G are connected in the conductive layer portion g2 of the gate electrode G by a contact C21 extending through the first interlayer insulating film. Furthermore, the wiring layer X2 and the wiring layer Y2 are connected by a contact C22 extending through the second interlayer insulating film. In addition, the wiring layer X3 and the source region S
are connected by a contact C32 extending through the first interlayer insulating film.

According to the above-described configuration, as shown in FIG.
Wiring layers X1 and X3 or wiring layers Y1 and X3
A logic circuit having a MIS transistor T accessed by the wiring layer X2 or the wiring layer Y2 is configured.

Further, as shown in FIG. 7, in the configuration shown in FIG. 5, the wiring layer Y2 is omitted, the contact C22 between the wiring layers X2 and Y2 is correspondingly omitted, and both ends of the wiring layer X1 are omitted. By having a configuration similar to that shown in FIG. 5 except that it does not extend outside the element area, as shown in FIG. 8, wiring layers Y1 and X3 and wiring layer A logic circuit having a MIS transistor T that is accessed is constructed.

Furthermore, as shown in FIG. 9, in the configuration shown in FIG. 5, the wiring layer Y1 is omitted, and accordingly, the contact C11 between the wiring layers X1 and Y1 is omitted.
is omitted, and both ends of the wiring layer X2 are connected to the element region Q.
10 by having a configuration similar to that shown in FIG. 5, except that it does not extend outwardly.
As shown in the figure, a logic circuit having a MIS transistor T accessed by wiring layers X1 and X3 and a wiring layer Y2 is configured.

Furthermore, as shown in FIG. 11, in the configuration shown in FIG. 5, both ends of the wiring layer X1 do not extend outside the element area, and the wiring layer Y2 overlaps the wiring layer X3 and the source region S. As shown in FIG. 12, the wiring layers Y1 and X3 have the same structure as that shown in FIG. accessed by wiring layer X2 or Y2
A logic circuit having an MIS transistor T is configured.

Further, as shown in FIG. 13, in the configuration shown in FIG. 5, both ends of the wiring layer
The wiring layer X of the wiring layer Y1 is not extended outward.
As shown in FIG. 14, the wiring layer Alternatively, a logic circuit having a MIS transistor T accessed by Y1, wiring layer X3, and wiring layer Y2 is configured.

As described above, according to the MIS transistor logic circuit configuration board according to the present invention, using it,
The present invention is characterized in that programmable logic arrays, read-only memories, and the like can be easily constructed with flexibility, compactness, and good characteristics.

Incidentally, for example, it is possible to easily construct a read-only memory circuit compactly and compactly, including a matrix arrangement using the MIS transistor logic circuit construction substrate having the configuration described above in FIGS. 7 and 8. can.

That is, as shown in FIG. 15, the wiring layer X2 on a plurality of rows is connected to an input buffer circuit IB supplied with an address decode output, which is known per se.
Further, the wiring layers Y1 on the plurality of columns are connected at one end to a precharge circuit (or pull-up circuit) F, which is known per se, and connected to an output buffer circuit OB at the other end. By connecting the row wiring layer X3 to the discharge circuit (or ground circuit) H, a dynamic (or static) read-only memory circuit can be easily constructed in a compact and compact manner.

Also, for example, programmable logic arrays can be easily, compactly and densely constructed, including matrix arrays using the configurations described above in FIGS. 7 and 8 and the configurations described above in FIGS. 9 and 10. Can be configured.

That is, as shown in FIG. 16, all or part of a desired line among multiple lines is
The remaining parts on the remaining rows have the configurations described above in FIGS. 9 and 10, and the wiring layer X having the configuration described above in FIGS. 7 and 8.
2, X3, and Y1 are connected to the input buffer circuit IB, discharge circuit (or ground circuit) H, and precharge circuit (or pull-up circuit) F, respectively, and the wiring layer having the configuration described above in FIGS. 9 and 10. Connect X1 to discharge circuit (or pull-up circuit) F' and output buffer circuit OB
The wiring layer X2 having the structure described above in FIGS. 9 and 10 is connected to the pull-up circuit (or discharge circuit) F'', and the wiring layer By connecting Y1 and the wiring layer Y2 having the configuration described above in FIGS. 9 and 10 via the wiring layer W, a dynamic type (or static type) programmable logic array circuit can be easily created. Moreover, it can be constructed compactly and densely.

Furthermore, a programmable logic array as shown in FIG. 17 can be configured including a matrix array using the configuration described above in FIGS. 11 and 12 and the configuration described above in FIGS. 13 and 14. I can do it.

That is, all or part of the required rows of the plurality of rows are configured as described above in FIGS. 11 and 12, and the remaining portions on the remaining rows are configured as shown in FIGS. 13 and 1.
4, and the wiring layers Y1, X3, and Y1, the input buffer circuit IB, the discharge circuit (or grounding circuit) H, and the precharge circuit (or pull-up circuit) having the configuration described above in FIGS. 11 and 12. ) F respectively,
In addition, the wiring layer Y1 having the configuration described above in FIGS. 13 and 14 is connected to the precharge circuit (or pull-up circuit) F' and the output buffer circuit OB, and the wiring layer Y1 having the configuration described above in FIGS. Connect layer X3 to the discharge circuit (or ground circuit H')
Furthermore, the wiring layer Y1 having the configuration described above in FIGS. 11 and 12 and the wiring layer Y2 having the configuration described above in FIGS. 13 and 14 are connected via the wiring layer W. Therefore, a dynamic type (or static type) programmable logic array plane can be easily constructed in a compact and dense manner.

Furthermore, as shown in FIG. 18, parts corresponding to those in FIG. 15 and FIG. 17 are given the same reference numerals, and detailed explanations are omitted. You can easily create logic circuits mixed with programmable logic arrays like the one shown below.
Moreover, it can be constructed compactly and densely.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of the main parts of a conventional MIS transistor logic circuit configuration substrate. Second
3 are a schematic plan view and a connection diagram showing the main parts of a logic circuit using the conventional MIS transistor logic circuit configuration substrate shown in FIG. 1. FIG. 4 is a schematic plan view showing essential parts of an example of a substrate for configuring an MIS transistor logic circuit according to the present invention.
5 and 6 are according to the invention shown in FIG.
FIG. 2 is a schematic plan view and a connection diagram showing essential parts of an example of a substrate for configuring an MIS transistor logic circuit, which is configured using the substrate for configuring an MIS transistor logic circuit and has a logic circuit. Figures 7 and 8; Figures 9 and 10; Figures 11 and 12; and Figure 1.
3 and 14 respectively show the main parts of other examples of the MIS transistor logic circuit configuration substrate having a logic circuit, which are constructed using the MIS transistor logic circuit configuration substrate according to the present invention shown in FIG. 4. FIG. 2 is a schematic plan view and a connection diagram shown in FIG. FIG. 15 is a systematic connection diagram showing an example of a read-only memory circuit using the MIS transistor logic circuit configuration substrate shown in FIGS. 7 and 8. FIG. Figure 16 shows the 7th
9 is a systematic connection diagram showing an example of a programmable logic array using the MIS transistor logic circuit configuration substrate shown in FIGS. 9 and 8 and the MIS transistor logic circuit configuration substrate shown in FIGS. 9 and 10. FIG. . Figure 17 is shown in Figures 11 and 12.
MIS transistor logic circuit configuration board and 13th
FIG. 15 is a systematic connection diagram showing another example of a programmable logic array using the MIS transistor logic circuit configuration board shown in FIG. FIG. 18 shows the read-only memory circuit shown in FIG. 15,
18 is a systematic connection diagram showing an example of a logic circuit in which the programmable logic array shown in FIG. 17 is mixed; FIG. 1... Semiconductor substrate, Q... Element region, S... Source region, D... Drain region, G... Gate electrode, g1, g2... Conductive layer portion, X, X1 to X3
...Wiring layer, Y, Y1, Y2...Wiring layer, C, C
11, C21, C12-C32...Contact,
T...MIS transistor, IB...I input buffer memory, OB...output buffer circuit, F, F',
F″……Pre-charge circuit or pull-up circuit,
H, H'...Destruction circuit or grounding circuit.

Claims (1)

[Claims] 1. When a semiconductor substrate is divided into a large number of square or rectangular element regions, within each element region,
From the main surface side, only a rectangular or rectangular drain region and a source region whose width is approximately equal to that of the drain region and whose length is longer than that of the drain region extend along the length direction of the source region. The region is formed with a required inner spacing in the length direction of the element region, and is formed on the semiconductor substrate, facing the region between the source region and the drain region with an insulating film interposed therebetween. hand,
A first conductive layer portion extending in the width direction of the element region; Only a gate electrode consisting of a second conductive layer portion extending shorter than the source region when viewed from the side edge of the source region on the drain region side is formed on one length direction of the gate electrode. and on the semiconductor substrate, a wiring layer is arranged to face a region extending from an extended edge of the gate electrode of the source region to a side opposite to the drain region side, with an interlayer insulating layer interposed therebetween. , extending mutually in the width direction of the element forming region, the wiring layer and a region extending from an extended edge of the gate electrode of the source region to a side opposite to the drain region. A substrate for configuring an MIS transistor logic circuit, characterized in that the transistors are connected to each other via contacts crossing the interlayer insulating layer at opposing positions.