JPH0519864B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a clamp circuit suitable for obtaining an accurate black level.

(Prior Art) Conventionally, when clamping a read signal in a video camera using a solid-state image sensor, for example, in order to obtain a stable optical black reference signal in each horizontal retrace period, A light shielding portion is often provided in the imaging cell corresponding to the back pouch.
This is due to the fact that the dark current, which is a factor in black level fluctuations in solid-state image sensors, approximately doubles when the element temperature rises by 8°C, and the general usage conditions for video cameras range from -10°C to +40°C. This is understandable considering that it extends to For the above purpose, in general, several to several tens of imaging cells corresponding to the back porch during the horizontal retrace period of a solid-state imaging device are shielded from light to form only the dark current, and the signal level in this portion is reduced. Clamping to a reference black level is performed. In this case, in order to perform a stable clamping operation, it is desirable that a large number of imaging cells be allocated to the light shielding section. However, if a large number of cells are used in the light-shielding part, there is a drawback that the resolution will further deteriorate in the current situation where the number of imaging cells is insufficient in the horizontal direction.

On the other hand, increasing the number of imaging cells within a limited size means increasing the area and increasing the integration of the device, which is a difficult problem unless there is significant improvement in process technology.

As a solution to this problem, video cameras that use an image pickup tube generally use a feedback clamp method, that is, a clamp circuit that clamps the level during the beam blanking period to a reference level using the black level, and this clamped signal. Consider a system consisting of a process circuit that performs γ correction after amplifying the signal, and in order to stabilize the output of this system, the process circuit output is compared with a predetermined reference level, and the above-mentioned A method of applying feedback to the clamp level has been considered.

However, when this method is particularly applied to a solid-state imaging device, noise during the blanking period is likely to enter the device because the output amplifier of the solid-state imaging device has a floating structure or the like.

Furthermore, in solid-state imaging devices, generally during the signal readout period, clock noise occurs due to capacitive coupling of the signal readout transfer pulse (approximately 1/3 of the saturation signal level). Therefore, if the potential of the light-shielding portion including the clock noise is detected, compared with a certain reference level, and clamped as in the conventional method, there is a problem that the video signal cannot be reproduced with sufficient precision.

As a means to solve this problem, a sample hold means for removing the above-mentioned clock noise may be provided before the feedback clamp.
However, when considering lower voltage and lower power consumption, even the sample and hold means generates command pulse clock noise of several tens of mV. On the other hand, as for the signal level, approximately 1/3 to 1/8 of the saturation signal output level of a solid-state image sensor is used as the standard operating level, but normally the saturation signal output level of a solid-state image sensor is several hundred mV, so the signal The level will be about 100 mV. Therefore, the ratio between this signal level and the clock noise mentioned above is about 20 dB, and in order to keep the black level stability (or low frequency conversion noise of clock noise) to about -50 dB or less, which is normally required for an imaging device, the feed must be adjusted. The performance of the back clamp circuit must be approximately -30dB or less.

Further, when the above-described solid-state imaging device is used as an electronic still camera for capturing still images, low power consumption and power start-up characteristics are required.
In other words, turn on the release switch (power switch)
At the same time, the electric circuit must have the ability to quickly process signals from the solid-state image sensor. To this end, it is desirable to avoid capacitive coupling in electrical circuits as much as possible and to connect them directly.

However, when trying to connect directly, the output amplifier of the solid-state image sensor is composed of a MOS amplifier.
Due to variations in MOS threshold voltage, a sample-and-hold device with a small dynamic range must be installed immediately after the solid-state image sensor.
The signal must then be amplified and configured to be input to the clamp circuit. In such a case, since clock noise is also amplified, the clamp circuit is required to have even higher potential stability.

(Objective) It is an object of the present invention to provide a clamp circuit that can eliminate the above-mentioned drawbacks.

In particular, the purpose is to provide a clamp circuit that can provide a stable black level.

(Example) The present invention will be described in detail below based on examples.

In the embodiment of the present invention, in order to eliminate the drawbacks of the prior art as described above, the light-shielding part signal is clamped with a clamp pulse as the first gate signal having a wide pulse width, and the black level detection circuit uses a clamp pulse as the first gate signal. This is intended to reduce the influence of clock noise by detecting the potential using a narrow pulse as the second gate signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed description of embodiments of the present invention will be given below with reference to the drawings.

FIG. 1 shows an example of the configuration of a solid-state image sensor applicable to the present invention, FIG. 2 is a block diagram showing an example of a signal processing system of the present invention, and FIG. 3 is a diagram showing waveforms of each part of FIG. 2. , FIG. 4 is a specific configuration diagram of the clamp circuit 4. As shown in FIG.

As is well known, solid-state image sensors can be broadly divided into
Although there are MOS type and CCD type, a case of a frame transfer type CCD will be explained as an embodiment of the present invention, and such a CCD is shown in FIG. 1st
As shown in the figure, the frame transfer type CCD consists of an imaging section PD, a storage section SD, a read register RR, and an on-chip preamplifier AD.
The imaging unit PD is provided with a light shielding unit OS that corresponds to a reference signal when clamping a signal.

In FIG. 2, 1 is a solid-state image sensor, 2 is a sample-and-hold circuit as a holding means of the present invention, and 3 is a solid-state image sensor.
4 is an amplifier, 4 is a clamp circuit, 5 is a signal processing circuit, and 6 is a synchronizing signal generating circuit as a signal generating means. In addition, in Fig. 4, 41 is a DC amplifier;
42 is a sample and hold circuit, 43 is an error amplifier, 44 is a clamper as a clamping means, C ₁ ,
_C2 is a capacitor, E is a reference power supply, and 45 is a clamp level forming circuit as a clamp level forming means.

The operation of the embodiment having the above configuration will be explained.

In FIG. 2, a driving pulse 6a from a synchronizing signal generating circuit 6 as an image sensor driving means of the present invention is shown.
The imaging unit PD of the solid-state imaging device 1 driven by
In this case, photoelectrons are generated by the incident light, and charges for one field period, for example, are accumulated by the action of a known potential well. The accumulated signal charge is transferred in parallel to the storage section SD during the vertical blanking period, and then transferred to the imaging section SD during the next field period.
In PD, charge is accumulated for the next field.

On the other hand, the signal charges in the storage section SD are transferred to the readout register RR horizontally one by one, and within one horizontal period, the signals of the black level period corresponding to the cells in the light shielding section OS are first read out, and then the signals in the image pickup section PD are read out. The image signal charges accumulated in are sequentially read out in time series.

Furthermore, in the present invention, even after reading one line of signals from the image pickup section PD, a blank read signal is obtained by supplying a drive pulse to the read register RR.

Although the dark current component in this blank read signal is relatively small, it can be regarded as being approximately the same as the dark current level of the light shielding part OS.

The PAM thus obtained (Pulse
Amplitude Modulation) signal is the solid line 1a in Figure 3.
This is shown schematically.

That is, in the PAM signal 1a, the part 101 is the light shielding part OS, the part 102 is the empty read period,
103 is a signal corresponding to the horizontal blanking period. These signals are converted into signals 2a in the third diagram by a sample/hold pulse 6b ( _6b1 is a sample, _6b2 is a hold) in the subsequent sample/hold circuit 2 shown in the third diagram. That is, the clock noise 2a' of the sample and hold device is superimposed on the signal 2a. The signal 2a is amplified to an appropriate signal level by an amplifier 3, and DC reproduction is performed in a clamp circuit 4. Here, the above-mentioned clamp circuit 4
For example, the configuration is as shown in FIG. 4, and the signal 3a passing through the amplifier 3 is connected to a coupling capacitor.
After passing through C ₁ , it is clamped to a certain potential charged in the capacitor C ₂ via the clamper 44 driven by the clamp pulse 6c-1 as the first gate signal in FIG. 3C. This clamped signal passes through a DC amplifier 41 and becomes an input signal 4a to a signal processing circuit 5 consisting of an encoder circuit, etc. However, the signal portion of the signal 4a during the black level period corresponding to the light-shielding portion OS is shown in FIG. 3B. Sample and hold pulse 6c-2 as second gate signal
The signal is sampled and held by a sample and hold circuit 42 driven by. Thereby, by detecting the optical reference signal and comparing and amplifying the detected signal and the reference voltage E in the error amplifier 43, a new clamp reference potential including the clamp error can be obtained, and this signal is applied to the clamper. 44, the video signal 3a is clamped in the direction of canceling the error.

Incidentally, the clamp pulse 6c- shown in FIG. 3A
1' is a pulse used to clamp the potential held by the sample-and-hold circuit 2 of the blank read signal, but in this case, since the clock noise 2a' is superimposed on the video signal 2a, the sample-and-hold circuit 4
When detecting the optical reference signal in step 2, clock noise 2a' is also detected, making it impossible to perform a stable clamping operation.

Therefore, in the embodiment of the present invention, as described above, the pulse 6c-1 having the timing shown in FIG. 3C is used as a clamp pulse. That is, the feature is that the clock noise of the light shielding section is removed by clamping the light shielding section 101 during the black level period.
Stable clamping operation can be achieved by removing clock noise in the light shielding section, detecting the black level by the sample and hold circuit 42, and performing feedback clamping. If the clamp pulse 6c-1 and the sample-hold pulse 6c-2 are identical and have the same phase, for example, B shown in the figure, the clamp operation will still not be stable. This is because in the clamper 44, the trailing end _B1 of the pulse is the most important. That is, when the rear end matches the clock noise in phase, clamping is performed at the potential of the clock noise, so even in the portion where the clock noise and the clamp pulse do not match in phase, the clock noise remains without being removed.
There is a possibility that the remaining clock noise will be detected by the sample and hold circuit 42. Also, in the sample-and-hold circuit 42, since the trailing edge _B2 of the pulse is important, the clamping capacitor _C1 and the clamper 44 are directly connected in the clamp circuit, and therefore the clamping time constant is small. Therefore, a resistor may be inserted here to increase the clamp time constant to form a soft clamp-like feedback clamp circuit. This is effective when the clock noise level is particularly high. Also, a sample hold pulse 6c-2 for black reference detection is used as a clamp pulse 6c-1 of the feedback clamp circuit.
It is also possible to use an appropriately delayed version.

(Effects) As explained above, stable clamping operation can be achieved by clamping the signal corresponding to the light shielding portion to remove clock noise and detecting the optical black reference signal within that period.

In addition, since there is no need to place a clock noise removal circuit in front of the clamp circuit as in the conventional case, there is no problem with pulse noise in the removal circuit, and the trailing edge of the clamp pulse is simply processed more temporally than the trailing edge of the black level detection sample and hold pulse. The configuration is very simple because it only requires a slight delay.

[Brief explanation of the drawing]

Figure 1 shows a frame transfer type CCD.
Figure 2 is a diagram showing an example of a signal processing system block.
FIG. 3 shows a waveform diagram of each part of FIG. 2, and FIG. 4 shows a configuration diagram of an example of a feedback type clamp circuit according to the present invention. 1 is a solid-state image sensor, 2 is a sample and hold circuit, 3 is an amplifier, 4 is a clamp circuit, 5 is a signal processing circuit, 6 is a synchronization signal generation circuit as a signal generation means, 41 is a DC amplifier, and 42 is a sample and hold circuit. , 43 is an error amplifier, 44 is a clamper as a clamping means, 45 is a clamp level forming circuit as a clamp level forming means, 6c-1
is the clamp pulse as the first gate signal, 6
c-2 is a sample hold pulse as a second gate signal.

Claims (1)

[Scope of Claims] 1. An imaging means having an optically shielded part in a part of a light receiving part that photoelectrically converts imaging light from a subject; and a black level signal outputted from the light shielding part of the imaging means to a predetermined value. clamping means for clamping to a reference level; level control means for controlling the reference level based on a signal obtained by sampling a black level signal after clamping; a first signal for setting the timing of clamping in the clamping means; signal generating means for outputting a second signal for setting the timing of sampling in the control means, at least a portion of the first signal and the second signal overlap, and a trailing edge of the second signal; An imaging means characterized in that the signal is preceded by a trailing edge of the first signal.