JPH0519982B2 - - Google Patents
Info
- Publication number
- JPH0519982B2 JPH0519982B2 JP61289341A JP28934186A JPH0519982B2 JP H0519982 B2 JPH0519982 B2 JP H0519982B2 JP 61289341 A JP61289341 A JP 61289341A JP 28934186 A JP28934186 A JP 28934186A JP H0519982 B2 JPH0519982 B2 JP H0519982B2
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- pad electrode
- slit
- lead
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07531—Techniques
- H10W72/07532—Compression bonding, e.g. thermocompression bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
Landscapes
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半導体集積回路装置に関し、特にアル
ミ・パツド電極の構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of an aluminum pad electrode.
(従来の技術)
従来、半導体集積回路装置のパツド電極にはア
ルミ材が多用され、また、半導体基板上では内部
アルミ配線群と隣接して設けられる。周知の通り
パツド電極は半導体集積回路装置の外部取出電極
であつて半導体基板の最上層に位置し組立ての際
この面上にボンデイング・ワイヤが熱圧着され
る。この熱圧着の際、アルミ・パツド電極および
内部アルミ配線との接続部を形成するアルミ引出
導体部はボンデイング応力の伝ぱん方向にそれぞ
れ伸長するので内部アルミ配線との接触を回避す
る必要上アルミ引出導体部は隣接する内部アルミ
配線と20〜30μm程度離間される。(Prior Art) Conventionally, pad electrodes of semiconductor integrated circuit devices are often made of aluminum, and are provided adjacent to internal aluminum wiring groups on a semiconductor substrate. As is well known, a pad electrode is an external electrode of a semiconductor integrated circuit device, and is located on the top layer of a semiconductor substrate, and a bonding wire is thermocompressed onto this surface during assembly. During this thermocompression bonding, the aluminum lead conductor parts that form the connections with the aluminum pad electrodes and the internal aluminum wiring expand in the direction of bonding stress propagation, so it is necessary to avoid contact with the internal aluminum wiring. The conductor portion is separated from the adjacent internal aluminum wiring by about 20 to 30 μm.
(発明が解決しようとする問題点)
しかしながら、微細加工技術が進み半導体装置
の高密度化および高速化が今日のように進展して
来ると、能動素子を含む電子回路の縮小化の達成
度に比べアルミ・パツド電極周辺の遅れが目立つ
ようになりその対策が望まれている。すなわち、
通常の内部アルミ配線の相互間距離が僅か3〜
4μmにすぎないのにパツド電極の離間距離がその
10倍にも達していることが注目され始めておりこ
の縮小化が望まれている。(Problems to be Solved by the Invention) However, as microfabrication technology progresses and semiconductor devices become more dense and faster than they are today, the degree of miniaturization of electronic circuits including active elements is becoming increasingly difficult. In comparison, delays around aluminum pad electrodes have become more noticeable, and countermeasures are desired. That is,
The distance between normal internal aluminum wiring is only 3 ~
Even though it is only 4 μm, the distance between the pad electrodes is
It is beginning to be noticed that the size has reached 10 times, and reduction of this size is desired.
本発明の目的は、上記の情況に鑑み、隣接する
内部アルミ配線との離間距離を縮小化し得るアル
ミ・パツド電極構造を備えた半導体集積回路装置
を提供することである。
SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device having an aluminum pad electrode structure capable of reducing the distance between adjacent internal aluminum wiring lines.
〔発明の構成〕
本発明によれば、半導体集積回路装置は、半導
体基板と、前記半導体基板のフイールド絶縁膜上
に互いに隣接して形成されるアルミ・パツド電極
および内部アルミ配線群と、前記内部アルミ配線
群の少なくとも一つと電気接続されるアルミ・パ
ツド電極のアルミ引出導体部と、前記アルミ・パ
ツド電極および或いはアルミ引出導体部の面上に
ボンデイング応力の伝ぱん方向と対面する向きに
それぞれ配設されるスリツト状の貫通孔とを備え
ることを含む。[Structure of the Invention] According to the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, an aluminum pad electrode and an internal aluminum wiring group formed adjacent to each other on a field insulating film of the semiconductor substrate, and an aluminum lead-out conductor portion of an aluminum pad electrode electrically connected to at least one of the aluminum wiring groups; and a slit-like through hole provided therein.
すなわち、本発明によれば、アルミ・パツド電
極およびアルミ引出導体部の何れか一方または両
方の面上にスリツト状の貫通孔がボンデイングの
際発生する応力の伝ぱん方向と対面する向きにそ
れぞれ配設される。具体的にはこれらの貫通孔は
アルミ引出導体部上では隣接する内部アルミ配線
群と平行に、また、アルミ・パツド電極上ではア
ルミ引出導体部と対向する縁端面の一部または電
極面の縁端部を通る円周に沿つて円周状に配設さ
れる。
That is, according to the present invention, slit-shaped through holes are arranged on either or both surfaces of the aluminum pad electrode and the aluminum lead-out conductor portion in a direction facing the propagation direction of stress generated during bonding. will be established. Specifically, these through holes are placed parallel to the adjacent internal aluminum wiring group on the aluminum lead conductor, and on a part of the edge surface facing the aluminum lead conductor or the edge of the electrode surface on the aluminum pad electrode. They are arranged circumferentially along the circumference passing through the end.
ここで、配設されたスリツト状の貫通孔はアル
ミ・パツド電極またはアルミ引出導体部の面上を
伝ぱんするボンデイング応力を受けて変形しこれ
を吸収してパツド電極全体の伸長を緩和するよう
作用する。従つて、アルミ引出導体部と隣接する
内部アルミ配線との離間距離は従来の1/2〜1/3に
縮小される。この際、配設する貫通孔の形状は矩
形に限らず円形、だ円形その他任意の形に設定す
ることも可能である。以下図面を参照して本発明
を詳細に説明する。
Here, the provided slit-shaped through-hole deforms in response to the bonding stress that propagates on the surface of the aluminum pad electrode or the aluminum lead conductor, absorbing this stress, and relaxing the expansion of the entire pad electrode. act. Therefore, the distance between the aluminum lead-out conductor and the adjacent internal aluminum wiring is reduced to 1/2 to 1/3 of the conventional one. At this time, the shape of the through hole to be provided is not limited to a rectangular shape, but can also be set to a circular shape, an oval shape, or any other arbitrary shape. The present invention will be described in detail below with reference to the drawings.
第1図aおよびbは本発明の一実施例を示すア
ルミ・パツド電極近傍の平面図およびそのA−
A′断面図である。本実施例によれば、本発明の
半導体集積回路装置は、半導体基板1と、このフ
イールド絶縁膜2上に互いに隣接して形成される
アルミ・パツド電極3および内部アルミ配線群4
と、内部アルミ配線の一つと電気接続されるアル
ミ・パツド電極のアルミ引出導体部5と、このア
ルミ引出導体部5の面上に内部アルミ配線群4と
平行に配設されたスリツト状の貫通孔6と、アル
ミ・パツド電極の絶縁保護膜7とを含む。
Figures 1a and 1b are plan views of the vicinity of aluminum pad electrodes showing one embodiment of the present invention, and their A-
It is an A′ cross-sectional view. According to this embodiment, the semiconductor integrated circuit device of the present invention includes a semiconductor substrate 1, an aluminum pad electrode 3 formed adjacent to each other on the field insulating film 2, and an internal aluminum wiring group 4.
, an aluminum lead-out conductor part 5 of an aluminum pad electrode electrically connected to one of the internal aluminum wirings, and a slit-shaped penetration arranged parallel to the internal aluminum wiring group 4 on the surface of this aluminum lead-out conductor part 5. It includes a hole 6 and an insulating protective film 7 for the aluminum pad electrode.
本実施例によれば、アルミ・パツド電極3上に
ボンデイング・ワイヤが熱圧着された際生じるボ
ンデイング応力の一部はアルミ引出導体部5上を
内部アルミ配線群4と直角方向に伝ぱんするがこ
の勢力はスリツト状の貫通孔6を変形することに
よつて消費される。従つて、アルミ引出導体部5
の横軸方向の伸長は著しく緩和されるので隣接す
る内部アルミ配線との離間距離Lを従来の1/2〜
1/3に縮小化し得る。 According to this embodiment, a part of the bonding stress generated when the bonding wire is thermocompressed onto the aluminum pad electrode 3 is propagated on the aluminum lead conductor portion 5 in a direction perpendicular to the internal aluminum wiring group 4. This force is consumed by deforming the slit-like through hole 6. Therefore, the aluminum lead-out conductor portion 5
Since the elongation in the horizontal axis direction of
It can be reduced to 1/3.
第2図aおよびbは本発明にかかるスリツト状
貫通孔のボンデイング応力吸収状況図でボンデイ
ング工程の開始前および終了後にそれぞれ対応し
ており、スリツト状の貫通孔5が応力を吸収した
際変形する様子を示したものである。 Figures 2a and 2b are diagrams showing how the slit-shaped through-hole absorbs stress during bonding according to the present invention, which correspond to before and after the bonding process, respectively, and show that the slit-shaped through-hole 5 deforms when absorbing stress. This shows the situation.
第3図および第4図は本発明の他の実施例をそ
れぞれ示すアルミ・パツド電極近傍の平面図であ
る。これら2つの実施例図には絶縁保護膜7が省
略された以外は全て前実施例と共通符号が付され
ている。ここで、スリツト状の貫通孔6は第3図
の実施例ではアルミ引出導体5と対向する位置の
アルミ・パツド電極の縁端面上に形成され、また
第4図の実施例ではアルミ引出導体5の面上と共
にアルミ・パツド電極3の縁端面に対して円周状
にそれぞれ配設される。この場合、何れの実施例
においてもスリツト状貫通孔6はボンデイング応
力を有効に吸収してアルミ・パツド電極全体の伸
長を著しく緩和し得る。特に第4図の実施例の如
くパツド電極および引出導体部の両方に配設する
とその伸長緩和効果はより一層顕著となる。 3 and 4 are plan views of the vicinity of aluminum pad electrodes showing other embodiments of the present invention, respectively. These two embodiment drawings have the same reference numerals as those of the previous embodiment except that the insulating protective film 7 is omitted. Here, in the embodiment shown in FIG. 3, the slit-shaped through hole 6 is formed on the edge surface of the aluminum pad electrode at a position facing the aluminum lead-out conductor 5, and in the embodiment shown in FIG. They are arranged circumferentially on the surface of the aluminum pad electrode 3 as well as on the edge surface of the aluminum pad electrode 3. In this case, in any of the embodiments, the slit-like through hole 6 can effectively absorb the bonding stress and significantly reduce the elongation of the entire aluminum pad electrode. Particularly, when it is provided in both the pad electrode and the lead-out conductor portion as in the embodiment shown in FIG. 4, the elongation relaxation effect becomes even more remarkable.
以上の実施例はもちろん本発明の単なる例示に
すぎないので、スリツト状貫通孔6の形状、配設
の仕方および組合せの選択は個々の半導体装置に
合わせ適宜決定することが可能である。また、ア
ルミ引出導体部5の大きさを多少広げる必要が生
じるが内部アルミ配線群4との離間距離Lの縮小
化には全く関係をもたないので特に問題となるこ
とはない。 Of course, the above embodiments are merely illustrative of the present invention, and the shape, arrangement, and combination of the slit-like through holes 6 can be appropriately determined in accordance with each individual semiconductor device. Further, although it becomes necessary to increase the size of the aluminum lead-out conductor portion 5 to some extent, this does not cause any particular problem since it has no relation to the reduction of the distance L from the internal aluminum wiring group 4.
以上詳細に説明したように、本発明によれば、
アルミ・パツド電極のボンデイング面およびアル
ミ引出導体部の何れか一方または両方にスリツト
状の貫通孔を配設することによりボンデイングの
際生じる機械的応力を吸収してアルミ・パツド電
極全体の伸長を有効に緩和し得るので、アルミ・
パツド電極とこれに隣接配置される内部アルミ配
線群との離間距離を従来の1/2〜1/3に短縮せしめ
得る。すなわち、電子回路の微細化技術と相俟つ
てパツド電極周辺の縮小化も達成することができ
るので集積度の向上に顕著なる効果を奏し得る。
As explained in detail above, according to the present invention,
By providing a slit-shaped through hole on either or both of the bonding surface of the aluminum pad electrode and the aluminum lead-out conductor, the mechanical stress generated during bonding is absorbed and the entire aluminum pad electrode is expanded. Aluminum and
The distance between the pad electrode and the internal aluminum wiring group disposed adjacent thereto can be reduced to 1/2 to 1/3 of the conventional distance. That is, in conjunction with electronic circuit miniaturization technology, it is also possible to reduce the area around the pad electrode, which can have a significant effect on improving the degree of integration.
第1図aおよびbは本発明の一実施例を示すア
ルミ・パツド電極近傍の平面図およびそのA−
A′断面図、第2図aおよびbは本発明にかかる
スリツト状貫通孔のボンデイング応力吸収状況
図、第3図および第4図は本発明の他の実施例を
示すアルミ・パツド電極近傍の平面図である。
1……半導体基板、2……フイールド絶縁膜、
3……アルミ・パツド電極、4……内部アルミ配
線群、5……アルミ引出導体部、6……スリツト
状の貫通孔、7……絶縁保護膜、L……離間距
離。
Figures 1a and 1b are plan views of the vicinity of aluminum pad electrodes showing one embodiment of the present invention, and their A-
A′ sectional view, FIGS. 2a and b are diagrams of bonding stress absorption state of the slit-like through hole according to the present invention, and FIGS. 3 and 4 are diagrams showing other embodiments of the present invention near the aluminum pad electrode. FIG. 1... Semiconductor substrate, 2... Field insulating film,
3... Aluminum pad electrode, 4... Internal aluminum wiring group, 5... Aluminum lead-out conductor portion, 6... Slit-shaped through hole, 7... Insulating protective film, L... Separation distance.
Claims (1)
絶縁膜上に互いに隣接して形成されるアルミ・パ
ツド電極および内部アルミ配線群と、前記内部ア
ルミ配線群の少なくとも一つと電気接続されるア
ルミ・パツド電極のアルミ引出導体部と、前記ア
ルミ・パツド電極および或いはアルミ引出導体部
の面上にボンデイング応力の伝ぱん方向と対面す
る向きにそれぞれ配設されるスリツト状の貫通孔
とを備えることを特徴とする半導体集積回路装
置。 2 前記スリツト状の貫通孔が前記アルミ引出導
体部面上に内部アルミ配線群と平行して配設され
ることを特徴とする特許請求の範囲第1項記載の
半導体集積回路装置。 3 前記スリツト状の貫通孔が前記アルミ・パツ
ド電極の縁端面上にアルミ引出導体部と対向して
配設されることを特徴とする特許請求の範囲第1
項記載の半導体集積回路装置。 4 前記スリツト状の貫通孔が前記アルミ・パツ
ド電極の縁端面上に円周状に配設されることを特
徴とする特許請求の範囲第1項記載の半導体集積
回路装置。[Scope of Claims] 1. A semiconductor substrate, an aluminum pad electrode and an internal aluminum wiring group formed adjacent to each other on a field insulating film of the semiconductor substrate, and electrically connected to at least one of the internal aluminum wiring group. an aluminum lead-out conductor portion of the aluminum pad electrode, and slit-shaped through holes arranged on the surface of the aluminum pad electrode and/or the aluminum lead-out conductor portion in a direction facing the bonding stress propagation direction. A semiconductor integrated circuit device comprising: 2. The semiconductor integrated circuit device according to claim 1, wherein the slit-shaped through hole is arranged on the surface of the aluminum lead-out conductor portion in parallel with the internal aluminum wiring group. 3. Claim 1, characterized in that the slit-shaped through hole is arranged on the edge surface of the aluminum pad electrode, facing the aluminum lead-out conductor part.
The semiconductor integrated circuit device described in . 4. The semiconductor integrated circuit device according to claim 1, wherein the slit-like through holes are arranged circumferentially on the edge surface of the aluminum pad electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61289341A JPS63141330A (en) | 1986-12-03 | 1986-12-03 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61289341A JPS63141330A (en) | 1986-12-03 | 1986-12-03 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63141330A JPS63141330A (en) | 1988-06-13 |
| JPH0519982B2 true JPH0519982B2 (en) | 1993-03-18 |
Family
ID=17741946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61289341A Granted JPS63141330A (en) | 1986-12-03 | 1986-12-03 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63141330A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0170316B1 (en) * | 1995-07-13 | 1999-02-01 | 김광호 | Pad design method of semiconductor device |
| WO2006046302A1 (en) * | 2004-10-29 | 2006-05-04 | Spansion Llc | Semiconductor device and manufacturing method therefor |
| JP4533804B2 (en) | 2005-06-02 | 2010-09-01 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
| JP5017872B2 (en) * | 2006-02-06 | 2012-09-05 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| KR100903696B1 (en) * | 2007-05-22 | 2009-06-18 | 스펜션 엘엘씨 | Semiconductor device and manufacturing method thereof |
| JP2009111073A (en) * | 2007-10-29 | 2009-05-21 | Elpida Memory Inc | Semiconductor device |
| EP2648212B1 (en) * | 2010-11-29 | 2019-07-03 | Toyota Jidosha Kabushiki Kaisha | A bonding wire bonded to an upper surface electrode with a slit |
| JP5922331B2 (en) * | 2011-02-02 | 2016-05-24 | ラピスセミコンダクタ株式会社 | Wiring structure of semiconductor device and manufacturing method thereof |
| JP5806137B2 (en) * | 2012-01-27 | 2015-11-10 | 京セラ株式会社 | Wiring board and electronic device |
-
1986
- 1986-12-03 JP JP61289341A patent/JPS63141330A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63141330A (en) | 1988-06-13 |
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