JPH0520772B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a circuit for performing arithmetic processing on signals expressed as digital values, such as acoustic signals.

BACKGROUND TECHNOLOGY When processing acoustic signals expressed as digital values, transients such as when switching algorithms such as bass enhancement or treble enhancement, when power is turned on, when changing coefficients, or when switching input sources, etc. During this period, discontinuous points may occur in the signal due to processing switching, and abnormal sounds such as pop noise may be superimposed on the acoustic signal. For this reason, typical prior art techniques include storing memory in signal processing circuits such that the level of the acoustic signal, represented by a digital value, is changed gradually over time rather than abruptly. A counter as shown in Fig. 4 is provided in the area, and when switching the processing as described above, the count value is sequentially incremented or decremented within a predetermined range according to the operation shown in Fig. 5. , the acoustic signal is multiplied as a coefficient to realize a muting operation that suppresses the occurrence of abnormal noise.

In other words, moving from step n1 to step n2,
The increment A (including the negative area) is added to the count value C of the clip counter, and the count value C is updated. At step n3, the updated count value C
It is determined whether C exceeds the maximum value MAX, and if not, that is, if it is less than the maximum value MAX, the process moves to step n4 and the count value C is
It is determined whether is less than the minimum value MIN,
If not, that is, the count value C is the minimum value
If it is greater than or equal to MIN, the process moves to step n5 and the operation ends.

At step n3, count value C reaches the maximum value
If it exceeds MAX, move to step n6,
Assign the maximum value MAX to the count value C and step
Move to n5.

At step n4, count value C is the minimum value
If it is less than MIN, proceed to step n7, substitute the minimum value MIN to count value C, and proceed to step n5.
Move to. By repeating such operations, for example, by making the increment A positive, the level of the acoustic signal can be gradually increased over time, thereby suppressing the occurrence of abnormal noise when the power is turned on. I can do it.

Problems to be Solved by the Invention In the prior art as described above, in order to perform the muting operation, the signal processing circuit must perform calculations for the muting operation in addition to the original audio signal processing such as tone control. Must be. Therefore, for calculations for this muting operation, for example, address is specified, count value C and increment A are read out, and after calculation processing,
Since it requires many program steps such as comparing the processing result with the maximum value MAX and minimum value MIN, it is difficult to realize the muting operation by software. This is disadvantageous for real-time processing of acoustic signals, which must be performed.

An object of the present invention is to provide a signal processing device that can improve the processing speed when processing an input signal such as an acoustic signal sequentially over time.

Means for Solving the Problems The present invention provides: a processing circuit that performs processing such as arithmetic processing and delay processing on digital data; a data memory that stores coefficients used in the processing of the processing circuit; and the data memory. an arithmetic circuit that updates the value of a coefficient stored in the arithmetic circuit, the arithmetic circuit comprising: a register that stores initial data or a calculation result used in the calculation; and an increment or decrement register that stores an increment per one addition operation. an adder; a maximum value register that stores the maximum value of the adder; a minimum value register that stores the minimum value of the adder; and an adder that stores the addition result of the adder and the maximum value or the minimum value, respectively. a comparing means for comparing; and controlling the addition operation of the adder, and when the addition result exceeds the maximum value or becomes less than the minimum value, the addition result of the adder is adjusted to the above-mentioned by the output from each of the comparison means. control means for setting the value to the maximum value or the minimum value, and updating the value of the coefficient used in the processing of the processing circuit by transferring the calculation result of the calculation circuit to the data memory as a coefficient. This is a signal processing device characterized by:

Effects According to the present invention, in connection with a processing circuit that performs processing such as arithmetic processing and delay processing on digital data such as an acoustic signal using coefficients stored in the data memory, An arithmetic circuit is provided to update the contents.
In the arithmetic circuit, the initial data used for the arithmetic operation or the stored contents of the register that stores the arithmetic result are updated by adding the increment per one addition operation stored in the increment or decrement register in an adder. . The addition result of the adder is given to the comparison means, and this comparison means also receives the maximum value, which is the upper limit value for the adder to perform the addition operation, from the maximum value register, and the maximum value from the minimum value register. A minimum value, which is a lower limit value, is given, and the comparison means compares the addition result with the maximum value and the minimum value, respectively, and determines when the addition result exceeds the maximum value or is less than the minimum value. At times, the output is derived to the control means, and the addition result of the adder is set to the maximum value or the minimum value. Then, the calculation results of the calculation circuit are transferred to a data memory and stored as coefficients, and the processing circuit uses the coefficients to perform processing such as the calculation processing and delay processing.

Therefore, for example, by using the coefficients that are sequentially updated within the range from the minimum value of 0 to the maximum value of 1 by the arithmetic circuit, the processing circuit can process the digital data such that the coefficients are used for acoustic signal processing. When used for this purpose, adjust the volume, etc. Therefore, since the coefficients for signal processing are changed by the arithmetic circuit according to the present invention provided outside the signal processing circuit, the processing circuit does not need a processing operation to change the coefficients. Therefore, the signal processing speed can be improved.

Embodiment FIG. 1 is a block diagram of an arithmetic circuit 1 according to an embodiment of the present invention, and FIG. 2 is a block diagram of an acoustic signal processing device 2 in which the arithmetic circuit 1 is used. For example, an analog audio signal from a radio receiver or the like is input from an input terminal 3 to an analog/digital converter 4.
is given to the data bus 5, converted into digital data, and
The signal is applied to the processing circuit 6 via. In the processing circuit 6, arithmetic processing such as tone control and delay processing are performed, and the thus processed acoustic signal is given from the data bus 5 to the digital/analog converter 7, converted into analog, and sent to the output terminal 8. It is applied to a connected power amplifier circuit, for example.

The coefficients used in the arithmetic processing in the processing circuit 6 as described above are stored in the data memory 9, and the stored contents of the data memory 9 are read out via the data buses 10 and 5 and used as the coefficients. The stored contents of data memory 9 are as follows:
The calculation result of the calculation circuit 1 is given and updated.
That is, the arithmetic circuit 1 derives a signal to the program memory 12 via the line 11, and transmits the processing procedure of the arithmetic operation stored in the program memory 12 to the program buses 13, 14 and the line 1.
5. According to the procedure thus read, the arithmetic circuit 1 derives a signal to the data memory 9 via the line 16, and the stored contents of the data memory 9 are read via the data buses 10, 5, 17, as will be described later. After the calculation operation is performed, the data is applied to the data memory 9 via the data buses 17, 5, and 10, and the stored contents of the data memory 9 are updated.

The arithmetic circuit 1 includes an adder 21 and this adder 21
a maximum value register 22 that stores the maximum value X of
A minimum value register 23 that stores the minimum value Y, and comparators 24 and 25 that compare the maximum value X and the minimum value Y with the maximum addition M of the adder 21, respectively.
, an increment register 26 that stores an increment Δ1 for each addition operation, a decrement register 27 that stores a decrement Δ2 for each addition operation, and an adder 2.
1, an instruction decoder 29 that decodes the program representing the processing procedure of the addition operation from the program memory 12, and the adder 21 according to the program via the instruction decoder 29. It is configured to include a control circuit 30 for controlling.

When the adder 21 performs an addition operation, the stored contents of the data memory 9 are first read out via the data buses 10, 5, and 17a, and stored in the register 28.
Initial settings are made. Next, the increment Δ1 per one addition operation is input from the processing circuit 6 to the increment register 26 via the data buses 5 and 17b, and similarly, the increment Δ1 per addition operation is input to the increment register 26 via the data buses 5 and 17c.
Decrement △2 is input to 7. Furthermore, the maximum value X of the addition operation is input from the processing circuit 6 to the maximum value register 22 via the data buses 5 and 17d, and similarly to the minimum value register 23 via the data buses 5 and 17e.
The minimum value Y is input to .

When the initial setting is completed in this manner, the processing procedure for the addition operation is read out from the program memory 12 by the signal derived from the control circuit 30 to the line 11 as described above, and is decoded by the instruction decoder 29 to be outputted to the control circuit. given to 30.

Control circuit 30 controls the addition operation of adder 21 based on the outputs from comparators 24 and 25 input via lines 34 and 35. Adder 21
reads out the stored content B of the register 28 via the data bus 36 based on a control signal from the control circuit 30, and reads out the increment Δ from the increment register 26 or the decrement register 27 via the data bus 37.
1 or the decrement Δ2 is read out and the addition result M is transferred to the register 28 via the data bus 38, thus updating the stored content B of the register 28.

Store contents B of register 28 are also provided to comparators 24 and 25, respectively, via data bus 39. The comparator 24 is supplied with the maximum value X for the adder 21 to perform the addition operation from the maximum value register 22 via the data bus 40, and similarly, the comparator 25 is supplied with the minimum value X via the data bus 41. The minimum value Y is given from the value register 23. Comparator 2
4 derives a signal to the line 34 to stop the addition operation when the stored content B of the register 28, that is, the addition result of the adder 21 becomes larger than the maximum value A signal for stopping the addition operation is derived on line 35 when the value becomes smaller than the minimum value Y. In this way, when the addition result M exceeds the maximum value X or becomes smaller than the minimum value Y, the maximum value X or minimum value Y via the data buses 42 and 43 is assigned to the stored content B of the register 28. Ru.

FIG. 3 is a flowchart for explaining the operation. In step m1, initial settings are performed as described above. That is, data memory 9
The stored content B of is read out to the register 28, and an increment Δ1 and a decrement Δ2 are given to the increment register 26 and the decrement register 27, respectively, from the processing circuit 6. Also, at this time, the maximum value register 22 and the minimum value register 23 contain the addition result M of the adder 21.
A maximum value X and a minimum value Y are set.

At step m2, the arithmetic instruction decoded by the instruction decoder 29 is taken in. step
At step m3, the store contents B of the register 28 and the increment .DELTA.1 or the decrement .DELTA.2 are read out to the adder 21, and an addition operation is performed at step m4. step m5
Then, the addition result M is given to the register 28, and the comparator 24,
25 each.

In step m6, it is determined whether the addition result M exceeds the maximum value X or is smaller than the minimum value Y, and if so, the process moves to step m7.
The maximum value X or the minimum value Y is stored in the register 28, and the process returns to step m2. At step m6, when the addition result M is within the range from the maximum value X to the minimum value Y, the process directly returns to step m2.

As described above, by providing the present calculation circuit 1 in the acoustic signal processing device 2 and using the calculation result as a coefficient for acoustic signal processing, the processing circuit 6 only performs the original processing operation of the acoustic signal. Therefore, the speed of audio signal processing can be improved, or the quality of audio signal processing can be improved.

Effects As described above, according to the present invention, in the arithmetic circuit,
Since the calculation operation is performed by hardware using the adder, the calculation speed can be improved. Furthermore, when the addition result of the adder is used, for example, as a coefficient for audio signal processing, the audio signal processing circuit does not need to perform a processing operation to change the coefficient, and the signal processing speed can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an arithmetic circuit 1 according to an embodiment of the present invention, FIG. 2 is a block diagram of an acoustic signal processing device 2 in which the arithmetic circuit 1 shown in FIG. 1 is used, and FIG. 3 shows the operation. FIG. 4 is a diagram showing a memory storage area in a signal processing circuit to explain the prior art, and FIG. 5 is a flow chart to explain the operation of the prior art. DESCRIPTION OF SYMBOLS 1... Arithmetic circuit, 2... Acoustic signal processing device, 6... Processing circuit, 9... Data memory, 12... Program memory, 21... Adder, 22... Maximum value register, 2
3...Minimum value register, 24, 25...Comparator, 26
...Increment register, 27...Decrement register, 28...Register, 29...Instruction decoder, 30...Control circuit.

Claims (1)

[Scope of Claims] 1. A processing circuit 6 that performs processing such as arithmetic processing and delay processing on digital data; a data memory 9 that stores coefficients used in the processing of the processing circuit 6; The arithmetic circuit 1 includes: a register 28 that stores initial data or the arithmetic result used in the arithmetic operation; and a register 28 that stores increments △1 and △2 per one addition operation. an adder 21; a maximum value register 22 for storing the maximum value of the adder 21; and a minimum value register 23 for storing the minimum value of the adder 21; Comparing means 24, 25 for comparing the addition result of the unit 21 with the maximum value or the minimum value, respectively.
and controlling the addition operation of the adder 21, and when the addition result exceeds the maximum value or becomes less than the minimum value, the addition result of the adder is adjusted to the maximum value or the minimum value according to the output from each of the comparison means. and a control means 30 for setting the value to the minimum value, and updating the value of the coefficient used in the processing of the processing circuit 6 by transferring the calculation result of the calculation circuit 1 to the data memory 9 as a coefficient. A signal processing device characterized by: