JPH0520785B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an inter-processor data transfer device of a parallel processing system that combines a large number of processors, and particularly relates to an inter-processor data transfer device that is provided corresponding to each processor. The present invention relates to an inter-processor data transfer device that transfers data by circulating data among the slots.

(Prior Art) A parallel processing system composed of a large number of processors is basically constructed by coupling processors 1a, 1b, 1c, ..., 1n by a coupling means 2, as shown in FIG. . Each processor 1a to 1n
transfer data to each other via the coupling means 2.

Incidentally, the coupling means 2 can be realized by using various means such as a common bus such as a shared memory, but one of them is to transmit data packets to a data transfer path 3 connected in a circular manner as shown in FIG. A method for high-speed circulation is known. That is, this method is
Slots Sa, Sb, Sc, ..., Sn for storing data packets to be transferred are provided for each processor 1a to 1n.
Each processor 1a-1n stores the data to be transmitted in the corresponding slot Sa-Sn.
Then, connect these slots Sa to Sn to each processor 1.
The slots are circulated at high speed by slot control devices 5a to 5n provided corresponding to slots a to 1n.

In this system, the data packets stored in each slot Sa to Sn usually have a configuration as shown in FIG. The data to be transferred is written in the DATA section 21, the transfer destination processor number is written in the PN section 22, the response signal from the transfer destination processor is written in the A section 23, and the V section 24
Information indicating that data is stored in the DATA section 21 is written in . A processor that transfers data writes the data to be transferred into the DATA section 21 of the slot corresponding to the processor, and
Write the transfer destination processor number in the PN section 22, and
24 is set to 1. This slot eventually reaches the destination processor through circulation. When the receiving processor receives the data in the slot when the PN section 22 matches its own processor number, it sets the A section 23 to 1 as a response signal. This slot is then cycled back to the sender's processor. The sender's processor confirms that the A part 23 of the slot is 1, that is, that the other party's processor has received the data.

As described above, data transfer is performed using this slot information. In order to realize this slot circulation system, a slot control device (hereinafter referred to as "SE") as shown in FIG. 11 is constructed using an LSI, and these are connected in a ring.
This SE has an input buffer 31 that receives information from other SEs from outside the LSI and takes it into the LSI, an input register 32 that holds the input, and uses the contents of the input register 32 as information on the slot at that time. The slot processing unit 33 performs the processing described in
and an output buffer 34 that outputs the results processed by the slot processing section 33 to the outside of the LSI.

In this coupling method, if the number of processors is n, and the time interval when the processors send data is p, then the time it takes for the slot to move between processors is s.
must satisfy s≦p/n. Therefore, as the number of processors connected to the coupling means increases, and as the required data transfer rate between processors becomes faster (as the time interval p becomes shorter), it becomes necessary to cycle through the slots at a faster rate. For example, if there are 10 processors and each processor transfers 1 data every 200ns,
It is sufficient to cycle each slot between processors every 200/10 = 20ns, but if the number of processors increases to 40, or if it is necessary to transfer one data every 50ns, it is necessary to cycle between the processors every 5ns. The processor must be cycled through.

Therefore, in such a case, it is necessary to use a high-speed element LSI. However, although this high-speed element is also high-speed inside the package, the signal going out to the outside of the package passes through an input/output buffer, so it cannot be made that high-speed. Also, this number
When the speed reaches approximately ns, the propagation delay due to the wiring length between the slot control devices cannot be ignored. For example, assuming that the speed of the input/output buffer is 1 ns and the wiring length of the slot control element is 30 cm (in this case, the delay is about 2 ns), as shown in Figure 12,
The delay due to input/output buffer and wiring is 4ns,
In order to cycle the processors every 5 ns, the transfer control process described above must be performed in the remaining 1 ns, which is virtually impossible. Furthermore, even if an element that enables ultra-high-speed processing is created, the first
As shown in Figure 2, only 1 ns is used for processing, resulting in extremely low processing efficiency.
From the above, with the conventional method of circulating slots, even if high-speed element LSIs are used, the circulation speed cannot be increased due to input/output buffers and wiring delays, and there are limits to the number of processors and data transfer speed. . Furthermore, even when ultra-high-speed element LSIs are used, there is a problem in that the ratio of slot processing time to the total transfer processing time between slots is extremely low, resulting in poor efficiency.

(Problems to be Solved by the Invention) As described above, in the conventional inter-processor data transfer device using the method of circulating slots, it is difficult to increase the circulation speed due to delays in input/output buffers, wiring between processors, etc. Therefore, it was not possible to increase the number of processors or increase the data transfer speed.
Furthermore, even if this was achieved using an ultra-high-speed element LSI, the processing efficiency would be extremely poor.

The present invention has been made in view of the above problems, and its purpose is to provide an inter-processor data transfer device that increases the circulation speed of slots and makes it possible to increase the number of processors and data transfer speed. There is a particular thing. Another object of the present invention is to provide a data transfer device with high processing efficiency that makes full use of the high-speed performance even when ultra-high-speed elements are used.

[Structure of the Invention] (Means for Solving Problems) The present invention connects slot control devices provided corresponding to each of a plurality of processors in a ring via a data transfer path to store transfer data. In the inter-processor data transfer device that performs mutual data transfer between the respective processors by circulating slots between the slot control devices, each of the slot control devices has two stages each storing two consecutive slots. It is characterized by having registers for the configuration and being composed of one module.

(Operation) According to the present invention, a two-stage register is prepared for each processor, and each processor is associated with two slots. This allows each processor to output two pieces of data to two slots during one rotation of the slot. Therefore, when the data transfer speed of the processor is kept the same, the circulation speed of the slot, that is, the time it takes for the slot to make one revolution, is reduced to 1/2 of the conventional speed. In addition, since the processing for two slots is realized by one slot control device, the effects of delays due to the input/output buffer and the wiring length between the slot control devices can be eliminated in one operation, which reduces the average transfer speed of the slots. can be raised.
From the above, it is possible to take longer time to process slots within the slot control device than in the past, improving efficiency.

(Example) Hereinafter, an example of the present invention will be described based on the drawings.

FIG. 1 shows the configuration of a parallel processing system that employs the data transfer method according to this embodiment. The plurality of processors 41a, 41b, . . . , 41n each include SE (slot control section) 42a, 42b, .
2n are connected, and the SEs 42a to 42n are connected in a ring via a data transfer path 43.

Each of the SEs 42a to 42n includes a reception buffer 51 that takes in data from the outside, a register 52 that temporarily stores data packets that are taken into the inside via this reception buffer 51, and a register 52 that temporarily stores data packets that are taken in from the outside via the reception buffer 51. Toggle generator 53 that generates toggle information indicating whether the data is the
and a slot processing unit 54 that performs processing for accessing and transferring slots based on the contents stored in the register 52, the toggle information, and requests from the processors 41a to 41n.
, a register 55 for temporarily storing data processed by the slot processing section 54, and a register 55 for temporarily storing data processed by the slot processing section 54.
5 and an output buffer 56 for outputting the data packet stored in 5 to the outside. That is, in this embodiment, in addition to the conventional SE configuration, a toggle generating device 53 and an output side register 55 are newly added. The toggle generator is e.g.
Can be configured using JK flip-flops.

Next, the operation of this system configured as described above will be explained.

The flow of data packets circulating through the data transfer path 43 is transferred through each of the SEs 42a to 42n through the input buffer 51→register 52→slot processing section 54→register 55→output buffer 56. That is, since each SE 42a-42n is provided with two registers 52, 55, each SE always holds two slots. Therefore, FIG. 2 schematically shows the correspondence between each processor and each slot. Each processor 41a~
41n each hold two slots. In the SE 42a, the register 52 holds information about the slot S1, and the information about the slot S2 is held by the register 52.
The register 55 holds the information, but the correspondence between the slots and the processors is arbitrary. For example, the slots S1 and S5 correspond to the processor 41a,
The processor 41b may correspond to the slots S2 and S6, the processor 41c may correspond to the slots S3 and S7, and the processor 41n may correspond to the slots S4 and S8, respectively. These slots S1 to S8 circulate in a constant cycle.

The structure of a data packet transferred by a slot is shown in FIG. The DATA section 61 stores the contents of the data to be transferred, the PN section 62 stores the transfer destination processor number, and the V section 63 stores the data to be transferred.
The DATA section 61 stores information indicating that data is stored, the A section 64 stores a response signal from the transfer destination processor, and the T section 65 stores toggle information indicating the context of the data. be done.

A processor that transfers data, e.g. 41a
describes the data to be transferred to the DATA section 61,
Write the transfer destination processor number in the PN section 62,
Write 1 indicating data transfer in the V section 63, and write 1 in the T section 6.
A data packet in which "0" is set for odd-numbered data and "1" for even-numbered data as toggle information is stored in the slot S1 or S5 corresponding to the processor 41a. This data packet eventually reaches the destination processor as it circulates through the slots. The receiving processor sets the T section 65 to "0" when the PN section 62 of the data packet matches its own processor number and receives odd-numbered data, and sets the T section 65 to "0" when receiving even-numbered data. Receives a data packet of “1” and sends the A section 64 to 1 as a response signal.
Set to . This data packet, with part A 64 set to 1, is further sent back to the sender's processor through further slot circulation. The sender's processor confirms that the A part 64 of the returned data packet is 1, that is, that the other party's processor has received the data, and sends the next data if necessary.

In this system, since two data packets for one processor are circulating on the data transfer path 43 at the same time, the receiver must always receive these two data packets in the correct order. For this reason, a T section 65 is provided in the data packet, and odd-numbered data is set to "0" and even-numbered data is set to "1".
is set to avoid changing the order of data. Note that in the data format shown in Figure 3, the sender's number is not written, so
It is necessary for the processor side to constantly monitor the position of its own slot. For example, as shown in Fig. 4, if a sender PN part 66 is provided in the data packet and the number of the sender processor is specified in this part, this can be done. No such monitoring is required.

Next, the operation of this system will be explained in more detail based on FIG. Data packets sent from SE 42n to SE 42a are stored in register 52 through input buffer 51. This register 5
2, the slot processing unit 54
performs the following processing.

of the data packet stored in the register 52.
When the number of the processor 41a connected to the SE 42a is written in the PN section 62 and there is a transfer request from the processor 41a, the data output from the processor 41a,
Transfer destination processor number and toggle generator 5
The toggle information from 3 is transferred to the DATA section 6.
1, is written in the PN section 62 and the T section 65, and outputs it to the register 65 with the A section 64 set to "0" and the V section 63 set to "1". Further, when there is no transfer request from the processor 41a, the V section 6
3 is set to "1" and output to the register 65.

There is a reception request from the processor 41a, and the PN part 62 of the packet data stored in the register 52 is the number of the processor connected to the SE 42a, the V part 63 is "1", and the T part 65 is the toggle generator. 53, the data stored in the register 52 is taken out and sent to the processor 41a, and the A section 64 of the data packet is set to "1" and output to the register 55.

, the data packet stored in the register 52 is directly stored in the register 55.
Transfer to.

The above processing results of the slot processing section 54 are held in the register 55, and are stored in the output buffer 56.
and is transferred to the next SE42b. Note that the register 52 can store the information of the next slot once the processing in the slot processing section 54 is finished, so
Two pieces of slot information are always held within one SE.

Here, we will consider the relationship between the number of processors, data transfer speed, and slot circulation speed in this system. In this system, one processor has two
Since two slots are compatible, one slot is
Data can be loaded into two slots during a cycle. Therefore, if the number of processors is n and the time it takes for the slot to move from one processor to the next is s, it takes ns for the slot to complete one rotation. During this time, two slot data can be loaded, so if the data transfer interval of the processor is p, the relationship n·s/2=p holds. Therefore, the moving time of the slot becomes s=2p/n, which is twice that of the conventional method s=p/n. Utilizing this property, it becomes possible to improve the circulation speed using high-speed element LSI, which was impossible with conventional methods.
Moreover, according to this embodiment, the above-mentioned effects can be obtained by an extremely simple improvement of simply adding the register 55 and the toggle generating device 53.

Note that in the above embodiment, each SE must process incoming slot information one after another. Therefore, as shown in FIG. 5, the slot processing section 54 is used in a time-division manner to proceed with the processing. In other words, the time it takes for a slot to move between processors is divided in half, with the first half processing the slot and the second half transferring it to the neighboring SE.

The breakdown of the slot transfer time between processors is as follows. As mentioned earlier, in the present invention, the slot circulation speed between processors can be halved, so if 10 processors send data every 50ns as described in the conventional example, or 40 processors send data every 200ns. In the case of sending, the slot is moved between processors in s=2×50/10=2×200/40=10 ns.
Therefore, due to input/output buffer and wiring delay,
Even assuming that there is a loss of 4 ns, a slot processing time of 10-4=6 ns is obtained. However, SE in Figure 1
42a to 42n use the slot processing section in a time-sharing manner, so the slot processing section 5
4 must finish the process. in fact,
The minimum value of these two, 5 ns, is the time for the slot processing section. The time allocation within SE at this time is
As shown in the figure. With 5ns, the processing of the slot processing section mentioned earlier can be realized using a high-speed element LSI.
The slot processing time can also be increased to 50% of the total time. There is also a margin of 1 ns, which allows the wiring length to be made even longer.

Note that in the SEs 42a to 42n in FIG. 1, the slot processing section 54 is used in a time-division manner, so even though 6 ns is allocated as the time for slot processing as described above, it actually has to be processed in 5 ns. , this point can be improved by configuring SE as shown in FIG. That is, the SE in FIG. 6 is the first SE
In contrast, two systems of registers 52a, 52b and slot processing units 54a, 54b are provided in parallel.

In this configuration, the first slot sent from another SE is stored in the register 52a and processed by the slot processing section 54a, and the second slot that is subsequently input is stored in the register 52b, and the slot Processing is performed by the processing unit 54b. The slot processing units 54a and 54b each output the processed results to the register 55.

By doing this, the slot processing section 5
4a and 54b, it is possible to perform processing in the maximum slot processing time (6 ns) obtained by the present invention, as shown in FIG.

[Effects of the Invention] As described above, according to the present invention, one processor can be associated with two slots, so the slot circulation speed can be allowed to be half that of the conventional one, and the speed between the slot control devices can be reduced. Since the wiring delay is included only once every two slots, the loss time of the time required for slot transfer can be reduced. Therefore, a system with high processing efficiency can be constructed using high-speed elements, and faster data transfer and connection of more processors are possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a parallel processing system according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the concept of data transfer of the system, and FIG.
4 and 4 are diagrams showing the format of data packets in the same system, FIG. 5 is a diagram showing the timing of data transfer in the same system, and FIG. 6 is a diagram showing the slots in a parallel processing system according to another embodiment of the present invention. Figure 7 is a block diagram showing the configuration of the processing device, Figure 7 is a diagram showing the timing of data transfer in the system, Figure 8 is a block diagram showing the basic configuration of the parallel processing system, and Figure 9 is the conventional slot circulation type parallel processing system. Figure 10 is a diagram showing the concept of the processing system, Figure 10 is a diagram showing the format of data packets in the system, Figure 11 is a block diagram showing the configuration of the slot processing device in the system, and Figure 12 is a diagram showing the data transfer timing in the system. FIG. 1a to 1n, 41a to 41n...processor, 2
...Coupling means, 3, 43...Data transfer path, 5a-5
n, 42a to 42n... slot control device, 31,
51...Input buffer, 32, 52, 52a, 52
b, 55, 55a, 55b...Register, 33, 5
4... Slot processing section, 34, 56... Output buffer, 53... Toggle generator.

Claims (1)

[Claims] 1. Slot control devices provided corresponding to each of a plurality of processors are connected in a ring via a data transfer path, and slots for storing transfer data are circulated among the slot control devices, thereby making it possible to In the inter-processor data transfer device that performs mutual data transfer, each slot control device includes an input buffer that receives data from the outside, and a first register that stores data input via the input buffer. a toggle generating device that generates toggle information that distinguishes between odd-numbered data and even-numbered data;
a slot processing unit that processes based on a transfer or reception request from the processor and the toggle information; a second register that stores data processed by the slot processing unit; and data stored in the second register. An inter-processor data transfer device comprising: an output buffer for outputting the data to the outside.