JPH0520791B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an image processing device that encodes a binary image of an object or the like photographed by a TV camera.

[Prior Art] An image processing device integrates pixels (represented by 1, for example) representing an image in a binary image for each X address and Y address, and projects the image in the X and Y directions. There is something to be desired.

Conventionally, such an image processing device scans a binary image pixel by pixel, and when a pixel represents an image, the content of the integration memory specified by the address of that pixel is incremented by one. In this way, I found a way to calculate the integrated value.

[Problems to be Solved by the Invention] However, since such image processing devices scan binary images pixel by pixel, it is difficult to perform such processing on images that have already been captured. ,
The memory capacity for one frame is required, and the memory capacity for one frame is required.
The integrated value cannot be determined unless the images for each frame are scanned. This has led to problems in that a large capacity memory is required and it takes a long time to calculate the integrated value.

The present invention has been made to solve these problems, and is an image processing device that can quickly calculate the projection of an image that has already been encoded and stored in a small memory. The purpose is to realize the following.

[Means for Solving the Problems] The present invention provides an image processing device that calculates the projection of a binarized image in the X direction and the Y direction. an X address memory and a Y address memory that store the X and Y addresses of the starting point of a series of pixels; a run length memory that stores the length in the X direction of a series of pixels representing an image; An address generator that provides an address signal for reading a run code to a run length memory, and an integrated value of the number of pixels representing an image are stored for each Y address, and an access position is determined by the Y address read from the Y address memory. is specified in the first
and the contents of the first integration memory specified by the Y address read from the Y address memory,
a first adder that adds the X-direction length data read from the run-length memory and stores the addition result at the same address as the address where the data before addition was in the first integration memory; a first control unit that controls generation of an address signal of the address generator and controls reading and writing of the first integration memory; and a value of the X address read from the X address memory is preset. an up counter, a down counter which is preset with the value of the length in the X direction read from the run length memory and generates a stop signal when the count reaches 0, and a down counter which generates a stop signal when the count reaches 0; a second integration memory whose access position is specified using the count of the up counter as an address; a second control section that performs a counting operation and stops supplying the clock when receiving a stop signal from the down counter, and controls reading and writing of the second integration memory; a second adder that adds 1 to the content of the second integration memory and stores the addition result at the same address as the address where the data before addition was in the second integration memory; The contents of the first integration memory specified by the Y address read from the Y address memory are
The number of pixels representing the image is accumulated for each Y address by adding the data of the length in the X direction read from the run length memory, and the projection of the image in the X direction is obtained; By adding 1 to the contents of the second integration memory specified by the count of the up counter from the time the up counter is preset until just before the stop signal is generated, the data for the count of the down counter is added. This image processing apparatus is characterized in that it increases the value by 1 and calculates the projection of the image in the Y direction.

[Example〕 The present invention will be explained below using the drawings.

In order to obtain an integrated value using the apparatus according to the present invention, a binary image is divided into the X and Y addresses of the starting point of a series of pixels representing an image (hereinafter referred to as a run),
A run code encoded according to the length of the run (hereinafter referred to as run length) is prepared. The run length in this case is the length in the horizontal direction. This data is generated by the image processing apparatus described in the specification of Japanese Patent Application No. 193226/1983 (Japanese Patent Application Laid-open No. 84073/1983) filed by the present applicant.

FIG. 1 is a block diagram of a main part of an embodiment of an image processing apparatus according to the present invention, and shows an apparatus for obtaining horizontal projection of an image.

In FIG. 1, 1 is a run code memory, which is composed of a Y address memory 11 and a run length memory 12. The Y address memory 11 and the run length memory 12 store the Y address of the start point of a run and the length of the run (hereinafter referred to as run length) as many times as the run code.

Reference numeral 2 denotes an address generator which generates an address signal for reading out a run code under the control of the control section 3 and supplies it to the Y address memory 11 and the run length memory 12.

Reference numeral 4 denotes an integration memory in which an integrated value for each Y address of the number of pixels of an image is stored. An access position is designated by an address signal from Y address memory 11.

An adder 5 adds the contents of the run-length memory 12 to the contents of the accumulation memory 4 specified by the address signal from the Y address memory 11, and stores the addition result at the same address in the accumulation memory 4.

Address generator 2, control unit 3, integration memory 4
and adder 5 constitute a projection integration section.

The operation of such an image processing device will be explained.

The address generator 2 generates an address AD ₁ for reading the run code under the control of the control unit 3. As a result, the data D ₀₁ and D ₀₂ having the contents specified by the address AD ₁ are read from the Y address memory 11 and the run length memory 12.

The address of the integration memory 4 is specified by data D ₀₁ from the Y address memory 11. That is, data D ₀₁ becomes address AD ₂ . At this time,
The integration memory is put into read mode by the R/W signal, and the data specified by address AD ₂ is read.
D ₀₃ is read out and input to the adder 5. Furthermore, data D ₀₂ is also input to the adder 5 .

Adder 5 adds data D ₀₂ and D ₀₃ . Here, by setting the R/W signal to the write mode, the addition result D _I1 is written to the address of the integration memory 5 designated by AD ₂ . As a result, the addition result is written to the same address as at the time of reading.

After scanning all the run codes in this way, the integration memory 4 has the following information as shown in FIG.
A horizontal projection of the image is stored. The size of the integration memory 4 is at least 1 in the horizontal direction of the screen.
It is sufficient to have as many pixels as the number of pixels in the column. FIG. 2 shows a 16×16 bit memory area for convenience of explanation.

FIG. 3 is a block diagram of a main part of an embodiment of an image processing apparatus according to the present invention, and shows an apparatus for obtaining a vertical projection of an image.

In FIG. 3, 6 is a run code memory, which consists of an X address memory 61 and a run length memory 62. The X address memory 61 and the run length memory 62 store the X addresses and run lengths of run start points for the number of run codes.

Reference numeral 7 denotes an address generator which generates an address signal for reading a run code under the control of the control section 8 similarly to the device shown in FIG.

Reference numeral 9 denotes an integration memory in which an integrated value of the number of pixels of an image for each X address is stored. The mode of this integration memory 9 is selected by an R/W signal (read/write control signal) from a control section 20, and the access position is specified by an up counter 21 and an address signal.

Reference numeral 10 denotes an adder, which adds 1 to the content read from the integration memory 9 and stores the addition result at the same address in the integration memory 9.

A control section 20 starts supplying clocks to the up counter 21 and down counter 22 upon receiving a start trigger from the control section 8 . Further, the control unit 20 supplies an R/W signal to the integration memory 9 to designate a read/write mode.

The up counter 21 is composed of a D type flip-flop, the output of the X address memory 21 is applied to the D terminal, the clock generated by the control unit 20 is applied to the CK terminal, and the integration memory 9 A signal is generated that specifies the address of. The up counter 21 is preset with the output of the X address memory 61.

The down counter 22 is composed of a D type flip-flop, and the output of the run length memory 62 is applied to the D terminal, and the clock generated by the control section 20 is applied to the CK terminal. Down counter 22
The output of the run length memory 62 is preset.

The address generator 7, control sections 8 and 20, integration memory 9, adder 10, up counter 21, and down counter 22 constitute a projection integration section.

Next, the operation of such an image processing apparatus will be explained.

Address generator 7 operates similarly to the device of FIG. AD ₃ is an address signal generated by the address generator 7, and D ₀₄ and D ₀₅ are data specified by the address signal AD ₃ and read from the X address memory 61 and run length memory 62.

The control section 8 applies a start trigger to the control section 20 in synchronization with issuing a clock to the address generator 7.

When the control section 20 receives this trigger, it starts supplying clocks to the two counters 21 and 22.
Further, in synchronization with this clock, the integration memory 9 is put into read mode by the R/W signal.

The down counter 22 generates a stop signal when the count reaches 0, and upon receiving this stop signal, the control section 20 stops supplying the clock.

This stop signal is also given to the control section 8, and when the control section 8 receives this signal, it outputs the next clock to the address generator 7 and also sends the next clock to the control section 20.
Apply a start trigger to.

The up counter 21 has an X address memory 61.
The output _D04 of is preset. The up counter 21 starts counting up with the clock from the control section 20. The output of the up counter 21 specifies the address of the integration memory 9.

The down counter 22 has a run length memory 6.
2 output _D05 is preset. The down counter 22 starts counting down in response to a clock from the control section 20, and outputs a stop signal to the control section 20 when the count reaches 0.

When the address AD ₄ is designated by the up counter 21 in the integration memory 9, the content D ₀₆ is first read out by the R/W signal, and the content D ₀₆ is input to the adder 10.

The adder 10 adds 1 to the content D ₀₆ by the “1” signal.
Add. The output of the adder 10 is input to the integration memory 9. Thereby, the addition result is written to the same address in the integration memory 9 at the time of reading.

Here, the operation for obtaining a vertical projection will be explained using the image shown in FIG. 2 as an example.

A case will be described in which the uppermost run in the image of FIG. 2 is processed.

The run code for this run has a starting point X, Y address of 4,2 and a run length of 5. Therefore, the up counter 21 is preset with the starting point X address 4, and the down counter 22 is preset with the run length 5.

Every time a clock is generated from the control section 20, the down counter 22 counts down from the count 5, and when the count reaches 0, a stop signal is generated. The up counter 21 counts up from count 4 to count 8 immediately before the stop signal is generated. As a result, the adder 10 increases the data value by 1 for the data stored from address 4 to address 8 of the integration memory 9.

That is, when the run length is 5, the data value of the contents of the integration memory 9 is increased by 1 for 5 addresses of data.

When processing other runs, similarly, the value of data at each address in the X direction where a run exists is incremented by 1.

After all the run codes have been scanned in this manner, the vertical projection of the image is stored in the integration memory 9 as shown in FIG.

If you want to project the image in both the horizontal and vertical directions, install both the devices shown in Figures 1 and 3, and if you want to map the image in either the horizontal or vertical direction, install the devices shown in Figure 1 and 3. One of the devices of FIG. 1 or 3 is provided.

Furthermore, when it is desired to obtain the projection of an image in both the horizontal and vertical directions, it is also possible to share components such as an address generator between the devices shown in FIGS. 1 and 3. good. In this way, projections in two directions can be obtained simultaneously.

[Effect] According to such an image processing device, since the projection of the image is obtained based on the run code, the result can be obtained faster than when the display image is also scanned pixel by pixel to obtain the projection. You can ask for it. This is particularly effective when obtaining a copy of image data that has been captured and stored in a memory in the form of a run code. Since the data that is the source of the projection is converted into a run code, the memory that stores this data only needs to have a small capacity.

Furthermore, using the image processing device according to the present invention,
When the position of an unclear line as shown in Figure 4 is applied to measurement, the result shown in Figure 5 is obtained, and the a ₁ , a ₂ , and a ₃ parts with large integrated values are detected as the line position. Ru. Therefore, the image processing apparatus according to the present invention is effective in such cases as well.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of an embodiment of an image processing apparatus according to the present invention, FIG. 3 is a block diagram of main parts of another embodiment of an image processing apparatus according to the present invention, and FIG.
FIGS. 4 and 5 are diagrams showing an example of the projection of images obtained by the apparatus shown in FIGS. 2, 7... Address generator, 3, 8... First control unit, 4... First integration memory, 5... First adder, 9... Second integration memory, 10... Second addition 11...Y address memory, 12, 62...Run length memory, 20...Second control unit, 21...Up counter, 22...Down counter, 61...X
Address memory.

Claims (1)

[Scope of Claims] 1. In an image processing device that obtains a projection of a binarized image in the X direction and the Y direction, , Y address, and a run length memory that stores the length in the X direction of a series of pixels representing an image.A run code is stored in the X address memory, Y address memory, and run length memory. an address generator that provides an address signal for reading; and a first address generator in which an integrated value of the number of pixels representing an image is stored for each Y address, and an access position is specified by the Y address read from the Y address memory.
and the contents of the first integration memory specified by the Y address read from the Y address memory,
a first adder that adds the X-direction length data read from the run-length memory and stores the addition result at the same address as the address where the data before addition was in the first integration memory; a first control section that controls generation of an address signal of the address generator and controls reading and writing of the first integration memory; and a value of the X address read from the X address memory is preset. an up counter, a down counter which is preset with the value of the length in the X direction read from the run length memory and generates a stop signal when the count reaches 0, and a down counter which generates a stop signal when the count reaches 0; a second integration memory whose access position is specified using the count of the up counter as an address; a second control unit that performs a counting operation and stops supplying the clock upon receiving a stop signal from the down counter, and controls reading and writing of the second integration memory; a second adder that adds 1 to the content of the second integration memory and stores the addition result in the same address as the address where the data before addition was in the second integration memory; The contents of the first integration memory specified by the Y address read from the Y address memory are
The number of pixels representing the image is accumulated for each Y address by adding the X-direction length data read from the run-length memory, and the projection of the image in the X-direction is obtained; By adding 1 to the contents of the second integration memory specified by the count of the up counter from the time the up counter is preset until just before the stop signal is generated, the data corresponding to the count of the down counter is added. An image processing device characterized by increasing a value by 1 and obtaining a projection of an image in the Y direction.