JPH0520940B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a packet switching system having a main processing section and a plurality of line corresponding sections, the main processing section can grasp the operating status of each line corresponding section at predetermined regular intervals. did.

[Industrial application field]

The present invention relates to a packet switching system, and more specifically, to a packet switching system in which the main processing section can improve the ability to grasp the operating status of each line corresponding section.

Packet switching systems include multiprocessor type packet switching systems. In this type of system, the management processor (main processing unit) recognizes the buffer usage status and frame-confirmed serial number of each line-compatible unit (mainly equipment that performs frame-level processing) connected to it. It is configured to manage the exchange processing of packets etc. sent to the packet terminal device via the .

[Conventional technology]

The manner in which the line handling section communicates the above-mentioned information to the main processing section, which is necessary for such exchange processing management, is as follows.

That is, the data is transmitted from the management processor (main processing unit) (MPR) (mainly performs packet level processing) 10 of the packet switching system shown in FIG. When the packet (DT ₀ , DT _{1 .} . . in FIG. 6) is sent to the line correspondence unit (LC) 16 connected to the input/output channel device 14, the line correspondence unit 16 converts the frame I containing the packet into Packet terminal equipment (DTE) that sent ₀ etc.
When the incoming call is confirmed from 18, the confirmed serial number (6th
Sends RR ₁ , RR ₂ ...) in the figure.

In addition, since the usage status of the buffer provided in the line handling unit 16 is also necessary for packet switching processing, the main processing unit 10 makes inquiries to the line handling unit 16 from time to time (BFQ in FIG. 6). In response, the line handling unit 16 notifies the main processing unit 10 of its own buffer usage status (BFA in FIG. 6).

[Problem that the invention seeks to solve]

In the conventional method described above, the main processing unit 10 is configured to receive a separate notification for each time-series event that the main processing unit 10 wants to grasp, so the number of notification events inevitably increases, and the main Since the notification event that the processing unit 10 receives from the line handling unit 16 is handled as an interrupt factor in the main processing unit 10, the overhead consumed in the interrupt processing, especially during high traffic, is reduced. This increases the overhead, resulting in a problem of lowering the system's packet processing ability.

The present invention was created in view of such problems, and provides a packet switching system that can capture the above-mentioned events at a certain period regardless of their number (high or low traffic) and improve packet processing capacity. The purpose is to

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in this figure, the present invention includes a main processing section 10 for packet level processing and an input/output connection means 2 for the main processing section 10 for packet level processing.
The present invention relates to a packet switching system having a plurality of line corresponding units 16 for frame level processing connected via 2. The present invention differs from the conventional one in that a buffer means 20 is provided between the main processing section 10 and each line correspondence section 16. Then, the operation information generated in the line correspondence section 16 within the first period is written into the buffer means 20, and the operation information string within the first period written in the buffer means 20 is processed by the main processing section 10 into the buffer means 20. The reading is performed in a second period which is asynchronous with the period of .

[Effect]

According to the system of the present invention, the main processing unit 10
The operating information of the line corresponding section that is desired to be grasped is written to the buffer means 20 in the first period, and read out from the buffer means 20 in the second period and made available to the main processing section 10.

Therefore, the disadvantages of the conventional system in which operating information is received separately in chronological order can be greatly improved, and the packet processing capacity of the system can be improved.

〔Example〕

FIG. 2 shows an embodiment of the invention. In this embodiment, a buffer register (BFR) 20 is provided between each line corresponding section 16 and the input/output channel device 14 of the conventional system shown in FIG.
While writing the number of free buffers and confirmed serial numbers (operation information) in the line correspondence section from the line correspondence section (LC) 16 corresponding to the first period, for example, at a fixed period t,
The present invention resides in that the content of the buffer register 20 is read by the main processing unit (MPR) 10 at a second period different from the first period, for example, at a constant period T longer than the period t. There are some characteristic parts.

By adopting such a configuration, the events that must be notified from the line handling unit 16 to the main processing unit 10 (the number of free buffers in the line handling unit and the confirmed serial number) can be notified within a certain period of time, rather than by event. It becomes possible to notify the main processing unit 10 of a plurality of events that have occurred as notification events.

FIG. 3 shows an example of the structure of this buffer register 20. The number of empty buffers in the line handling section 16 is 20 ₁ ,
The confirmation serial number ₂₀₂ etc. from the terminal device 18 is stored,
It is passed to the main processing unit 10.

FIG. 4 shows an example of a packet sequence using this buffer register 20. The line correspondence section 16 writes the confirmation serial number and the number of empty buffers in the line correspondence section 16 to the buffer register 20 at a constant period t, and the main processing section 10 writes the buffer register 20 at a constant period T.
Read it with .

The packet DT ₀ from the main processing unit 10 is transmitted on the line as a frame I ₀ , and when the frame level confirmation RR1 is obtained from the terminal device 18, the line handling unit 16 assigns the confirmation serial number "1" to the own line. Part 16
Store it in the internal memory area.

Thereafter, at writing time a into the buffer register 20, the confirmation serial number "1" in the memory and the number of empty buffers at that time are written into the buffer register 20. The main processing unit 10 side reads the contents of the buffer register 20 at reading time a' and processes the packet according to the confirmation serial number stored in the buffer register 20.

That is, the previously sent data DT is
If confirmed by , send the next data DT. If it is not confirmed, transmission of the next data DT is stopped until confirmation is obtained. or,
If the number of empty buffers in the line handling section 16 is less than the specified value, data transmission is stopped and processing is performed such as transmitting an RNR packet that cannot be received by the other party to the terminal device 18 on the originating side.

This example in FIG. 4 shows a case where the packets transmitted from the main processing unit 10 are sequentially confirmed by the terminal device 18, and the confirmation serial numbers RR ₂ and RR ₃ for frames I ₁ and I ₂ are also once sent to the line corresponding unit. 16 in memory. Then, at point b, the latest confirmation serial number
Write RR ₃ and the empty buffer status at that time into the buffer register 20. This information is stored in the main processing unit 10
At time point b', the packet is read from the buffer register 20 and thereafter the packet continues to be transferred in the same manner.

As explained above, the main processing unit 10 recognizes the serial number information necessary for packet transfer and the buffer status in the line handling unit 16 via the buffer register 20 at regular intervals T, so that the traffic is reduced. Even if the number of packets increases, the load required for these processes remains constant, and stable packet transfer is possible. Further, since the read processing of the buffer register 20 does not involve interrupt processing, the overhead of interrupt processing can also be eliminated.

〔Effect of the invention〕

As described above, according to the present invention, an example of an event within a certain period of time that must be notified from the line handling section to the main processing section is handled as one notification event, so the overhead spent on these events is reduced. The packet processing capacity of the system can be improved.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a diagram showing an embodiment of the present invention, Figure 3 is a diagram showing an example of information in the buffer register, and Figure 4 is an explanation of the embodiment shown in Figure 2. FIG. 5 is a diagram showing the configuration of a conventional system, and FIG. 6 is a diagram showing an example of a packet sequence for explaining the system shown in FIG. In FIGS. 1 and 2, 10 is a main processing unit;
Reference numeral 16 represents a line correspondence section, and reference numeral 20 represents a buffer means (buffer register).

Claims (1)

[Scope of Claims] 1 Main processing unit 10 for packet level processing and a plurality of line corresponding units 1 for frame level processing connected to this via input/output connection means 22
6, a buffer means 20 is provided between the main processing section 10 and each line correspondence section 16, and operation information of the line correspondence section 16 is written to the buffer means 20 at a first cycle. , characterized in that the operating information string written in the buffer means 20 within a second cycle longer than the first cycle is read by the main processing unit 10 in the second cycle. packet switching system.