JPH0521337B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of dry etching a metal pattern having a submicron line width, which is applied to integrated circuit devices, GaAsFETs, and the like.

[Technical background of the invention]

Recent semiconductor devices have become highly integrated and highly functional, as typified by VLSIs, and as a result, development of finer patterns is being actively promoted. The background to this is the practical use of RIE (Reactive Ion Etching) and ion beam milling as anisotropic etching methods in addition to isotropic etching, as well as improvements in resists.

Incidentally, GaAsFETs have already been commercialized, but the current situation is that the reduction of gate line width is an issue in order to improve their characteristics, and development is currently being carried out toward this goal. Of course, this GaAsFET requires a gate layer, a source region, and a drain region, and it is generally known that the gate layer is constructed by stacking multiple types of metal layers. The first step in this gate layer formation method is to directly deposit a resist layer on the GaAs substrate, remove the area where the gate layer is to be formed, and deposit multiple metal layers on the exposed GaAs substrate.
A method is known in which the excess composite metal layer is then removed by a lift method in which the resist layer is dissolved away.

On the other hand, in order to form a desired gate layer by installing a resist layer after depositing these multiple types of metal layers on the surface of the GaAs substrate, only the resist layer at the position where the gate layer is to be formed is removed to expose the composite metal layer. And furthermore,
After depositing the metal layer to serve as a mask on the remaining resist layer and the exposed composite metal layer, the remaining resist layer and the mask layer deposited thereon are removed by the lifting method as described above, and the mask layer is removed in advance. A method is known in which a composite metal layer including a metal layer is coated, a resist layer is coated, and the resist layer and mask metal layer other than the position where the gate layer is to be formed are removed.

The gate layer of this composite metal is made of Ti from the GaAs substrate side.
-W 1000 Å, Mo 1000 Å and Au 5000 Å as a mask metal layer, and Ti 1000 Å are laminated thereon, and the following methods are specifically shown.

FIG. 4 is a diagram schematically showing the top surface of a GaAsFET, in which a source region 2 and a drain region 3 are provided on a GaAs substrate 1, and a gate layer 4 is provided to be electrically connected to both regions.

In the method, Ti-W1000Å is deposited on a GaAs substrate.
After depositing Mo1000Å, Au5000Å, and Ti1000Å,
ODUR1014 (positive resist manufactured by Tokyo Ohka Co., Ltd.) is applied thereto, and the positive resist other than the position where the gate layer is to be formed is removed by contact exposure and development using a DeePUV exposure device. This positive resist is characterized by being weak against freon-based gases but strong against ion beams. Next, the Ti directly under the removed positive resist layer
After removing the layer, the Ti remaining at the location where the gate layer was to be formed
Ion beam milling is performed using the layer and resist layer as a mask as shown in Figure 6 to determine the line width.
A gate layer of 0.5 μm was obtained.

The method is similar to that on the GaAs substrate surface.
After depositing Ti-W, Mo, and Au, and depositing a negative resist CMSEX(R) (manufactured by Toyo Soda) on the Au layer that constitutes the top layer, use a direct writing EB exposure device to place the gate layer at the planned position. An opening is provided to expose the Au layer. Next, a Ti layer is placed on top of this negative resist.
At this time, a Ti layer with approximately the same thickness is obtained on the Au layer exposed in the opening. Furthermore, when this negative resist layer is dissolved, the laminated
The Ti layer is also removed, resulting in a shape in which the Ti layer remains only at a specific position on the Au layer, that is, the position where the gate layer is to be formed. Next, the Au layer was etched by ion beam milling, and the other metal layers were removed by RIE to obtain a gate layer in the 0.5 μm line.

This negative resist is characterized by its resistance to Freon gas.

[Problems with background technology]

Not only GaAsFET but also MISFET and other FETs,
There is a trend to improve characteristics by narrowing the gate width, and in this GaAsFET, the line width of the gate metal layer is also being reduced.
Development is underway to narrow the diameter from 0.5 μm to around 0.25 μm. Moreover, since this gate layer needs to be formed with its thickness direction perpendicular to the surface of the semiconductor substrate, a dry etching method, that is, an anisotropic etching method is employed. Moreover, since there is no suitable gas that can etch the Au layer required as the gate metal layer, ion beam milling becomes an indispensable method.

In this ion beam milling method, it is known that once the ion beam is incident, it is reflected and redeposited, promoting etching. It is necessary to select the incident angle of the ion beam in order to keep the velocity balanced. Furthermore, when performing ion beam milling, it is common to rotate to minimize etching errors between each workpiece or within a single workpiece, and of course also perform constant cooling. It is.

If ion beam milling is performed on a long and narrow gate layer under such conditions, the end portion of the gate layer, which rotates at a constant speed, will be severely damaged and the remaining metal layer will be poor, resulting in a slanted version of the FET. Characteristics are adversely affected. This residual film rate indicates the transferred film thickness in percentage.

[Purpose of the invention]

The present invention provides a novel metal pattern etching method that eliminates the above-mentioned difficulties.

[Summary of the invention]

In order to achieve the above object, the present invention adopts a method of forming a metal layer having a line width of submicrons on a semiconductor substrate by installing a pattern larger than the line width at the end of the metal layer pattern.

When patterning a metal layer, a simple and reliable method to prevent insufficient resist film thickness at the tip and loss due to loss of the side surface during etching by ion milling is to set the line width of the metal layer to 0.2 to 0.3. By providing a pattern with a line width of about 1 to 2 μm at the end of the resist film, a sufficient thickness of the resist film can be obtained, and variations in the line width of the metal layer can be suppressed.

[Embodiments of the invention]

The present invention will be explained in detail with reference to FIGS. 1 to 5.

FIG. 4 is a top view schematically showing the gate layer pattern of the GaAsFET. That is, the GaAs substrate 1 is provided with lead-out regions 2 and 3 from the gate electrode, and a gate layer 4 electrically connected to these regions is provided.
The specific means are shown in Figures 2 a to d, Figures 3 a to d,
This will be explained with reference to FIGS. 1 and 5.

As shown in Figure 2a, the GaAs substrate 1 has Ti-W
4 at 1000Å, Mo5 at 1000Å, Au6 at 5000Å and
Deposit Ti7 with a thickness of 1000Å, and apply ODUR 1014 to this Ti layer 7.
(Tokyo Ohka positive resist) 8 is applied and the second
Figure b is obtained. This positive resist is removed by contact exposure and development using a deep UV exposure device except for the position opposite to the position where the gate layer is to be formed. This state is shown in FIG. 2c. During this exposure and development, a pattern 10 consisting of a Ti layer 7' and a positive resist 8' having a larger line width than the intended line width is provided at the end of the gate layer, as shown in FIG.

Next, under the Ti 7 remaining as a mask, the positive resist 8 and the pattern 10, Ti-W4,
Etching a composite metal layer consisting of Mo5 and Au6
Line width 0.2μm that functions as the gate layer of GaAsFET
A composite metal pattern was obtained.

This ion beam milling device includes a discharge chamber 11 having an Ar gas inlet 10.
Consisting of target chamber12, this
Discharge chamber 11 has a Solenoid magnetic field that generates plasma and increases ionization.
is installed, and furthermore, a cathode 13 and an anode 14 are placed. Furthermore, this Discharge chamber 11 and
A grid 16 is provided between the Torget chambers, and a grid 16 is located adjacent to the grid 16.
There are 17 Neutralization filamuts, 500eV~
An ion beam 18 having an energy of 1500 eV sets a sample stage 19 holding a sample, that is, the GaAs substrate 1 described above, at a low temperature. This sample stage is arranged so as to be rotatable. By the way, O ₂ is also introduced from the Ar gas inlet 10, and the ion beam incidence angle is Ti.
Set at 10°, Au at 30° to 50°.

Next, an example of the method shown in the background art section will be explained with reference to FIG. On the surface of GaAs substrate 1, Ti-W4 is applied to 1000 Å and Mo5 is applied to 1000 Å as shown in Fig. 2.
5000 Å of Au6 is coated in this order as shown in Figure 3a, and a negative resist CMS is applied to this Au layer 6.
EX(R) (manufactured by Toyo Soda) 20 is provided, and then an opening 21 is provided as shown in FIG. 3b using a direct writing EB exposure device. In this example, the solid line in FIG. 1 corresponds to this opening, and the relationship is exactly opposite to that in FIG. 2.

Next, as shown in FIG. 3c, when Ti 1000 Å 7 is deposited on the negative resist 20, the Ti layer 7 is also formed on the Au layer 6 exposed in the opening 21.
Next, when this negative resist 20 is dissolved, FIG.
As shown in the figure, the Ti layer 7' is exposed at the position where the gate layer of the GaAsFET is planned to be formed.

Next, the composite metal layer with the Au layer as the top layer is etched using the Ti layer 7' as a mask using the ion milling device described above to obtain a composite metal layer with a line width of 0.25μ, and furthermore, this mask layer, the Ti layer 7 ' was also removed to obtain a composite metal layer functioning as the gate metal layer of the GaAsFET shown in FIG.

It goes without saying that there is no problem in changing the type of resist between the examples shown in Figures 2 and 3.
It should be added that a method in which only the layer is etched by ion beam milling can also be adopted as an applied example.

〔Effect of the invention〕

In the present invention, the tip of the gate pattern has a thickness of 1 to 2 μm.
Since this pattern has been provided, the characteristics of the resist remaining film at the tip of the metal layer are good when patterning the metal layer, and the pattern is tilted, and furthermore, the tip of the metal layer is not damaged during etching by ion beam milling as in the background technology. This makes it possible to reduce variations in the thickness of the metal layer.

This means that there is a thickness of 1 to 2 μm at the tip of the metal layer pattern.
Since a wide variety of patterns are installed, it is assumed that increasing the adhesion strength also contributes to achieving the above-mentioned effect.

In this way, from a metal layer with a line width of 0.5 μm (film thickness 1.0 μm) and an aspect ratio of 2, a line width of 0.25 μm (film thickness 0.8 μm) is obtained.
Although metal layers with an aspect ratio of 3 are required to be progressively thinner and taller, this requirement can be fully met.

On the other hand, the performance of the low noise element is determined by the following equation.

NF _nio +1+L _G √ _G + _Swhere , NF _nio : minimum noise figure, L _G : gate length, R _S : source resistance, R _G : gate resistance,
In order to reduce this noise figure, it is necessary to reduce L _G , R _S , and R _G . In this R _G , (1) increase of gate metal film thickness, (2) introduction of metal with good resistivity L _G
Therefore, the requirement is how to reduce the gate length.

However, as described above, by adding a pattern with a line width larger than that of the metal layer, it becomes possible to form a thin pattern over its entire length, and it becomes possible to form an element with a small noise figure.

It goes without saying that the method of the present invention is applicable not only to GaAsFETs but also to MISFETs, and furthermore, to devices requiring submicron metal layers.

[Brief explanation of drawings]

Figure 1 is a tilted view of the metal layer pattern necessary for the present invention, Figures 2 a to d and Figures 3 a to d are process diagrams using the pattern in Figure 1, and Figure 4 is a schematic diagram of the top surface of a GaAsFET. FIG. 5 is a cross-sectional view schematically showing a manufacturing apparatus applied to the present invention, and FIG. 6 is a perspective view of a conventional metal layer pattern.

Claims (1)

[Claims] 1. A step of forming a composite metal layer on the surface of a semiconductor substrate when etching the composite metal layer, which is rotated by ions incident at a specific angle on the composite metal layer pattern covering the surface of the semiconductor substrate; coating the layer with a resist; selectively removing the resist to form a resist with a large line width at the edges thereof; using the resist as a mask, removing the top layer of the composite metal layer; A metal pattern etching method comprising the step of removing the exposed composite metal layer using the remaining composite metal layer as a mask.