JPH0521373B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a synchronous terminal station that receives an 8KHz reference clock and necessary clocks from a clock supply device. The present invention relates to a phase monitoring system that issues control counter failure information when the phase deviates from a predetermined phase difference.

(b) Technical background This section explains how to determine the phase of signals between synchronous terminal stations in a synchronous terminal station group.

FIG. 1 is a block diagram showing the system configuration of an example of a group of synchronous terminal stations.

In the figure, 1 is a clock supply device (hereinafter referred to as DCS), 2 and 3 are multiplexers, multiplexers or exchanges that are synchronous terminal stations, 4 is a transmission line, and 5 is an internal station that transmits and receives signals between synchronous terminal stations. Shows the signal line.

In a synchronous terminal station group consisting of synchronous terminal stations such as MUX2 and MUX or switch 3, the phase of the 8KHz reference clock supplied from DCSI is used as a reference.
By determining the output phase of the signal output via the local signal line 5, the capacity of the phase absorption memory on the receiving side is minimized. Therefore, unless a signal is input with a predetermined phase on the receiving side, the phase cannot be absorbed and correct reception cannot be performed.

(c) Prior Art and Problems FIG. 2 is a block diagram of a conventional synchronous terminal station focusing on the inside of the station.

1 in the figure is the same DCS as in Figure 1, 6
1 shows a clock receiving section, 7 a control counter, 8 a multiplexing circuit, and 9 an intra-office interface circuit.

In each synchronous terminal station, the clock receiver 6 receives the 64KHz and 8KHz reference clocks supplied from the DCSI, and the clock receiver 6 multiplies the 64KHz clock to generate a 2MHz or 8MHz clock.
It is supplied to the control counter 7 along with the 8KHz reference clock. The control counter 7 uses the phase of the 8KHz reference clock as a reference, and the 8KHz clock and 2M clock.
It generates a Hz or 8MHz clock, and also generates control pulses necessary for multiplexing processing and supplies them to the multiplexing circuit 8. The multiplexing circuit 8 performs multiplexing based on the control pulses, and transmits and receives signals to and from other synchronous terminal stations via the intra-office interface circuit 9. In other words, the phase of the signal output from the in-station interface circuit 9 is determined by the control counter 7 using control pulses necessary for processing determined based on the phase of the 8KHz reference clock from the DCSI. . However, in conventional synchronous terminal stations, if the phase of the signal output from the in-office interface circuit 9 becomes a phase that cannot be absorbed by the memory on the receiving side due to a failure in the control counter 7, correct reception will not be possible. The disadvantage is that maintenance personnel have to spend time and effort in detecting faults because no alarm is issued.

(d) Purpose of the Invention In view of the above points, the purpose of the present invention is to prevent the phase difference of the signal output from the internal interface circuit of the synchronous terminal station from exceeding a predetermined phase difference that can be absorbed by the memory on the receiving side due to a failure in the control counter. The purpose of the present invention is to provide a phase monitoring method that issues control counter failure information when a failure occurs.

(e) Structure of the Invention In order to achieve the above object, the present invention focuses on the fact that the phase of the signal output from the in-station interface circuit matches the phase of the 8KHz clock output from the control counter. The phase of the output 8KHz clock is monitored based on the phase of the 8KHz reference clock from the DCS, and if the phase difference deviates from a predetermined phase difference that can be absorbed by the memory on the receiving side, fault information is generated.

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings.

FIG. 3 is a block diagram focusing on the inside of the synchronous terminal station according to the embodiment of the present invention.

In the figure, components with the same functions as those in FIG. 2 are indicated by the same symbols, and 10 is a phase monitoring circuit.

The difference between FIG. 3 and FIG. 2 is that the phase monitoring circuit 10
The point is that In the phase monitoring circuit 10, based on the 8KHz reference clock from DCSI received by the clock receiver 6, the phase of the signal output from the in-station interface circuit 9 is set to 8KHz corresponding to a predetermined phase difference that can be absorbed by the memory on the receiving side. A pulse with a phase width of

(g) Effects of the Invention As explained in detail above, according to the present invention, when a signal with a phase exceeding the phase absorption processing capacity of the signal receiving section is output due to a failure of the control counter, the control counter Since a warning of failure information is issued, this has the effect of making it easier for maintenance personnel to detect failures.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an example of a synchronous terminal station group, Fig. 2 is a block diagram focusing on the inside of a conventional synchronous terminal station, and Fig. 3 is a synchronous terminal according to an embodiment of the present invention. It is a block diagram when focusing on the inside of the station. In the figure, 1 is a clock supply device, 2 and 3 are synchronous terminal stations, 4 is a transmission path, 5 is an in-office signal path, 6 is a clock receiver, 7 is a control counter, 8 is a multiplexing circuit,
Reference numeral 9 indicates an in-office interface circuit, and 10 indicates a phase monitoring circuit.

Claims (1)

[Scope of Claims] 1. The output of a control counter that receives a reference clock from a clock supply device, generates and outputs a clock having the same frequency as the reference clock using the reference clock as a reference, and determines the input phase of the reference clock. The phase monitoring circuit compares the phase of the input clock with the phase of the reference clock to determine a phase difference, and issues fault information when the phase difference deviates from a predetermined phase difference. A phase monitoring method featuring: