JPH0522397B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a solid-state image sensor, particularly an interline transfer type CCD solid-state image sensor.

BACKGROUND TECHNOLOGY AND THEIR PROBLEMS Solid-state imaging devices intended for application to color cameras have entered the practical stage and are under active development. Cameras using solid-state image sensors have problems in resolution, sensitivity, etc. when compared to tube-type cameras currently in practical use, and a particular feature that should be improved is the reduction of smear. That is, in the interline transfer type CCD solid-state image sensor, as shown in FIG. When incorporated into the channel layer 6, smear occurs. In the figure, 7 is an insulating film made of SiO ₂ or the like, 8 is a transparent sensor electrode, 9 is a transfer electrode, and 10 is a light shielding layer made of Al or the like. As a method for reducing this smear, as shown in FIG. There is a way to form it. In addition, there are also methods such as the intra-switch getter method, which removes smear charges within the semiconductor substrate by forming recombination centers at high density, and the method where the drive circuit is improved to eject the charges within the vertical transfer register. Are known.

By the way, in the smear reduction method using the configuration shown in FIG. 2, if the impurity concentration of the island region 11 under the sensor section 1 and the vertical transfer register section 5 is the same, the charge generated at the bottom of the sensor section is horizontally It spreads and smear components increase. Therefore, it is necessary to form a barrier by making the impurity concentration of the island region under the sensor lower than the impurity concentration of the island region under the vertical transfer register. On the other hand, for example, when a P-type island region is formed in a P-type semiconductor substrate, the impurity concentration of the P-type island region must be higher than the substrate concentration in order to act as a barrier against smear charges, and at least several kT or more (k
is the Boltzmann constant and T is the absolute temperature). Ion implantation is usually used to form the P-type island region from the viewpoint of impurity concentration and depth control.

FIG. 3 shows a conventional method for manufacturing a CCD solid-state image sensor using island regions as a smear reduction method. In this example, first, for example, a P-type silicon semiconductor substrate 21
An oxide film 2 serving as a mask for ion implantation on one main surface of the
2 (see FIG. 1A), and this oxide film 2
Only the portion corresponding to the vertical transfer register section 2 is selectively etched using the photoresist layer 23 as a mask (see FIG. 3B). As the ion implantation conditions, it is necessary to increase the depth of the island region, so the implantation energy must be 300 KeV or more. For this reason, since the oxide film 22 alone is insufficient as a mask for ion implantation, the photoresist layer 23 used when patterning is also left. Next, boron ions are implanted and P
A shaped first island region 24a is formed (see FIG. 3C). When ion implanting boron at 300KeV,
According to LSS theory, R _P in silicon is 1.0002 μm, ΔR _P
= 0.143μm, and in SiO ₂ R _P =0.7536μm,
Since ΔR _P =0.0902 μm, if only SiO ₂ is used as an ion implantation mask, the thickness must be at least 1.08 μm or more. Furthermore, when the implantation energy is increased, the oxide film (SiO ₂ ) 22 and the photoresist layer 23
Even two layers will be insufficient. As the oxide film 22 becomes thicker, pattern accuracy decreases. Next, after this ion implantation, the photoresist layer 23 is peeled off, and heat treatment (drive-in) is performed for a long time at a temperature of 1100° C. or more depending on the depth of the first island region 24a (Fig. 3D).
reference). Next, a CVD SiO ₂ film 25 is deposited on the entire surface of the substrate, and a portion of the SiO ₂ film 25 corresponding to the area including the sensor section and the vertical transfer register section is selectively etched away (see Fig. 3E). ). Pattern accuracy in selective etching at this time is not required very much. Then, boron ions are implanted to form a P-type second island region 24b, and heat treatment (drive-in) is performed (see FIG. 3F). Next, an N ^- type buried channel layer 26 of a vertical transfer register section is formed in the island region 24 corresponding to the first island region 24a (see FIG. 3G). Note that the second island region 24b between the buried channel layers 26 becomes the sensor portion formation region 27. In the subsequent steps, necessary steps for forming a CCD solid-state image sensor, such as forming transfer electrodes on the vertical transfer register section or forming sensor electrodes, are performed in the same manner as usual.

However, the conventional manufacturing method, particularly the method for forming the P-shaped island region 24, has the following problems. That is, high-energy ion implantation is required to form the first island region 24a, and therefore a thick oxide film is required as a mask for ion implantation, which does not improve pattern accuracy. Especially in the case of high resolution, the pattern width is less than 3μm, so
High-precision pattern formation becomes difficult. Furthermore, when high-energy ion implantation is used, it is difficult to obtain an ion implantation mask that can withstand this. In other words, when the energy is 700KeV, R _P of SiO ₂ is 1.3μm,
A thickness of 1.9 μm or more is required, making it difficult to use a two-layer mask consisting of an SiO ₂ film and a photoresist layer. Furthermore, since high-energy ion implantation is used, implantation damage becomes large and crystal defects occur, which cannot be sufficiently recovered even with annealing treatment, causing image defects and an increase in dark current. In addition, in order to form a deep P-type island region, high temperature (over 1100℃) is applied after ion implantation.
A long heat treatment (drive-in) is required, and the contamination from the furnace and the effect on the silicon substrate cannot be ignored. At the same time, the increase in processing time is disadvantageous in terms of cost. Further, there are problems not only in the pattern formation method but also in the impurity concentration profile within the island region. Particularly in the case of boron, when the implantation energy is 500 KeV or more, the impurity concentration distribution in the P-type island region corresponding to the vertical transfer register section is high on the substrate surface and decreases toward the inside of the substrate (see Fig. 5). distribution()). If an N ^- type buried channel layer is formed in the P-type island region in this state, the N-type impurity concentration must also be increased because the surface concentration of the island region is high, which limits the conditions for forming the buried channel layer. become. Additionally, the position of the minimum potential of the buried channel layer moves toward the surface, making it more susceptible to surface traps.

OBJECTS OF THE INVENTION The present invention provides a method for manufacturing a solid-state imaging device that improves the problems encountered in forming the above-mentioned island regions.

Summary of the Invention The present invention selectively forms an island region of one conductivity type on the main surface of a semiconductor substrate by ion implantation, and forms a one-conductivity type island region with an impurity concentration lower than that of the island region on the main surface of the substrate including the island region. A vertical transfer resist portion is formed in a portion of this epitaxial layer corresponding to the island region, and a sensor portion is formed in another portion of the epitaxial layer.

In the manufacturing method of the present invention, since low-energy ion implantation can be used, the ion implantation mask can be made thinner, and pattern accuracy can be improved. Further, heat treatment after ion implantation, impurity concentration distribution in the island region, etc. are improved.

Embodiment Hereinafter, an embodiment of the solid-state image sensing device according to the present invention will be described using FIG.

In the present invention, first, as shown in FIG. 4A, an oxide film 22 serving as an ion implantation mask is deposited on one main surface of a P-type silicon semiconductor substrate 21 with an impurity concentration of about 10 ¹⁴ cm ^-3 . Form. This oxide film 22 is formed by depositing a thermally oxidized SiO ₂ film and a CVD SiO ₂ film.

Next, as shown in FIG. 4B, a photoresist layer 23 is formed.
Using this as a mask, a portion of the oxide film 22 corresponding to the vertical transfer register portion is selectively removed by etching.

Next, as shown in FIG. 4C, this photoresist layer 23 is also left and ions of, for example, boron are implanted into the main surface of the base 21 to form a P ⁺ type first island region 24a with an impurity concentration of about 10 ¹⁶ cm ^-3 . form. The ion implantation conditions at this time do not necessarily require high-energy ion implantation, and the conventionally used low-energy ion implantation of about 100 KeV may be used. Therefore, the thickness of the oxide film 22 may be approximately 3000 Å.

Next, after removing the photoresist layer 23, heat treatment is performed for a short time (10 to 20 minutes) at around 1000°C for the purpose of drive-in or annealing. This repairs the implant damage and also provides some drive-in (see Figure 4D).

Next, as shown in FIG. 4E, the oxide film 22 is completely removed and a P-type epitaxial layer 31 corresponding to the second island region is grown on the main surface of the base body 21. This epitaxial condition has an impurity concentration of 10 ¹⁴ to 10 ¹⁵ cm.
A thickness of about ^-3 and a thickness of about 1 μm is sufficient. With the current epitaxial technology, epitaxial growth using SiH ₄ can guarantee variation within ±10% in a thickness of 1 μm, so there is no problem in controlling the thickness. Moreover,
Since the process is carried out at a temperature of around 1020°C, the occurrence of defects can be sufficiently controlled. Further, the impurity concentration of the first island region 24a is
Since it is about 10 ¹⁶ cm ^-3 , there is no autodoping,
The concentration profile within epitaxial layer 31 can also be precisely controlled.

Next, as shown in FIG. 4F, an epitaxial layer 3 is formed.
An N ^- type buried channel layer 26 of the vertical transfer register section is formed in a portion corresponding to the first island region 24a of the first island region 24a. Further, a portion corresponding to the epitaxial layer 31 is designated as a sensor portion formation region 27, and a sensor portion is formed here. The subsequent steps are to form a channel stop region and an overflow drain region (not necessary in the case of a vertical overflow drain structure) in the same way as usual, and to form a transfer electrode on the vertical transfer register section via an insulating film. The desired interline transfer type CCD solid-state imaging device is constructed by forming sensor electrodes and the like.

According to this manufacturing method, in the island region 24 corresponding to the vertical transfer register section, the impurity concentration of the first island region 24a on the base side can be arbitrarily controlled by ion implantation, and the portion where the buried channel layer 26 is formed can be controlled arbitrarily by ion implantation. The impurity concentration of the (so-called second island region) can be separately controlled by the epitaxial layer 31. Therefore, an impurity concentration distribution () as shown in FIG. 6 is obtained in the P-type island region 24. Incidentally, FIG. 5 shows the impurity concentration distribution () of the conventional P-type island region 24 produced by the manufacturing method shown in FIG.

When forming the buried channel layer of the vertical transfer register section, if the basic concentration is high, it is necessary to increase the surface concentration of the buried channel layer, making it difficult to form a buried channel structure. As the concentration of the buried layer increases, the position of the minimum potential moves closer to the substrate surface, resulting in nearer surface channel behavior. Therefore, it is necessary that the impurity concentration in the island region of the buried channel forming portion be low. on the other hand,
In order to prevent charges caused by light incident from the sensor section into the substrate from entering the vertical transfer register section, it is necessary that the impurity concentration of the island region under the buried channel layer is higher than that of the substrate. In this manufacturing method, the 6th
As shown in the impurity concentration distribution () in the figure, the buried channel formation part in the island region has a low concentration, and the deeper part has a higher concentration than the base, so it is possible to reliably prevent smearing and at the same time ensure a normal buried channel. Operation is guaranteed.

Further, in this manufacturing method, high energy ion implantation as in the conventional method is not required for ion implantation to form the first island region 24a. For this reason, the oxide film 22 serving as a mask for ion implantation can be made thin, and pattern accuracy during mask formation is improved. This is suitable for forming a high-resolution solid-state imaging device with a pattern width of 3 μm or less. Also,
Since the buried channel layer of the vertical transfer register portion is formed in the epitaxial layer 31, there is no implantation damage or crystal defects caused by conventional ion implantation, and image defects, increase in dark current, etc. can be avoided. Further, there is no need to make the first island region 24a deep, and the heat treatment after ion implantation can be performed at a lower temperature and in a shorter time. Therefore, contamination from the furnace and adverse effects on the semiconductor substrate are eliminated, and process time is also shortened.

Note that in the method of forming a P-type island region on a P-type semiconductor substrate, the concentration of the sensor portion and the concentration of the substrate may be the same. In addition, in this manufacturing method, as a method for creating marks for pattern alignment after the formation of the first island region 24a, a selective epitaxy method can be used, leaving the SiO ₂ film only in the mark portions.

The above example describes the case where a P-type island region is formed on a P-type semiconductor substrate, but in addition, as shown in FIG. It can also be applied to configurations that form. Furthermore, it can also be applied to a configuration in which the conductivity types are reversed.

Effects of the Invention According to the present invention described above, an island region of one conductivity type is selectively formed on the main surface of a semiconductor substrate by ion implantation, and an epitaxial layer of one conductivity type is formed on the island region with an impurity concentration lower than that of the island region. , low energy ion implantation can be used for ion implantation. Therefore, the oxide film serving as a mask for ion implantation can be thin, and the pattern accuracy when forming the mask is improved. Further, since the high concentration island region formed by ion implantation is located at a substantially deep position, heat treatment after ion implantation can be performed at a low temperature and in a short time. Further, since the vertical transfer register portion is formed in the portion corresponding to the island region of the epitaxial layer, the concentration of the vertical transfer register portion can be controlled.

As described above, the present invention can improve the reliability of a solid-state imaging device using island regions as a smear reduction method, and can also achieve high resolution.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of a solid-state image sensing device used to explain the present invention, FIG. 3 is a cross-sectional view of a manufacturing method of a conventional solid-state image sensing device, and FIG. 4 is a cross-sectional view of a solid-state image sensing device according to the present invention. 5 is an impurity concentration distribution diagram of the island region according to the conventional manufacturing method, FIG. 6 is an impurity concentration distribution diagram of the island region according to the manufacturing method of the present invention, and FIG. FIG. 3 is a sectional view showing another embodiment of the present invention. 21 is a semiconductor substrate, 24a is a first island region of one conductivity type, 26 is a buried channel layer of a vertical transfer register section, and 31 is an epitaxial layer of one conductivity type.

Claims (1)

[Claims] 1. An island region of one conductivity type is selectively formed on the main surface of a semiconductor substrate by ion implantation, and an epitaxial layer of one conductivity type with a lower impurity concentration than the island region is formed on the main surface of the substrate including the island region. A method for manufacturing a solid-state image sensing device, characterized in that a vertical transfer register section is formed in a portion of the epitaxial layer corresponding to the island region, and a sensor section is formed in another portion of the epitaxial layer.