JPH0522913B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a group language learning device consisting of one master device and a plurality of slave devices, and in particular uses random access memory as a storage medium for teaching materials, and The present invention relates to a device in which audio signals stored in the random access memory are read out multiplexed in a time-division manner according to operations by a student, and distributed and supplied to each child device.

<Background technology and its problems> In general, the so-called LL-system (language
In the group language learning method called the Laboratory System, the main content is the repeated practice of basic fixed sentences.

To do this, we first create duplicate tapes of teaching materials for the number of students, and the students play the duplicate tapes at their own pace using LL tape recorders placed for each student to practice language skills such as English conversation. was taken.

Therefore, in the conventional method as described above, LL tape recorders for the number of students are necessarily required.
A drawback is that the larger the scale of the LL-system, the greater the cost to create the system.

In addition, the recording and playback operation of a tape recorder is originally a so-called sequential operation that is performed along the magnetic tape, and when a student arbitrarily selects a specific part of the teaching material to practice, rewinding the tape,
Fast-forwarding takes time and it is not possible to respond to the selection immediately.

Furthermore, since each tape recorder operates independently, it is difficult to synchronize all tape recorders and have all students listen to the same sentence at the same time. cannot be used in synchronization with other devices.

<Object of the invention> The present invention has been made in view of the above-mentioned circumstances, and uses random access memory (hereinafter referred to as "RAM") as a storage medium for teaching materials in the LL-system.
), we aim to diversify language learning methods using the LL-system and
The purpose is to eliminate the drawbacks of the LL-system.

<Summary of the Invention> In order to achieve the above object, the present invention provides N (N=1, 2,
3...) a slave device, a memory for digitally encoding and storing the audio signal at a predetermined sampling period, and reading out the digitally encoded audio signal from the memory and transmitting the digitally encoded audio signal to the N slave devices. In the group language learning device, the readout means of the parent device includes an address register having a storage area corresponding to each of the N child devices, and an operation mode of the child devices. address value updating means for updating the value of the address data stored in each storage area of the address register according to the state of the selection switch; The value of the address data stored in each storage area of the address register is updated periodically, and the address data stored in each storage area is supplied to the memory, so that the value of the address data stored in each storage area of the address register is supplied to the memory. The digitally encoded audio signal is read out, and the digitally encoded audio signal having the predetermined sampling period is distributed to each slave device. .

<Example> An example according to the present invention will be described below with reference to FIGS. 1 to 5.

First, before describing specific embodiments of the group language learning device according to the present invention, the basic configuration and operation of the present invention will be outlined.

As shown in FIG. 1, the group language learning device according to the present invention consists of one master device 1 and a plurality of child devices 2, 2, 2, . . . (for example, as many as the number of students).

The master device 1 is provided with a RAM 3 for storing audio teaching materials for language learning, and this RAM
3 with a given sampling period and quantization level.
Each data signal of the audio teaching material digitally encoded into a PCM (Pulse Code Modulation) signal is stored at a predetermined storage address (hereinafter referred to as "RAM address"). Note that the data signal is a signal of each sample value obtained by digitally encoding the analog signal of the audio teaching material at a predetermined quantization level.

In addition, the slave devices 2, 2, 2, etc. are placed one at a time in each student's hand, and can be adjusted according to each student's operation.
Address register 4 that specifies the RAM address,
4, 4, ..., digital-to-analog converters 5, 5, 5, ... that convert data signals read from the RAM 3 into analog signals according to their specifications, and headphones 6, 6, 6, ... .

The master unit 1 and slave units 2, 2, 2 are connected by a signal line formed through a signal distributor 7.

The signal distributor 7 includes a pulse generator 8.
The reference pulse output from the address register 4, 4, 4,
4. RAM of RAM3 output by the operation of...
A signal specifying an address (hereinafter referred to as "RAM address signal") is sequentially supplied to the RAM 3 in a time-division manner in synchronization with the reference pulse. Similarly,
Each data signal read from the RAM 3 according to the RAM address signal is sent to the digital-to-analog converter 5, 5, 5, . . . of each child device 2, 2, 2, . are distributed and supplied sequentially.

As mentioned above, the parent unit of the group language learning device according to the present invention digitally encodes the audio signal for the teaching material at a predetermined sampling period and quantization level, stores the data signal obtained thereby in the RAM 3, and The data signals to be supplied to the slave devices 2, 2, 2, .

Then, the digital-to-analog converters 5, 5, 5, ... of each child device 2, 2, 2, ... convert the data signal supplied at the sampling period into an analog signal,
As a result, audio signals for teaching materials are supplied to each student.

As described above, in the group language learning device according to the present invention, audio signals for teaching materials can be read out in response to each student's operation of the child device, similar to group language learning using a conventional tape recorder.

Next, specific examples according to the present invention will be described.

Note that the group language learning device in this example is
Audio band 4.0 between 1 parent device and 256 child devices
In addition to sending and receiving [kHz] audio signals for teaching materials,
It is assumed that it is equipped with a RAM that can store 1000 seconds worth of audio signals.

In addition, in this example, since the audio signal in the audio band of 4.0 [kHz] is handled, the sampling frequency is set to 8.0 [kHz] (sampling period: 125
[μsec]). Furthermore, if the quantization level of the data signal stored in the RAM 10 that stores the audio signal for 1000 seconds is 8 [bit], then the RAM 10
The storage capacity of is the product of the sampling frequency, quantization bits, and storage time, so the storage capacity of RAM 10 is 8.0×10 ³ [Hz] x 8 [bit] x 1000 [sec] = 64 x 10
⁶
[bit]≡8×10 ⁶ [byte].

FIG. 2 is a block diagram showing the electrical configuration of the group language learning device according to this embodiment.

In this device, the address register 20 for specifying the RAM address of the RAM 10 is
00 side, 256 word memory address AR1~corresponding to the number of child devices 101 [256 units]
RAM with AR256 is used.

In addition, each of the above memory addresses of the address register 20
AR1 to AR256 each consists of 23 [bit],
As a result, each of the memory addresses AR1 to AR256 can store the first to ^23rd RAM addresses.

In addition, since 2 ²³ 8.4 × 10 ⁶ , each memory address AR1 to AR256 of the address register 20 of this device is
The RAM address of all data signals (8×10 ⁶ ) that can be stored in RAM 10 can be specified.

The address register 20 is supplied with various signals, which will be described later, that are output from an operating device 40 provided in the child device 101.

Then, the address register 20 supplies the RAM address signal RAP to the adder 21, and
It is supplied to the RAM 10 via a multiplexer (hereinafter referred to as "MPX") 22.

Next, the operating device 40 includes a forward/stop switch (hereinafter referred to as "F/S switch") 41 and a normal/jump switch (hereinafter referred to as "N/J") for specifying the operation mode of this device selected by each student. 42 (hereinafter referred to as "JMP switch"), and a jump destination address specification switch (hereinafter referred to as "JMP switch").
) 43.

The F/S switch 41 outputs a binary signal of "1" when the student selects the forward mode and "0" when the student selects the stop mode as the address operation signal OP to the adder 21 via the MPX ₂ 23.
Supplied to one side of the input. When the adder 21 is supplied with "1" as the address operation signal OP, it adds "1" to the RAM address signal RAP already supplied from the address register 20 and supplies it to the MPX ₅ 26, and also outputs the address Operation signal
When “0” is supplied as OP, the RAM address signal RAP has already been supplied to the adder 21.
is supplied as is to MPX ₅ 26.

The above JMP switch 43 is composed of 23 [bits] and sends a jump destination address signal JAP to specify how far to jump when a certain student selects the jump mode described later.MPX ₃ 25
to MPX ₅ 26 via.

Like the F/S switch 41, the N/J switch 42 receives a binary signal of "1" or "0" as the operation mode selection signal MSP via the MPX ₄ 24.
MPX ₅ 26, thereby switching the output signal of MPX ₅ 26.

In other words, when a student specifies normal mode, the operation mode selection signal MSP is set to "0".
MPX ₅ 26, which makes the output of MPX ₅ 26 the new RAM address signal RAP supplied from adder 21, and also sets "1" to MPX as the operating mode selection signal MSP when the student specifies jump mode. ₅ 26, thereby
Jump the output of MPX ₅ 26 to the destination address signal JAP
and one of these signals (RAP or JAP)
is supplied to the address register 20.

Next, 50 is a pulse generator, and this pulse generator 50 uses the sampling period (125 [μsec]) as the reference clock pulse SP of this device for the number of slave devices (256
A timing pulse of 488 [ns], which is equal to the value divided by [unit]), is supplied to the counter 51. This counter 51 is composed of 8 bits, and outputs the count number "1 to 256" corresponding to each of the 1st to 256th child devices 101 as a counter signal CP in synchronization with the reference clock pulse SP. do.

The counter signal CP is the MPX ₂ 2
3, MPX ₃ 25, MPX ₄ 24, address register 20, and a demultiplexer (hereinafter referred to as “D”), which will be described later.
−MPX”) 11 input terminals 27, 28,
29, 30, and 12.

For example, when a counter signal CP with a count number of "n" is output, this counter signal CP is sent to the address via each of the signals RAP, JAP, and MPX ₅ 26 output from the controller of the n-th slave device. When the data signal D is supplied to the n-th memory address ARn of the register 20, the data signal stored in a predetermined location of the RAM 10 corresponding to the RAM address stored in the n-th memory address ARn of the address register 20 is supplied to the n-th memory address ARn of the register 20. - Each of the MPXs 23, 24, 25,
Controls the address register 20 and the D-MPX 11.

Further, the counter 51 has an output period of 488 [n
sec] by counting the reference clock pulse SP of 488[n
The counter signal CP corresponding to the count number "1" to "256" is output at a period of [sec]. Therefore, according to this counter 51, for example, a counter signal CP with a count number of "1" is output at a cycle of 125 [μsec], which is equal to the sampling cycle.

Therefore, data signals are distributed and supplied to each child device 101 at a timing equal to the sampling period.

Next, the counter 51 receives the reference clock pulse.
Divide SP by 256 to 125 [μsec], which is equal to the sampling period.
When writing the reference pulse WSP with a period of
3. Reference pulse input terminal 1 of write signal generator WPG52 and address specification counter WAC53
5, 16, 54, and 55 as a synchronizing signal.

The above address specification counter WAC53 is 23 [bit]
The above writing reference pulse WSP
The addressing signal WAP for counting and specifying the RAM address from 1 to 2 ²³ is
Supply to MPX ₁ 22.

Note that the MPX ₁ 22 is switched between a read mode and a write mode by a mode changeover switch 56, and when in the read mode, it receives the RAM address signal RAP supplied from the address register 20.
On the other hand, in the write mode, the address designation signal WAP output from the address designation counter WAC53 is supplied to the RA10.

In addition, the write signal generator WPG52 is turned on and off by switching the mode changeover switch 56.
When it is turned off and turned on, that is, in the write mode, it supplies the write signal WP to the RAM 10 in synchronization with the write reference pulse WSP.

Next, an audio signal for language learning is supplied to the audio signal input terminal 17 of the analog-to-digital converter 14, which is supplied with the writing reference pulse WSP via the reference pulse input terminal 16. Then, this analog-digital converter 14 digitally encodes the audio signal into a PCM signal with a sampling period of 125 [μsec] and a quantization level of 8 [bit].

Then, each data signal of the digitally encoded sample value is sequentially sent to the RAM 1 at a timing of 125 [μsec].
0.

Next, the operation of the group language learning device according to this embodiment as described above will be explained.

The operation of this device can be broadly divided into two types:
The operation is divided into a write operation in which the data is stored in the RAM 10, and a read operation in which the specified teaching material is read out according to the operation of the controller 40 by each student.

First, the writing operation of this device will be explained.

This device is set to write mode by switching the mode changeover switch 56, and thereby
From MPX ₁ 22, address specification counter WAC5
Address designation signal WAP supplied from 3 is output and supplied to RAM 10.

In addition, the write signal generator WPG52 is also turned on, and the write signal output from the generator 52 is
WP is supplied to RAM10.

When analog signals (audio signals) A, B, C, etc. having waveforms as shown in FIG. 3 are supplied to the audio signal input terminal 17 of the analog-to-digital converter 14, those signals A, B, C, ... is the sampling period
It is digitally encoded at 125 [μsec] and quantization level 8 [bit], and the data signals are each "a ₁ , a ₂ , a ₃ ,
a ₄ ,…, an” “b ₁ , b ₂ , b ₃ , b ₄ ,…, bm” “c ₁ ,
c ₂ , c ₃ , c ₄ ,…, cl”… are output in sequence,
It is supplied to RAM10.

Reference pulse WSP when writing above, each data signal
a ₁ , a ₂ , a ₃ , ..., b ₁ , ..., c ₁ , ..., address designation signal WAP and write signal WP are supplied to the RAM 10 at the timing shown in FIG.

That is, the above data signals a ₁ , a ₂ , a ₃ ,...,
b ₁ , ..., c ₁ , ..., the address signal WAP, and the write signal WP are all supplied to the RAM 10 in synchronization with the writing reference pulse WSP.

Then, the first data signal _a1 is
an addressing signal WAP representing "1", which simultaneously becomes the RAM address of the signal _a1 ;
Then, a write signal WP instructing to store the data signal a ₁ in the RAM address "1" is supplied, so that the data signal "a ₁ " is stored in the RAM address "1" of the RAM 10.

The above storage operation is repeated sequentially at a timing of 125 [μsec], and the data signal "a ₂ " is stored in the RAM.
The data signal "a 3 " is stored to the address "2", the data signal "a ₃ " is stored to the RAM address "3", and the data signal "bm" is stored to the RAM address "n+m".

Therefore, RAM address "1" of RAM10
to RAM address “8×10 ⁶ ” in order.
Data signals from the 8th×10 6th data signal “a ₁ ” to the 8th×10 ^6th data signal are each stored.

Next, the reading operation of this device will be explained.

First, by operating the mode selection switch 56, the write mode is switched to the read mode.

This causes MPX ₁ 22 to become address register 2.
It outputs the RAM address signal RAP supplied from 0 and supplies it to the RAM10.

At the same time, the write signal generator WPG52
It goes into the OFF state and stops supplying the write signal WP to the RAM 10.

This device has an operating device 40 arranged for each child device 101.
The following three types of read operations can be performed by the operation.

That is, the first operation is to operate the N/J switch 42 to set the normal mode, and to switch the F/S
Data signal stored in RA10 by operating switch 41 to change to forward mode (hereinafter referred to as "normal forward mode")
This is a case where a ₁ , a ₂ , . . . are sequentially read from the first one.

Now, to explain the case where the first student (the student operating the AR1) specifies the normal forward mode, the first memory address of the address register 20 is cleared as an initial state.

The adder 21 is connected to the F/S switch 41 of the first student's controller 40 via the MPX ₂ 23.
"1" is supplied as the address operation signal OP from the RAM address signal OP, and the RAM address signal is incremented.
As a result, MPX ₅ 26 has RAM address “1 (1
A new RAM address signal specifying "+0)" is supplied. At the same time, the above MPX ₅ 26 has MPX ₄ 2
4, "0" is supplied from the N/J switch 42 as the operation mode selection signal MSP.
MPX ₅ 26 specifies RAM address "1"
The RAM address signal is supplied to the first storage address AR1 of the address register 20, and the storage address AR1 stores "1" as a new RAM address.

The above operation is performed during the period from when the counter signal CP with a count number of "1" is outputted from the counter 51 until the counter signal CP with a count number of "2" is outputted, that is, during a period of 488 [ns]. After the counter signal CP with the count number "2" is output, a predetermined new RAM address is stored in the second storage address AR2 of the address register 20 based on the operation of the second student, as in the case described above. Ru.

Then, after the counter 51 outputs the counter signal CP with the count number "256" (that is, 125
(After [μsec]) The counter 51 returns to the count number “1”
Similarly to the above case, the address register 20 outputs the RAM address signal specifying the RAM address "1".
is supplied to RAM10, which causes RAM10 to
The data signal a ₁ stored in the RAM address "1" is supplied to the D-MPX 11, and the D-MPX 11 distributes and supplies the data signal a ₁ to the digital-to-analog converter 13 of the first student.

At the same time, the first memory address of address register 20
RAM added “1” by adder 21 to AR1
A new RAM address specifying address "2 ₍₁₊₁₎ " is stored.

Next, the second operation is to operate the N/J switch 42 to enter normal mode, and operate the F/S switch 41 to enter stop mode (hereinafter referred to as "normal stop mode").
This is a case where the data signal is prevented from being read from the RAM 10.

That is, in this case, in the first operation, the address operation signal is sent from the F/S switch 41.
Since "0" is supplied as the OP to one input of the adder 21, the RAM address is not incremented and the memory address of the address register 20 is maintained in a clear state, so that no data signal is output from the RAM 10.

Also, if the normal forward mode is switched to the normal stop mode at any time, the RAM address is changed to the adder 21 as described above.
is not incremented by the adder 21, and the new
RAM at the time of switching above is always used as the RAM address.
A RAM address designation signal designating an address continues to be supplied to the designated storage address of the address register 20.

Therefore, the same data signal is always supplied from the RAM 10 to the slave devices, and no audio teaching materials are supplied to the students.

That is, when the normal stop mode is set, the RAM 10 outputs a signal that is not decoded as an audio signal, as shown in the column for the second student (No. 2) in FIG.

Next, the third operation is to operate the N/J switch 42 to set jump mode, and to specify the jump destination address with the JMP switch 43, from any teaching material (data signal corresponding to) desired by the student. This is a case where the data is read out.

Now, the nth student (student operating ARn)
To explain the case where the user tries to read the audio signal B of the second teaching material, first, the initial state is the first operation (normal, forward,
mode), the nth storage address ARn of the address register 20 is cleared.

Then, by specifying the jump destination address "n+1" with the JMP switch 43, MPX ₅ 2
6 is supplied with a RAM address signal specifying jump destination address "n+1" via MPX ₃ 25. Moreover, the MPX ₅ 26 selects the jump destination address "n+1" by "1" as the operation mode selection signal MSP supplied via the MPX ₄ 24.
A RAM address signal specifying the address is supplied to the nth storage number ARn of the address register 20, and the jump destination RAM address "n+1" is stored in the storage number ARn as a new RAM address.

Then, after 125 [μsec], the count number is “n” again.
When the counter signal CP is output from the counter 51, the nth memory address of the address register 20 is
ARn is accessed again and specifies the jump destination RAM address "n+1" that was previously stored.
RAM address signal is RAM10 and adder 2
1 single-sided input.

As a result, from RAM10, the jump destination
The data signal stored at RAM address "n+1" is output, and the data signal b ₁ is output from D-MPX11.
Accordingly, the digital of the child device 101 of the nth student -
The signal is distributed and supplied to the analog converter 13.

In addition, in this third operation, "1" is then supplied to the adder 21 as the address operation signal OP from the F/S switch 41, as in the first operation, thereby causing the jump destination address specified by the student to be Following the data signal b ₁ stored in the data signal b 1 , the data signals b ₂ , b ₃ , b ₄ , . . . are sequentially read out as subsequent data signals.

As is clear from the above description, in the group language learning device of this embodiment, the first and third students specify the normal forward mode, and the second student specifies the normal stop mode.
In addition to specifying the mode, when the 256th student tries to read from the second teaching material B, the data signal output from the RAM 10 will be the 5th data signal at a period of 488 [ns] synchronized with the counter signal CP. As shown in the vertical columns of the figure, “a ₁ ” “ ” “ a ₁ ”… “b ₁ ”,
"a ₂ """"a ₂ "... "b ₂ ", "a ₃ """"a ₃ "...
``b <sub>3</sub> '', ``a _o '', ``a <sub>o</sub> ''...``b _o '', ``b <sub>1</sub> '', ``''
b ₁ ”
… “b _o+1 ”, etc.

Also, those data signals are sent to the first and third students as "a ₁ " and "a ₂ " by the D-MPX11.
Supplied as “a ₃ ”… “a _o ” “b ₁ ” “b ₂ ”…
The 256th student has "b ₁ ", "b ₂ ", "b ₃ "... "b _n "
They are distributed and supplied sequentially like "c ₁ ", "c ₂ ", etc.

Since the data signal is distributed and supplied to each student at a cycle equal to the sampling cycle of 125 [μsec], the read data signal is converted into the original analog signal (audio signal) by the digital-to-analog converter 13. be done.

Incidentally, the audio signal of the teaching material is naturally supplied to each of the 4th to 255th students, who are not mentioned in the above explanation, in the same manner as described above.

<Effects of the Invention> As is clear from the above description, in the group language learning device according to the present invention, the operation mode selection switch operated by each learner can be changed depending on the state of the operation mode selection switch, such as forward mode, stop mode, jump mode, etc. Since the value of the address data stored in the corresponding storage area of the address register is updated, each learner can freely retrieve learning information from the memory of the master device according to his or her own learning speed. and learn effectively.

Further, the address changing means is configured to 1/1 of the sampling period.
The value of the address data stored in each storage area of the address register is updated at a cycle of N, and the address data stored in each storage area is supplied to the memory, thereby updating the memory. The digitally encoded audio signal is read out from the digitally encoded audio signal, and the digitally encoded audio signal having the predetermined sampling period is distributed to each slave device. Therefore, a digitally encoded audio signal can be easily converted into the original analog signal, and the configuration of each child device can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic principle of the present invention, FIG. 2 is a block diagram showing the electrical configuration of an embodiment of the present invention, and FIG. 3 is a waveform diagram showing the audio signal of the language learning material. 4 is a time chart of each signal when the digitally encoded audio signal shown in FIG. 3 is stored in the group language learning device shown in FIG. 2, and FIG. It is a figure which shows the output signal of the group language learning device which memorize|stored the signal. 10...Random access memory (RAM),
11...Demultiplexer (D-MPX), 20...
...address register, 21...adder, 22...
Multiplexer 1 (MPX ₁ ), 23...Multiplexer 2 (MPX ₂ ), 24...Multiplexer 4
(MPX ₄ ), 25...Multiplexer 3 (MPX ₃ ),
26...Multiplexer 5 (MPX ₅ ), 51...Counter, 100...Main device, 101...Slave device.

Claims (1)

[Claims] 1 N each having an operation mode selection switch
(N=1, 2, 3...) slave devices, a memory that digitally encodes and stores the audio signal at a predetermined sampling period, and reads out the digitally encoded audio signal from the memory and In a group language learning device comprising a parent device having readout means for supplying data to the N child devices, the readout device of the parent device includes an address register having a storage area corresponding to each of the N child devices; address value updating means for updating the value of the address data stored in each storage area of the address register according to the state of the operation mode selection switch of the slave device; The value of the address data stored in each storage area of the address register is updated at a cycle of 1/N of , and the address data stored in each storage area is supplied to the memory. , the digitally encoded audio signal is read out from the memory, and the digitally encoded audio signal having the predetermined sampling period is distributed to each slave device. Group language learning device.