JPH0522920B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a frequency control device suitable for electronic musical instruments that generates data for expressing frequencies, and particularly to one that controls frequencies using a digital method. Conventionally, various proposals have been made for musical tone generators using digital systems. Among these, digital data of a sine wave or a musical sound waveform is stored in memory, and this is read out sequentially to create a continuous musical sound waveform, which is then multiplied by envelope data corresponding to an envelope signal. hand,
There is a device in which a musical tone signal from the rise to the fall of a sound is formed by changing the amplitude value. In order to change the frequency of the generated waveform, it is sufficient to skip over a predetermined number of samples and read each sample of the digital data, instead of reading each sample sequentially. If the jump number is J, the frequency can be set in direct proportion to J. Instructions on how to generate such signals were published in 1969 by THE MIT
The book “The Technology” published by PRESS
of Computer Music", pages 134 to 138. Also, the magazine IEEETrans.on Audio
and Electroacous-tics, Volume 19, No. 1, 48-58,
1971 Document A Digital Frequency Synthesizer”
shows the specific configuration. Japanese Patent Application No. 165189/1989 provides a more specific and practical system based on these known examples. For these musical tone synthesis methods, it is necessary to generate and supply the jump number J. The present invention relates to a method for generating and supplying this jumping number J, and is particularly devised to efficiently generate various frequencies. Next, the relationship between the method of the present invention and the conventional example will be described. Conventionally, music synthesizers generate a key voltage V _K corresponding to each key on the keyboard, and then superimpose the voltage V _F that sets the frequency and the vibrato voltage V _V on this, and calculate 2V ₁ = (V _K + V _F + V _V ), and through an exponential converter, we obtain V _O =K _1exp (V _{K +} V _F + _V
Determine. When the voltage V _F is oV, the key voltage V _K
A frequency determined by , that is, a frequency corresponding to the musical scale (261.625 Hz for C ₃ ) is generated. Normally, the standard key voltage V _K is 1V per octave. When 1V is added as voltage V _F ,
It rises one octave and generates 513.25Hz. This hits C ₄ as well as the second harmonic of C ₃ . If a voltage other than 1V is applied as the voltage V _F , arbitrary harmonic components such as the third and fourth harmonic components can be obtained. The vibrato voltage V _V modulates the frequency up and down around each of the above frequencies, but what is important here is that even if V _K and V _F have various values, the rate of frequency fluctuation is , the pitch fluctuation remains constant if V _V is constant. Japanese Patent Laid-Open No. 81824/1984 is known as a method in which such a method is replaced with digital calculation. however,
Such conventional devices have drawbacks such as being unstable because they are made of analog circuits, and requiring a large number of highly accurate digital arithmetic units. The present invention solves these problems and provides a frequency control device that can be easily configured in practice. FIG. 1 is a block diagram of an electronic musical instrument employing the frequency control device of the present invention. 1 is a keyboard section, 2 is an operation section consisting of a tone tablet switch, a vibrato effect on/off switch, a volume for setting the depth of the vibrato effect, etc., and 3 is a central processing unit (CPU), which is used in computers etc. 4 is a read/write storage device (random access memory, usually
5 is a read-only storage device (read-only memory, usually called RM) in which a program that determines the operation of the CPU 3 is stored; 6 is a
A ROM 7 stores envelope parameters among parameters for synthesizing timbres, and a ROM 7 stores data related to frequencies among parameters for synthesizing timbres. 8 is a frequency control device of the present invention, 9 is the above-mentioned sine wave generator, 10 is an envelope data generator, 1
1 is a multiplier that multiplies the sine wave and envelope data; 12 is a time slot control device that adds predetermined results of time-division multiplexed multiplication results or replaces them with the order of time-division multiplexing; time division multiplexed phase modulator, 14
is a digital-to-analog converter, and 15 and 16 are electroacoustic transducers. Keyboard section 1, operation section 2, CPU 3, RAM 4,
ROM5, ROM6, ROM7, frequency control device 8, and envelope data generator 10 are coupled by a data bus, an address bus, and a control line. The method of connecting the data bus, address bus, and control line in this way is as follows:
This is a well-known method for configuring minicomputers and microcomputers. Eight to 16 data buses are used, and data is transmitted and received on these bus lines not in one direction but in multiple directions in a time-division manner. A plurality of address buses, for example 16, are prepared, and normally the CPU 3 outputs the address code, and other parts receive the address code. As the control line, a memory request line (), an I/request line (), a read line (), a write line (), etc. are usually used. indicates reading and writing memory,
IORQ indicates the retrieval of the contents of the input/output device (I/), indicates the timing to read data from the memory or I/, and indicates the timing to write data to the memory or I/. Using such a control line,
An example is the microprocessor Z80 from Zilog. Next, the operation of the electronic musical instrument shown in FIG. 1 will be described. The keyboard section 1 is configured such that a plurality of key switches are divided into a plurality of groups and the N-FF states of the key switches in the group can be sent to the data bus all at once. For example, for a 5-octave keyboard
60 keys in 10 groups of 6 keys (half octave) and 1 key
Divide into 11 groups and assign one address code to each group. When an address code indicating one of the above groups arrives on the address line,
When RD is applied, the keyboard section 1 decodes the address code and outputs 6-bit or 1-bit data indicating ON-FF of the key switches in the corresponding group to the data bus. These can be constructed using decoders, bus drivers and some gate circuits. Of the operating section 2, the tablet switch can have the same configuration as the keyboard section 1. Regarding the setting status of the volume, the voltage output from the volume is converted into a digital code by an analog-to-digital converter, and this is converted into an address code and a control line.
Read by IORQ. CPU3 reads the instruction code from the address of RM5 that corresponds to the code of the internal program counter, decodes it, performs arithmetic operations, logical operations, reads and writes data, and jumps instructions by changing the contents of the program counter. Perform tasks such as The steps for these tasks are RM
It is written in 5. First, the CPU 3 reads a command for importing data of the keyboard section 1 from the ROM 5, and imports codes indicating N-FF of each key of the keyboard section 1 for each group. Then, the pressed key code is assigned to a finite channel of the musical tone generator. Next, the CPU 3 sequentially reads a group of instructions from the RM 5 for importing data from the operating section 2, decodes them, outputs the address code and control signal corresponding to the operating section 2, and connects the operating section to the data bus. It outputs the code that expresses the switch and volume status in step 2, and
Load within 3. Then, the CPU 3 knows which tone of musical tone signal should be synthesized. Now that it has become clear which channel of the musical tone generation section should generate which tone at which frequency, the CPU 3 selects the desired tone from the ROM 7 which stores data regarding the frequency of each tone. The address code storing the frequency parameters and the control signals MREQ and RD are output, and the desired frequency parameters are read out onto the data bus, taken into the CPU 3, and written into the frequency control device 8. In order to write, the frequency control device 8
CPU3 outputs the address code corresponding to the data register provided inside the CPU3, and at the same time
When WR is output, data representing the frequency parameter being output on the data bus at the rising edge of the signal is written into the data register. Next, timbre parameters representing the content of the timbre to be output are read from the RM 6 and written into a register inside the envelope generator 10. Next, when a sound output command is given to both the frequency control device 8 and the envelope generator 10, the frequency control device 8 gives the jump number J to the sine wave generator 9, and the envelope generator 10 generates envelope data. . The sine wave data output from the sine wave generator 9 and the envelope data are multiplied to give an envelope to the sine wave. The sine wave data and envelope data are generated by being time-division multiplexed, respectively. Time division multiplexing is, for example, 160 multiplexed, 20 sine waves are assigned to each channel, and 8 channels are provided. Normally, one musical tone is synthesized by combining 20 sine waves.
Therefore, as known from the Fourier series formula, 20 sine wave data will be added. Data addition between time slots for this purpose is performed by the time slot converter 12. The time slot converter adds predetermined data from among the sine wave data strings modulated with envelope data, which are time-division multiplexed and input into 160 time slots to reduce the number of time slots, or This converts time slots like the time division multiplex converter of Japanese Patent No. 57-202790. The time-division multi-real phase modulator 13 is based on the patent application filed in 1983-
Like No. 182083 “Digital musical tone modulation device”,
Multiple types of modulation are performed simultaneously using time division multiplexing. The output of the time-division multiplexing phase modulation device 13 is converted into an analog signal by an analog-to-digital converter 14 and output from electroacoustic transducers 15 and 16. Although not shown in FIG. 1, the time slot converter 12 and time division multiplexing phase modulation device 13 are also connected to the CPU 3 via address buses, data buses, and control lines, and are controlled by the operating section 2. The time slot conversion and modulation conditions can be changed and set in accordance with the tone color and modulation effect settings that are made at the same time. In the frequency control of the present invention, first, the note octave of each key, the frequency of each harmonic, etc. are arranged on a cent scale and processed. The note and octave position of the fundamental wave of the musical tone to be output, the position of harmonics relative to the fundamental wave, the relative shift of non-harmonics, etc. are expressed in cents, and the cent address can be added or subtracted on the cent scale. Then, the cent address for the cent value of the actual frequency component is obtained, and this is subjected to exponential conversion. In order to digitize the system and to obtain the jump number J for a large number of spectra, consideration is given to quantizing and handling one octave on the cent scale and performing arithmetic processing by time division multiplexing. Also, the timing is considered so that the calculated J is appropriately transferred to the sine wave generator 9. The present invention relates to a frequency control device 8 as a part of an electronic musical instrument as shown in FIG. It is. One embodiment is shown in FIG. The frequency control device in Fig. 2 includes a data bus DB,
The address bus ADR is connected to the CPU 3 through the control line and the chip select line CS to receive frequency parameters, and the address bus is connected to the microcomputer interface circuit (MIF) 25.
The ADR code is decoded and written to the internal register group, and the necessary multiple J _i are calculated through the internally provided mechanism for calculating the jump number J. ,
The signal is supplied to a sine wave generator 9. First, the constituent elements will be explained. 21 is a program counter that supplies timing pulses;
(PC) 22 is a timing pulse generator (TPG) that extracts logic from timing pulses to create necessary address codes and receives control flag (FLG) signals to generate control signals; 23 is a timing pulse generator 24 is a sequencer (SEQ) consisting of RM that stores the contents and procedures of arithmetic operations and discursive operations, which will be described later. Command signal (OC1~12), write command signal (0~
3) It is an instruction decoder that outputs an operation command signal (P code), etc. 25 is the microcomputer interface circuit (MIF) described earlier.
26 is an arithmetic unit (ALU) that performs addition, subtraction, and comparison between two inputs, the A bus and the B bus, outputs the operation result to the C bus, and records the sign, upper bit, etc. of the operation result. Output as FLG.
FLG is supplied to TPG22. 27 is the working register (WREG)
It consists of two words of memory, WREG1 and WREG2, and accepts input from the C bus and supplies output to the B bus. AD2 selects one of the two words and writes it at the rising edge of 1, and provides an output when C8 is "H". 28 is a RAM consisting of 16 words x 15 bits, which receives input from the C bus.
Provides output to the bus. The 160 words are divided into 8 channels of 20 words each, and any one word within the 20 words can be converted into a 5-bit address code AD.
1, select any one of the 8 channels with the 3-bit address code AD4, write the data on the C bus at the rising edge of 2, and the output remains on the D bus. However, the upper five bits of the output are supplied to the buffer memory 29. The buffer memory 29 is a 160 word x 17 bit RAM, and accepts the data on the C bus and the upper 5 bits of the RAM 28 as input. The 160 words are divided into 8 channels of 20 words each.
One word out of 20 words is selected with address code AD3, one of the eight channels is selected with address code AD4, input data is written at the rising edge of 3, and output when OC9 is "H".
The output of the buffer memory 29 is the octave shifter 3
0. The code of the upper 5 bits of the buffer memory 29 causes the lower data to be
It is bit shifted by a predetermined number of bits and output. This output is transferred to a register corresponding to a predetermined address among the registers provided inside the sine wave generator 9 and storing the jump number. 33 is the note octave register (ND
(n)) to get the latest note octave data,
It is accepted from the CPU 3 via the data bus DB and output to the A bus when necessary. Write is performed with 2, and read with OC2. 34 is a note octave register (ND(n-1)) which receives the previous note octave data from the CPU 3 via the data bus DB, and outputs it to the B bus when necessary. It also receives and stores intermediate processing data from the B bus. Write data from DB using 3, write from B bus using WRO, and output to B bus using C3. 35
is a harmonic data memory (HMD), which is composed of 64 words x 13 bits RM.
Which of the 64 words is selected is determined by a 6-bit code output from the partial number memory 36. The partial number memory 36 is
Data bus DB with 20 words x 6 bits RAM
Accept input from. Select 1 word out of 20 words with address code AD1 and write at the rising edge of 4. The output is always supplied to harmonic data memory 35. The output of the harmonic data memory is output to the A bus when C4 is "H". 37 is non-harmonic memory (INH),
It consists of 20 words x 6 bits RAM.
1 word out of 20 words is address code AD
1 is selected, data bus is selected at the rising edge of 5.
Data on the DB is written and output to the A bus when C5 is "H". 38 is the exponent conversion table (EXP). Constructed by RM. D
The bus is input, and when C6 is "H", the contents are output to the A bus. Reference numeral 39 denotes a differential index conversion table (DEXP), which is composed of RM, receives the D bus as an input, and outputs the stored contents to the B bus when C6 is "H". The contents of these two tables will be described later. 40 is a gate which inputs the D bus and outputs to the B bus when C7 is "H". 32 is a portamento register (PRT) which accepts a code representing portamento speed from the data bus and stores it at the rising edge of 1. 31 is a portamento data converter, which generates frequency increase/decrease data based on the contents of the portamento register 32, and when C1 is "H"
Output to the A bus when . The same contents as the normal portamento register 32 are output. 42 is a vibrato data generator that generates a code representing a vibrato waveform, and C10 is set to "H".
When VIB(n) is connected to B bus, C11 is “H”
When VIB(n) is connected to the A bus, C12 is “H”
When , VIB (n-1) is output to the B bus. VIB
(n) represents the current vibrato data,
VIB(n-1) represents the previous vibrato data. 41 is status flip-flop (SFF)
Then, the data on the data bus DB is stored at the rising edge of 6, and the contents are supplied to the TPG 22. The TPG 22 outputs an interrupt signal INT when the frequency control device requests new data from the external CPU 3.
The interrupt vector code indicating the interrupt contents is sent to the data bus.
Output on DB. When the output command signals C1 to C12 are "L", the outputs of the memories and registers corresponding to them become high impedance and A
We are trying not to have any impact on buses or B buses. <Data Structure> Next, the mechanism of index conversion for frequency control performed in the present invention and the data structure before and after conversion will be described. One octave has a frequency ratio of 1:2. As a numerical value directly proportional to the frequency F, the jumping number J
is defined as follows. Assume that the memory that stores one waveform of a sound source consists of ²¹⁸ words (samples). Sample readout frequency cK
If it is Hz, the frequency of the output waveform will be c/2 ¹⁸ Hz when all samples are read out one sample at a time. This corresponds to the jump number J=1. Generally, the frequency F for the jump number J can be expressed as F=c/2 ¹⁸ ×J (1). In the present invention, one octave is quantized on the cent scale, and the calculated frequency value expressed on the cent scale is converted into an interlaced number directly proportional to the frequency by exponential conversion. The method of index conversion will be described below. If one octave is expressed in cents, it is 1200.
Become a cent. The ratio of the two frequencies F _A and F _B in cent scale CE is as follows. CE (cent) = 1200log ₂ (F _A /F _B ) (2) If the jump numbers of frequencies F _A and F _B are J _A and J _B , Let J _B correspond to C on the equal-tempered 12 chromatic scale,
And if its value is 2048 and J _A is expressed as J, then becomes. If this is written for the range of CE = 0 to 1200 (cents), it will look like Figure 3 A. Equation 5 is a curved line, but it is approximated by a broken line as follows. If you divide CE (0-1200) into 12 equal parts, you will get 100 cent intervals. This corresponds to the chromatic scale of 12 equal temperaments. Divide the 100 cents into 8 equal parts, making them 12.5 cents apart. Doing this will result in 12 x 8 = 96 points. Let J be _J for these 96 points CE _i =12.5×i (i=0 to L-1, L=96). Between i and i+1, further divide 12.5 cents into 8 equal parts. CE _i , _j = 12.5i + 12.5/8j (7) i = 0 ~ L-1, L = 96 j = 0 ~ M-1, M = 8 CE _i , _j (j = 1 ~ For 7), linearly interpolated values are used. In other words, J _i and _j are as follows. In general, J _i , _j = J _c [2 ^i/L + 2 ^i/L (2 ^{1/L -} 1) j/M(9) J _c : Number of jumps at the reference point L: Number of divisions in one octave M: number of divisions within the linear interpolation interval i=0, 1, 2,..., L-1 j=0, 1, 2,..., M-1. As mentioned earlier, if L=96 and M=8
The 1200 cent interval is quantized into 768 points at intervals of 1.5625 cents. The error will be less than ±0.78125 cents. Assign addresses to these 768 points.
Let this be the cent address. Next, in equation (8),
We will explain how to calculate J _i and _j . According to FIG. 3, J is represented by 12 binary bits for one octave. It is represented by 2048-4096. Figure 3B shows the range of CE=0 to 100 (cents) in detail. 100 cents is divided equally into 12.5 cents. Equation (8) is It can be expressed as Express i as a binary coded 96-decimal number. Since 96 = 4 x 3 x 8, the upper digits can be represented by two binary digits, the middle digit by a binary coded ternary number, and the lower part by three binary digits. The middle bit only needs to be 2 bits, so the total is 7 bits. j is represented by three binary digits and is the lower order of i.
In other words, 96 x 8 = 768 points within 1200 cents is the 4th point.
It can be represented by 10-bit codes _N3 to _N0 and _S5 to _S0 in Figure A. This code is called a cent address. Of these, N ₁ and N ₀ are expressed in binary coded ternary notation. For such values of (i, j),
96 values of J _i and _p are prepared in EXP 38 in FIG. Assuming 96 addresses, each with 12 bits,
96 x 12 = 1152 bits of ROM. This J _i , _p is
This corresponds to the first term of equation (10). Next, as a difference, a part of the second term of equation (10) Prepare in DEXP39 in Figure 2. The maximum value of DJ _i , _j is when i = 95, j = 7, DJ ₉₅ , ₇ = 25.784
Therefore, DJ _i and _j can be expressed as 5-bit binary numbers. Furthermore, (i, j) has 96×8=768 ways. Therefore, St. Address 768 Street, 768×
5 = 3840 bits of RM. The cent address input to the ROM of the EXP38 is the 7 bits {N ₃ to N ₀ , S ₅ to _{S 3 }} in FIG. N ₀ , S ₅
~S ₀ } 10-bit code. EXP
By adding the outputs of 38 and DEXP 39, J _i , _j in equation (10) can be obtained as a 12-digit binary number. FIG. 4A represents a binary number or expanded cents address displaying quantized pitches on a cents scale. O ₄ , O ₃ , O ₂ , O ₁ , O ₀
represents an octave. N ₃ , N ₂ , N ₁ , and N ₀ represent each note of the 12 equal-tempered chromatic scale within one octave. Of these, (N ₁ , N ₀ ) is binary evolution 3
Represents base numbers (0, 0), (0, 1), (1, 0), and (1, 1) does not occur. Therefore, (N ₃ ,
N ₂ , N ₁ , N ₀ ) are decimal numbers. In Figure 5 (N ₃
~N ₀ ) and the musical scale. _S5 , _S4 , _S3 , _S2 ,
S ₁ and S ₀ are 6-bit binary numbers that represent each pitch of the semitone interval divided into 64 equal parts. 1 octave is 1200
Since a semitone is a cent and a semitone is 100 cents, {S ₅ ~
S ₀ } represents an interval of 100 cents at intervals of 1.5625 cents. FIG. 4B shows the data format of ND(n), where the lower 4 bits indicate a note and the upper 4 bits indicate an octave. ND(n) corresponds to the fundamental frequency ₁ of the musical tone with the specified octave and note. Figure 4C shows harmonic data representing the ratio of the frequency _K of each harmonic component included in a harmonic musical tone to the fundamental frequency ₁ in cents.
This is HMD _K. HMD _K = 1200log ₂ ( _K / ₁ ) (12) (k = 1, 2, 3, ..., 64) expressed in binary. {H ₁₂ ~ _{H 0} }
Using 13 bits, the accuracy is ±0.78125 cents,
Can express up to 2 ⁸ = 256th harmonic. {H ₇ , H ₆ } are expressed in binary coded ternary numbers like {N ₁ , N ₀ }. FIG. 4D is a format of inharmonicity data INH _K representing non-harmonicity. INH
_is expressed as _a deviation of several cents from the HMD data in FIG. FIG. 4E expresses transient or steady fluctuations such as vibrato and glide on a cent scale. If the range of fluctuation is within ±100 cents, it can be represented by a 7-bit code {V ₆ to V ₀ }. Of these, _V6 becomes the sign bit. The procedure for determining the desired jump number J from the data shown in FIG. 4 will be explained. first,
Each symbol shall have the following meaning. (1) N(n): Cent address for note octave data at time n (2) HMD _K : Binary representation of cents for the fundamental frequency of the kth harmonic number (difference cent address) HMD _K = 1200log ₂ ( _K / ₁ ), _K = k ₁ (k = 1, 2, 3, ..., 64) (13) (3) IHM _k : Frequency deviation from the kth harmonic frequency in cents and Displayed in binary.
(Basically, if the difference cent address _K = k ₁ + d _k , then INH _k = 1200 log ₂ (k ₁ + d _k /k ₁ ) (14), but when INH _k exceeds 100 cents, it must be less than 100 cents for handling purposes. of
To find INH _k , proceed as follows. INH _k+p = 1200log ₂ k ₁ + p ₁ + (d _k − p ₁ )/k ₁ + p
₁ (15) (p=0, 1, 2, 3, ..., and d _k −p ₁
≧0) That is, it is shifted by d _k from the k-th harmonic, but this means that it is considered to be shifted by (d _k −p ₁ ) from the (k+p)-th harmonic. (4) VIB(n): Frequency deviation due to vibrato or glide at time n expressed in cents and in binary. (Modulation cent address) From the above variables, the frequency cent representation of the k-th harmonic, that is, the cent address, can be determined with the symbol LGJ (i,
j), LGJ _i , _j = ND(n) + VIB(n) + HMD _K + INH _k
...(16) becomes. LGJ _i , _j has the data format shown in FIG. 4A. Among these, {N ₃ , N ₂ , N ₁ , N ₀ ,
The 7 bits of S ₅ , S ₄ , S ₃ , } are in 96-decimal notation and represent i in equation (10). Similarly, the three bits {S ₂ , S ₁ , S ₀ } represent j. These codes mentioned above
When given as address data for the exponent conversion table and differential exponent conversion table for EXP38 and DEXP39, exponent conversion can be performed according to equation (10). This is expressed by the following formula. J*, _j = EXP [LGJ _i , ₀ ] + DEXP [LGJ _i , _j ]
...(17) From Figure 3A, the exponent conversion table has a range of only one octave. J _i , * indicates a value within this range. If the range exceeds an octave, J _i ,* may be bit-shifted according to the octave data {O ₄ , O ₃ , O ₂ , O ₁ , O ₀ } in FIG. 4A. For example, when {O ₄ to _{O 0} }=(00011), it is sufficient to shift 3 bits upward. As for how many bits to shift, use the sine wave generator 9
All you have to do is match it to the bit position. The above describes the data structure and the number of jumps J based on it.
The calculation procedure has been clarified. Although it is possible to implement a configuration in which equations (16), (17), and (18) are executed all at once, in the embodiment of the present invention (FIG. 2), they are executed in sequence. (16) formula,
Various methods can be considered to execute equations (17) and (18) step by step. The procedure according to the configuration shown in FIG. 2 described above is shown in Table 1.

【table】

[Table] In Table 1, of instruction groups A, B, and C, A
and B show the procedure for calculating the jump number J for 8 channels and 20 spectra in each channel. The instruction group A consists of instructions 4 to 7, and the instruction group B consists of instructions 8 to 11. The content of each command is indicated by the command content. For example, instruction 4 is N
Add D(n) and VIB(n) and write working register
This means storing in WREG2. Instruction 5 reads the contents of working register WREG2 and harmonic data HMDI, adds them, and stores them in WREG2. Instruction 6 is WREG2
and inharmonicity data INHI are added and stored in register LGJ (K, I).
Instruction 7 uses the contents of register LGJ (K, I) as an address code and converts it to exponent conversion table EXP2.
8 and the difference index conversion table DEXP39,
Add each output to buffer memory BUF
(K, I) Store in 29. Here, I represents a processing time slot (PTS), which will be described later, and also represents the spectrum number in each channel. I=1, 2, ..., 20.
K stands for channel time slot (CHS). K=1, 2, ..., 8. CHS
This will be discussed later. Regarding instruction group B, the meaning of the operation contents can be similarly read from Table 1. △ in instruction 8 is set to zero. Command group A is executed when note octave data ND(n) is changed, and thereafter command group B is executed. In instruction group B,
Since ND(n), HMDI, and INHI do not change, we do not calculate these, but subtract VIB(n-1) from the previous value LGJ(K, I) to calculate the value for the new value of VIB(n). Perform calculations and perform exponential conversion. When the note octave data ND(n) is updated, the program returns to the instruction group A and then executes the instruction group B again. In Table 1, ITS is an instruction time slot, and there are ITS1 to ITS4, and instructions 0, 4, and 8 are ITS
1 is executed. Also shown are write lines, write pulses, and output control lines that are activated when each instruction is executed. To execute the above instructions, the program counter 21, timing pulse generator 22, sequencer 23, and instruction decoder shown in FIG. 24 needs to work. less than,
Explain timing. FIG. 6 is a diagram showing the timing of the embodiment of FIG. 2. FIG. 6A shows a sample arrangement of sinusoidal waveforms, and the sampling period of one sinusoidal waveform is 20 μs. FIG. 6B is an enlarged view of 20 μs, in which there are 8×20=160 time slots and 160 samples.
Each sample is processed in 125ns steps. Channel 1 (CH1) has 20 samples. The same applies to CH2 to CH8. On the other hand, Fig. 6C
is the timing at which the jump number J is calculated in synchronization with A. Channel time slots CHS 1 to 8 are provided in units of 160 μs. In CHS1, the J calculation for channel 1 is performed, and the J calculations for the corresponding channels are performed in the following order. J calculation for each channel is repeated at a cycle of 160×8=1280 μs (1.28 ms). Figure 6D
shows the inside of each channel time slot CHS, and as an example, CHS1 is enlarged. In CHS1, there are processing time slots PTS 1 to 32 in units of 5 μs.
For PTSI,I=1 to 20, the number of jumps that determine the frequencies corresponding to 20 spectra (sine waveforms) in channel 1 is calculated. And P.T.S.
In the first half of 2.5μs, the calculated 20 J values are calculated in 125ns steps as shown in Figure 6F.
The signal is transferred to the sine wave generator 9 (FIG. 1). The timing of this transfer differs for CHS1 to CHS8. For example, in CHS8, it is executed in the latter half of PST24.
Figure 6E shows each processing time slot PTS1 to 2.
This is an enlarged version of the contents of 0. PTS1~20
are divided into four parts, instruction time slots ITS1 to ITS4, respectively. Each is 1.25μs long. The instructions in Table 1 above are executed in these instruction time slots ITS. PTS1
~20, in the embodiment of FIG. 2, the ALU
An operation centered on 26 is performed. PTS21
~32, new data is written mainly to MIF25 in Figure 2 to the data bus DB.
and VIB(n), VIB(n-1)
Update data. There are various methods for creating the timing shown in FIG. FIG. 7 and FIG. 8 show an example. Figure 7 shows a timing counter, and 51 is a 14-stage counter with CK as input.
Output P ₀ to P ₁₃ . P ₀ to P ₂ perform binary coded quinary counting, and P ₃ to P ₁₃ perform binary counting.
{P ₅ , P ₄ } are codes representing instruction time slots ITS1 to ITS 4, 5 bits of {P ₁₀ to P ₆ } are codes representing processing time slots PTS 1 to 32, {P ₁₃ ,
P ₁₂ , P ₁₁ } is the channel time slot CH1
It corresponds to a 3-bit code representing ~8. The counter 52 is a 20-decimal counter consisting of five stages, {Q ₄ ,
Q ₃ , Q ₂ , Q ₁ , Q ₀ } are output. Counters 51 and 52 are synchronized. From the outputs of counters 51 and 52, the timing pulse shown in Figure 8 is TPG2.
It is made inside 2. CK has a frequency of 125ns (8MHz). From P ₁ , P ₂ , ₃ , ₄ , ₅ ,
WRC, IST1-4, 1-4 are obtained.
The IST1-4 signals are the output command signal C1 in Fig. 2.
The signal that is the source of ~12, 1~
WRC4 is a signal from which write command signals 0 to 3 are generated. Figure 9 shows the address codes AD3 and AD4 added to the buffer memory 29 and the output command signal C.
9. This is an example of a circuit that generates the write command signal 3. Address code AD4 is {P ₁₃ , P ₁₂ , P ₁₁ },
In AD3, either {P ₁₀ to P ₁₆ } or {Q ₄ to _{Q 0} } is selected by the selector 69. 3 is a processing time slot created by the AND gate 70 with invert input and the OR gate 71 with invert input.
It is 4 corresponding to ITS4 in PTS1-20. AND gates 60, 61, 62, 63 are
Detect {P ₁₀ , P ₉ , P ₈ }={1, 0, 1}. This corresponds to PTS21-24. At this time, the selector 69 selects _Q4 to _Q0 . EXR gates 64, 65, 66 are {P ₇ , P ₆ , P ₅ } and {P ₁₃ ,
P ₁₂ , P ₁₁ }. and gate 6
7 matched CHS number among PTS21-24
Select half interval of PTS and when output is “H”
Output OC9. Therefore, to summarize,
In ITS4 of PTS1-20, AD4 and
AD3 specifies K and I, respectively, outputs 3 at ITS4, and writes instruction 7 or 11 in Table 1 to buffer memory 29 (BUF(K,I)). CHS between PTS21-24=K
C9 becomes “H” for 2.5μs corresponding to
The contents of I=1 to 20 of BUF (K, I) are output according to address codes AD4 and AD3. FIG. 10 shows an example of the format of the instruction code stored in the sequencer 23 in FIG. 2-bit P code for operation,
It consists of a 3-bit destination code that indicates the data transfer or storage destination, a 3-bit source 1 code that indicates the register from which the data is taken out, and a 4-bit source 2 code. The meaning of each code is shown in FIGS. 10B-E. The P code specifies the function of the ALU 26. The operations of the 12 instructions shown in Table 1 are expressed by the instruction codes shown in FIG. Figure 10 E ZER
O means to output ZER to the A bus. Using the same concept as illustrated in Figure 9, based on the instruction code in Figure 10 and the CHS, PTS, ITS, write line, output control line, etc. in Table 1,
The instruction decoder 24 and circuits that generate necessary control signals and timing pulses can be designed. FIG. 11 shows the timing of execution switching between instruction groups A and B in Table 1. From the top, channel time slot, operation execution, J transfer, interrupt pulse, data transfer, and KN flag are shown. Operation A or B is the processing time slot
PTS 1 to 20 (Figure 6) are executed 20 times.
At the end of the 20th time, the interrupt pulse is as shown in Figure 2.
The TPG 22 outputs the signal to the CPU 3 shown in FIG.
At this time, at the same time, CHS8 is used as an interrupt vector.
A code {P ₁₃ , P ₁₂ , P ₁₁ } indicating this is output to the data bus DB in FIG. The CPU 3 reads this interrupt vector {P ₁₃ , P ₁₂ , P ₁₁ } and executes the next
If it knows that CHS is 1 and the pitch to be played on channel 1 is changing, data transfer is performed. Data transfer is performed from the data bus of the CPU 3 to the data bus DB shown in FIG. and,
Predetermined data is written to ND(n) 33, PN 36, INH 37 and status FF 41. In particular, K included in the status FF
Set the N flag flip-flop (FF).
The KN flag indicates that the pitch of the sound corresponding to CHS1 has been changed. When the KN flag is "1", instruction group A is read out and executed during CHS1. When the execution is finished, an interrupt pulse is generated again and an interrupt vector indicating CHS1 is output.
At the same time, KN flag FF is reset. In response to the interrupt pulse and interrupt vector {P ₁₃ , P ₁₂ , P ₁₁ }, the CPU 3 determines whether or not the previous pitch remains the same in the next CHS 2, and if the same pitch should be output, the CPU 3 uses the data. No transfer occurs. Therefore K
The N flag remains at "0". At this time, instruction group B is executed 20 times. Instruction group A is based on new ND(n) data,
In the program for calculating J, instruction group B is a group of instructions that corrects only changes in vibrato data with respect to the previous J. The reading and switching of instruction groups A and B are performed by reading out and switching instructions corresponding to instruction time slots _ITS1 to ITS4 within the time period in which the processing time slot codes {P10 to _P6 } of the counter 51 in FIG. 7 indicate PTS1 to PTS20. This can be done by reading out groups A and B, selecting one using the KN flag, and outputting it. In the embodiment of FIG. 2, the amount of data to be transferred from the CPU 3 to the frequency control device of the present invention is N
A total of 43 words is sufficient, including 1 word for OD(n), 20 words for PN, 20 words for INH, 1 word for status FF, and 1 word for PRT. In the above description, one vibrato data generator 42 is common to eight channels. In case of glide effect, glide data GL(n,K)
and GL (n-1, K), (K = 1, 2, ..., 8) are provided independently for each channel, and each CHS1
By outputting the respective data corresponding to 8, an independent glide can be applied to each channel. In the above explanation, as the buffer memory 29,
Although 160 words have been prepared, one transfer is performed in units of 20 words, so 20 words may be prepared. Regarding the partial number memory 36 and harmonic data memory 35 in FIG. 2, the former may have 13 bits per word, and the latter may have 6 bits per word. The maximum harmonic order is set to 64, but when increasing it, the number of words in the partial number memory must be increased to 64, and 1 of the harmonic data must be increased.
Just increase the number of words from 6 bits. Although the harmonic data may be transferred directly from the CPU 3, the amount of data to be transferred can be smaller in the embodiment shown in FIG. Further, in the embodiment of the present invention, it is possible to omit some of the many harmonic orders to generate a skip number J that is a toothless frequency control value. In addition, partial number memory 3
Although we explained that a different partial number is given to the 20-word RAM of 6, the same partial number can be stored in any plural words, and non-harmonic memory 3
When writing slightly different INH data to 7,
The generation of two or more frequency components of very close frequency becomes possible. In other words, a chorus effect can be obtained. Among keyboard instruments, the pitch of the piano tends to fall in the low range and rise in the high range compared to the keyboard range, and one octave does not have an exact 1:2 frequency ratio. This phenomenon can be called pitch extend. To do this, an RM is provided to generate this shift, and this RM is accessed by the data of ND(n) to output the amount of shift corresponding to the note octave, and this amount is used as the difference address in the ALU
It may be added at 26. Further, the above deviation can also be included in the data written to the non-harmonic memory 37. It goes without saying that in order to generate a musical tone that does not have non-harmonic properties, it is sufficient to write a zero value as INH data. In the above explanation, part of the data is displayed in binary coded ternary notation. instead of this 2
It is also possible to display evolution, 12 evolution, binary evolution, hexadecimal, etc. It is also possible to obtain octave data by displaying and calculating data in complete binary format, and then converting it into binary code and ternary code for higher-order digits, including the note data part. good. For this purpose, a binary-ternary conversion ROM may be provided. In the embodiment shown in FIG. 2, only one register is provided for ND(n). These registers and RAM
If the number of channels is provided for 8 channels, the calculation procedure is A
It gets better just in groups. As described above, there is a relationship between the configuration and the calculation procedure, and there are various types other than those in this embodiment, but a description thereof will be omitted. In the above description, the procedure and configuration are described for calculating the jump number J for sine wave synthesis, but it can also be used for frequency control of a waveform generator that reads out waveforms other than sine waves. For example, instead of 20 harmonic components, J is 1 for one waveform.
Even when only one is generated, an optimal configuration can be made using the same concept as above. <Portamento Effect> In the embodiment shown in FIG. 2, the number of jumps J can be gradually changed in response to the portamento effect. In the embodiment shown in FIG. 2, portamento is applied only to one channel, that is, CHS1. First of all, as mentioned earlier, in portamento mode,
This note octave data is ND(n)33
, the previous note octave data is ND(n
-1) Stored in 34. At the same time, portamento speed and key press interval ND(n)-ND(n-1)
Data representing the increment corresponding to is stored in PRT32. This data is stored as is or after some transformation in the portamento converter. Instruction group C in Table 1 determines whether portamento is increased or decreased. Instruction 0 adds an increment Δ to the previous ND(n-1). For instruction 1, whether the result reached or exactly matched the target value ND(n),
Compare and judge whether you have surpassed it. CP means compare. As a result of this comparison, ALU 26 sets its internal flag FLG. The flags FLG of ALU26 include zero flag Z and sign flag S.
will be established. These flags are attached to a normal adder/subtractor, and the zero flag Z is a flip-flop which becomes "1" when all bits of the operation result are "0" and becomes "0" otherwise.The sign flag S is a flip-flop. , is composed of a flip-flop which becomes "1" when the most significant bit of the operation result is "1" and becomes "0" otherwise. The comparison result of instruction 1,
With △S representing the sign of the increment △, instructions 2 and 3 are
One of the two is executed. Instruction 2 adds △ to the current note octave data ND (n-1) and creates new note octave data ND.
(n-1). Instruction 3 stores the final target ND(n) as a new ND(n-1). With the above instruction group C, in the portamento effect, by adding the increment △, the pitch becomes the target note octave data ND(n).
Determine whether the target value has not been reached, exactly, or exceed the target value, and based on the results,
Increment the frequency on the cent scale of the fundamental wave or harmonics △
The user is asked to select whether to execute the instruction group B that increases the target value ND(n) or the instruction group A that performs an operation at the destination point based on the target value ND(n). FIG. 12 shows which of the instructions 0 to 11 will be executed depending on the combination of three flags ΔS, Z, and S. Instructions 0 and 1 are executed every time. A case where instruction 3 and instruction group A (instructions 4 to 7) are executed by flags Z, S and △S which are the operation results of instruction 1;
It is classified into cases where instruction 2 and instruction group B (instructions 8 to 11) are executed. The former case is a case where the target value ND(n) is exactly reached or exceeded by accumulating the increments Δ. The latter is a case where the target value ND(n) is not yet reached even after accumulating the increments Δ. FIG. 13 is a timing chart in portamento mode. In the processing time slot PTS in which the operation is performed, instruction group C is executed in PTS32, and instruction groups A and B are executed in PTS1-20. An interrupt pulse is generated at the end of PTS20 or the beginning of PTS21 and is sent to CPU3 in Figure 1.
Request new data. At this time, the CHS code {P ₁₃ , P ₁₂ , P ₁₁ } is output to the data bus DB as an interrupt vector, and CPU3
CHS, but you can also find out what the next CHS is. If the key has been changed and it is time to move to a new note octave, CPU 3 will write the new ND(n), the previous N
A group of data of D(n-1), PN, and INH and status flag data are transferred. The status data includes the KN flag,
Set KN flag FF to “1”. In portamento mode, arithmetic processing can be performed regardless of this KN flag. First, just before CHS1
The PTS 32 of the CHS 8 executes instructions 0 to 3 of the instruction group C. However, execution of one of instructions 2 and 3 is ignored due to flags ΔS, Z, and S in FIG. Thereafter, instruction group A or B is executed in PTS1 to PTS20 of CHS1 according to the status of the flags. Reading of instruction group C is performed at the timing when PTS becomes 32, that is, when the processing time slot code {P ₁₀ -P ₆ } becomes {111111}.
The address code indicating 3 may be added to the instructions RM in the sequencer 23 in order, and instructions 0 to 3 may be read out. To ignore one of instructions 2 and 3, set the read instruction output to flags △S, Z, S
All you have to do is gate according to the code. Regarding the selection of instruction groups A and B, the 2 bits of the lower address code for reading instruction groups A and B are selected by {P ₅ , P ₄ } at the timing when the processing time slot codes {P ₁₀ to P ₆ } indicate 0 to 19. By specifying the upper 2 bits of the address code that is generated and distinguishing instruction groups A and B by a combination of flags △S, Z, and S, and adding a 4-bit address, instructions 4 to 7 in instruction RM are 8 to 11 may be selectively read out. FIG. 14 shows an example of an adder in the ALU 26 that performs operations on data having the data structure shown in FIG. Since N ₁ and N ₀ are binary coded ternary numbers, the carry C _S from the lower S ₅ and the N ₁ on the A bus,
With N ₀ and N ₁ , N ₀ on the B bus as inputs, the outputs N ₁ , N ₀ on the C bus and carry C _N to the higher order are determined as shown in the truth table in FIG. 14A. B is an example of hardware. 80 is on the A bus and B bus
Binary adder with 6 bits _S5 to _S0 as input, 82
is a binary adder whose inputs are O ₅ to _{O 0} , N ₃ , and N ₂ on the A bus and B bus, and 81 is a read-only memory (ROM) having a truth table pattern. C _S is 2
The carry of the adder 80, C _N , is the carry output from the ROM 81. Subtractors and comparators can also be constructed using a similar idea. Vibrato data generator 42 in FIG.
may be something like a digital sine wave generator. For example, at the timing of updating the VIB(n) and VIB(n-1), read the RM from the ROM that stores the waveform of the vibrato signal,
It may be possible to write to each register. The octave shifter 30 has a buffer memory 29
By adding multiple sets of codes obtained by shifting the output of 1 bit to the required bit to the respective gates, one set of these gates is converted to {O ₄ , O ₃ ,
The selection may be made using the code O ₂ , O ₁ , O ₀ }. In this example, the octave code has 5 bits, so 2 ⁵ = 32 different octaves can be taken, but the frequency range that humans can hear is from 20KHz to
As 20Hz, it is 10 ³ times 10 octaves, so
There are about 10 possibilities for bit shift. In this case, the MSB O ₄ may be omitted. In Figure 4, the data are 15 from O ₄ to S ₀ .
I thought it would be possible to handle bits. It goes without saying that when the data length is 15 bits or less as shown in FIGS. 4B to 4E, the extra bits above and below it may be arranged with "0"s. For negative numbers,
It differs depending on whether the display is 2's complement or 1's complement, but in the latter, "1" is output at the top and "0" is output at the other bits, and in the former, "1" is output in all upper bits. All you have to do is output it. 1
In the case of the complement of FIG. 4E, sign bit _V6 may be used as the most significant. As mentioned above, in the embodiment shown in FIG.
The jump number J is calculated by calculating each data in the format explained with the drawings in a step-by-step manner. Portamento mode (13th
To switch between the normal mode (Figure 11) and the normal mode (Figure 11), enter the status FF in Figure 2.
Prepare the RMAL/PRTAMETO mode bit, and send "1" to this bit from CPU3 to set it to normal mode, and send "0" to portamento mode, and change the instruction reading according to the mode bit. . In the normal mode, zero is written in the PRT32 (FIG. 2) so that Δ becomes zero. FIG. 15 is another example of index conversion. 3
8 stores J _i,p in EXP38, which is the same as in FIG.
39-1 is a differential ROM having addresses for 7 bits {N ₃ to S ₃ }, and stores differential values (J _i+1,p −J _i,p ) of 96 index sample values. The output is 5
It's bit. 39-2 is 3 of {S ₂ , S ₁ , S ₀ }
This is a simplified multiplication RM for outputting an interpolated value of a difference value according to the bit. That is,
(J _i+1,p − J _i,p )×j/8 is stored. If you do this, the quantization error will increase a little, but the memory size will change from 768 x 5 = 3840 bits to 96 x 5 + 2 ^{5 + 3}
×5 = 1760 bits. In FIG. 3A above, one octave is assigned to 2048 to 4095. Therefore, it is 12 bits. In this case, the 12 equal temperament notes will be within an error of ±0.78125 cents. However, at low frequencies, the bits are shifted according to the octave code, and it is also conceivable that the bits are shifted to the lower side. At this time, the lower 12 bits are truncated, sometimes resulting in 8 to 9 bits. At this time, the above error increases. For 9 bits, 3
Since it was bit shifted, the error is 8 times ±
It becomes 6.25 cents. However, as is well known, in 9 bits, 239, 253, 268, 284, 301,
For the combination of 12 numbers 319, 338, 358, 379, 402, 451, the error from 12 equal temperament is less than ±1.2 cents. Therefore, instead of 2048, let C be 253×8=2024, and 239×16=
If 3824 is B, it is possible to convert a cent address to an interlaced number with the highest precision using 12 bits. To summarize the present invention, at least one octave section is divided into a plurality of sections having equidistant cent intervals, and a cent address is given to each section boundary point, and a single or multiple frequency components of a musical tone to be generated are divided into sections. By expressing the frequency with the address value of the above-mentioned cent address and giving the above-mentioned address to a converter having approximately exponential conversion characteristics, a frequency control value that approximates the above-mentioned frequency of the musical tone to be generated is obtained. be. Here, in the embodiment, what divides at least one octave interval into a plurality of intervals having equal cent intervals and gives cent addresses to the interval boundary points is the exponent conversion table 38 or the exponent conversion table 38. This is a difference index conversion table 39. By inputting the address values set by this table to the frequency control device of the present invention, an interlace number that is desired frequency information is generated. A converter with approximately exponential conversion characteristics is
For example, an index conversion table 38, a differential index conversion table 39, an arithmetic unit (ALU) 26, a working register (WREG) 27, a RAM 28, a program counter 21 that controls them, a timing pulse generator 22, a sequencer 23, an instruction decoder 24, etc. Consisted of. As is clear from the above description, the present invention provides means for generating pitch information of a musical tone to be generated (in the embodiment, the note octave registers 33, 3
4), means for generating harmonic information corresponding to the harmonic frequency of the musical tone corresponding to the timbre information of the musical tone to be generated (in the embodiment, the partial number memory 36 and the harmonic data memory 35); Means (in the embodiment, ALU 26, working register 27, RAM
28, and a program counter 21, a timing pulse generator 22, a sequencer 23, an instruction decoder 24) that control them, and an approximate system that takes the above cent address as input and converts it into a frequency control value corresponding to the above cent address. A converter having index conversion characteristics (in the embodiment, an index conversion table 38, a differential index conversion table 39, an arithmetic unit (ALU) 26, a working register (WREG) 27, a RAM 28, a program counter 21 that controls them, and a timing pulse) generator 22, sequencer 23,
an instruction decoder 24), which divides at least one octave section into a plurality of sections having equidistant cent intervals, assigns cent addresses to the boundaries thereof, generates the pitch information as the cent addresses of the boundaries, and generates the pitch information as the cent address of the boundaries; Generate harmonic information as a difference address between cent addresses, obtain the sum cent address of the pitch information and harmonic information, and supply the sum cent address to the converter to obtain the fundamental frequency and harmonic frequency of the musical tone. Since the frequency control value representing each of It has the characteristic that it requires only a small number of digits.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a digital electronic musical instrument to which the present invention is applied, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of an index conversion table, and Fig. 4 is a diagram of the above embodiment. FIG. 5 is a diagram showing an example of the data format used in the above embodiment, FIG. 6 is a diagram showing an operation timing chart of the above embodiment, and FIG. 7 is a diagram showing a counter for timing pulse generation. 8 is a diagram showing a timing pulse chart, FIG. 9 is a diagram showing a decoder, FIG. 10 is a diagram showing an example of an instruction code format, and FIG. 11 is a general timing chart in normal mode. , FIG. 12 is a diagram showing the instruction execution pattern in portamento mode, FIG. 13 is a diagram showing the global operation timing chart in portamento mode, FIG. 14 is a diagram explaining the operation of the adder, and FIG. 15 is an exponent diagram. It is a figure which shows an example of a conversion table. 1...Keyboard section, 2...Operation section, 3...CPU,
4...RAM, 5...RM, 6...Envelope parameter ROM, 7...Frequency parameter
ROM, 8... Frequency control device, 9... Sine wave generator, 10... Envelope data generator, 11
... Multiplier, 12 ... Time slot control device,
13...Phase modulator, 14...Digital-to-analog converter, 21...Program counter, 22...
...Timing pulse generator, 23...Sequencer, 24...Instruction decoder, 25...Microcomputer interface circuit, 26...Arithmetic unit, 27...Working register, 28...RAM, 29...Buffer memory, 30... ...octave shifter, 31
... Portamento data converter, 32 ... Portamento register, 33, 34 ... Note octave register, 35 ... Harmonic data memory, 36 ... Partial number memory, 37 ... Non-harmonic memory, 38 ... Exponential conversion table, 39
...Difference index conversion table, 40...Gate, 4
1...Stator flip-flop, 42...Vibrato data generator.

Claims (1)

[Scope of Claims] 1. Means for generating pitch information of a musical tone to be generated, means for generating harmonic information corresponding to a harmonic frequency of the musical tone corresponding to timbre information of the musical tone to be generated, and the above-mentioned means for generating a cent address corresponding to the fundamental frequency and harmonic frequency of a musical tone to be generated by combining pitch information and harmonic information; and a means for generating a cent address corresponding to the fundamental frequency and harmonic frequency of a musical tone to be generated; a converter having approximate exponential conversion characteristics for conversion, divides at least one octave section into a plurality of sections having equally spaced cent intervals, assigns cent addresses to the boundaries thereof, and converts the pitch information into generate the above-mentioned boundary cent address, generate the harmonic information as a difference address between the cent addresses, obtain the sum cent address of the pitch information and the harmonic information, and supply the sum cent address to the converter. A frequency control device characterized in that frequency control values representing each of the fundamental frequency and harmonic frequency of the musical tone are obtained by using the above-described method. 2. A means for generating pitch information corresponding to the pitch frequency of the musical tone to be generated, and a positive harmonic corresponding to a positive harmonic frequency in the vicinity of the harmonic frequency of the musical tone corresponding to the timbre information of the musical tone to be generated. means for generating wave frequency information, means for generating non-harmonic information representing the amount by which said harmonic frequency deviates from said positive harmonic frequency, and modulation information representing frequency shifts due to vibrato, glide, portamento, etc. at least one
Divide the octave section into multiple sections with equally spaced cent intervals, assign cent addresses to the boundaries, generate the pitch information in the form of the cent addresses, and convert the positive harmonic frequency information to the positive harmonic frequency information. output in the form of a positive harmonic difference cent address representing a cent value corresponding to the ratio of the frequency and the pitch frequency, and output the above-mentioned non-harmonic information in the form of a non-harmonic difference cent address corresponding to the deviation. , generate the above modulation information in the form of a modulated cent address, add the above cent address to obtain a sum cent address,
The sum cent address is applied to the converter to obtain the frequency control value, the converter receives the cent address assigned to the boundary as input and outputs corresponding frequency control information, and the at least one octave For cent address input outside the interval, the deviation from the above interval is obtained as the upper octave data of the cent address, and the digit of the output of the converter is shifted according to this octave data, thereby achieving wide range frequency control. A frequency control device designed to obtain a value.