JPH0523524B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a synchronous signal selection output method for extracting a frequency-stable signal in synchronization with a trigger.

(Prior Art) Conventionally, in the calibration of measuring instruments, for example, the adjustment work to accurately determine the repetition period of a measuring clock,
The measurement clock of the measuring instrument and a reference clock with a known repetition period are displayed vertically on a two-sample ascilloscope, and by shifting the rising or falling position of the reference clock horizontally on the screen, the phase of the reference clock can be adjusted. After making the measurement clock match the measurement clock of the measuring device, the measurement device is adjusted to make the repetition period of the measurement clock match the reference clock.

In calibrating such measuring equipment, in order to match the phase of the reference clock with the measurement clock,
A synchronization signal selection output means is required which inputs a trigger at an appropriate phase position of the measurement clock and generates a reference clock of a predetermined frequency with a phase synchronized with the trigger.

Generally, it is relatively difficult to extract a signal whose frequency and phase are always constant relative to the trigger. For example, when a crystal resonator is used to increase frequency stability, there is a problem that the time required from when a trigger signal is input until the amplitude and frequency of the output signal of the oscillator become stable is not constant. on the other hand,
If you use an LC or RC oscillator for synchronization, you will be able to achieve synchronization, but you will not be able to achieve frequency accuracy. Also, the initial synchronization of the output signal may differ from the steady state synchronization.

Next, in the synchronous signal selection output method, a crystal oscillator is continuously oscillated, and when a trigger signal is received, the output is taken from the falling edge of the trigger.
The output frequency is very stable, but as shown in Figure 13, when the period of this oscillation output is T(S), the output of the crystal oscillator starting from the trigger is:
Depending on the relative point in time at which the trigger is applied within one cycle (see Figure 13), the maximum
This causes a synchronization shift (jitter) of a period T(S) (see FIG. 13). Due to this jitter,
On the screen, as shown in Figure 14, it becomes difficult to distinguish between HI and LOW, making it impossible to perform calibration.

(Problems to be Solved by the Invention) A method for improving frequency stability and reducing jitter is to continuously oscillate a crystal oscillator with an integral multiple of the required frequency, and when a trigger is received,
It is conceivable to construct a circuit so as to start frequency division by 1/(integer multiple). FIG. 15A shows a case where a crystal oscillator with a frequency four times the required frequency is used, and frequency division by 1/4 is started when a trigger is received. In addition, Figure 15 b is
This example shows a case where a crystal oscillator () with a frequency 16 times the required frequency is used, and when a trigger is received, it starts dividing the frequency by 1/16. are the output waveforms obtained from each synchronization signal selection output method, the vertical stripes indicate jitter, and the times t ₁ and t ₂ of the jitter are t ₁ = 1/4 and t2 = 1/16.
As is clear from the comparison with
It decreases to 1/(the oscillation frequency of the crystal oscillator which is an integer multiple).

However, the cutoff frequency of the active element is finite, and the highest frequency that can be used is subject to this restriction. In other words, it is a frequency that can control the frequency division operation, for example, to start frequency division after receiving a trigger, or to stop frequency division for a necessary time and maintain a constant state. naturally has an upper limit and cannot be set to a very high frequency. Therefore, there is a limit to the reduction of jitters.

(Object of the Invention) The present invention has been made to solve such problems, and an object of the present invention is to provide a synchronization signal selection output method that can easily achieve the necessary phase accuracy using general-purpose active elements. .

(Structure of the Invention) The synchronization signal selection output method of the present invention receives a reference signal that is m times the repetition frequency of the required output signal (m is an integer of 2 or more), and shifts the phase of the reference signal. Create n sub-reference signals (n is an integer of 2 or more) with different phases, input them individually to a presettable 1/m frequency divider prepared for each sub-reference signal, and divide these n sub-reference signals into A trigger is applied to the preset input terminals of the frequency dividers all at once, and from the moment this trigger is applied, each frequency divider divides each of the above sub-reference signals into 1/m, and the output signal of each frequency divider is divided into n.
The input signal is input to an input AND gate, and an output signal is taken out from the AND gate.

Further, another synchronization signal selection output method of the present invention is as follows:
By receiving a reference signal m times (m is an integer greater than or equal to 1) the repetition frequency of the required output signal and shifting the phase of the reference signal, n substations with different phases (n is an integer greater than or equal to 2) can be generated. Create a reference signal, input these individually to a presettable 1/(2m) frequency divider prepared for each sub-reference signal, and apply a trigger to the preset input terminals of these n frequency dividers all at once. From the time this trigger is applied, each sub-reference signal is divided into 1/2m by each frequency divider, and the non-inverted output signal of each frequency divider is input to the first n-input AND gate. The inverted output signal of the frequency divider is input to the second n-input AND gate, the outputs of both AND gates are input to the OR gate, and the output signal is taken out from the OR gate.

(Example) The present invention will be explained below with reference to the illustrated embodiments.

In Figure 1, 1 is a clock generator configured to use a crystal resonator to generate a clock signal (reference signal) SA with a repetition frequency A of necessary accuracy, and 2 is a clock generator that generates a trigger signal G. It is a trigger generator. Reference numeral 3 designates an input terminal that receives the reference signal SA from the clock generator 1, 4 an input terminal that receives the trigger signal G, and 5 an output terminal from which the output signal S of the required repetition frequency is taken out. The repetition frequency 0 of the input reference signal S0 is
It is an integer multiple of the repetition frequency of the output signal S to be extracted, and 0 = m (m is an integer of 2 or more)
There is a relationship between 10 is a delay device for sequentially delaying the phase of the reference signal S0 from the clock generator 1 by 1/n (n is an integer) and dividing it into n sub-reference signals; 20 is a selection circuit; , each of the n sub-reference signals appearing at the output terminals "1" to "n" of the delay device 10 starts to be divided by 1/p (p is an integer) in synchronization with the trigger signal G. It consists of a frequency dividing circuit 21 consisting of a frequency divider, and an AND circuit 22 which calculates the AND of the outputs of the n frequency dividers and outputs the result to the terminal 3. As described later, the jitter t of the output signal S with respect to the trigger is t=1/(×
n), and the larger n is, the smaller the jitter is.

In FIG. 1, the nth output of the delay device 10 is in phase with the reference signal S0, whereas the first
The th output is a signal delayed by one period with respect to the input reference signal S0. Therefore, the delay device 10
whose first delay output terminal is the reference signal
This is a terminal that directly outputs S0 without delay.
The second and subsequent delay output terminals may sequentially output delayed outputs, and the final stage delay output terminal may output the (n-1)th delayed output.

First, as a first embodiment, m times the repetition frequency of the required output signal (m is an integer of 2 or more).
By receiving the reference signal of with a frequency divider of 1/m
A synchronizing signal selection output method will be described in which the frequency is divided into 1/p=1/m, and the output signal is obtained by ANDing the outputs of each frequency divider.

FIG. 2 shows a specific circuit in the case of m=p=2 and n=3. That is, the reference signal S0 with repetition frequency 2
This is an example of a circuit in which three sub-reference signals SA, SB, and SC are created by sequentially delaying the phase by 1/3, and their frequency is divided by 1/2 using three frequency dividers. . The delay device 10 includes two delay circuits DL1,
It is configured by cascading DL2, and the selection circuit 2
0 frequency divider circuit 21 is composed of 1/2 frequency dividers 23, 24, 25 each consisting of presettable flip-flops FF1, FF2, FF3, and AND circuit 22 is composed of these flip-flops FF1, FF3.
It is composed of an AND gate 26 having three inputs, Q outputs of FF2 and FF3. 1 to 8 in FIG. 6 show the operation of each part of the circuit in FIG. 2.

Set the desired repetition frequency as the output signal S.
When the frequency is 2MHz, the reference signal S0 with a repetition frequency of 2 (4MHz) is input as it is from the delay device 10 to the clock input CK of the FF1 as the sub-reference signal SA, and on the other hand, the phase is sequentially inputted through the delay circuits DL1 and DL2. After being shifted, the sub reference signal SB,
The signals are input as SC to frequency dividers 23, 24, and 25, respectively. The sub reference signals SA, SB, and SC are out of phase with each other by 1/3 of one period (2 to 4 in FIG. 6). Now, trigger signal G is input to terminal 4,
Therefore, when the inverted signal is applied from the inverter 27 to the preset input PR of flip-flops FF1, FF2, and FF3, each flip-flop is preset by the falling edge of the trigger signal G (the rising edge in the case of the inverted signal shown in FIG. 6). (Point a in Figure 6). That is, the Q outputs of FF1, FF2, and FF3 are:
Sub reference signal input to clock input terminal CK
It is reversed each time SA, SB, and SC fall,
Start frequency division by 1/2 (5) to 7) in Fig. 6).
AND gate 26 is connected to these FF1, FF2, FF3
The Q output of , that is, the signal after frequency division by 1/2 (2MHz) is ANDed and outputted to terminal 5 as output signal S (8 in FIG. 6).

The repetition period T of this output signal S is 2 in FIG.
As is clear from ~8, the period of the sub-reference signal
This is twice the period of TA, TB, and TC (that is, the period of the reference signal S0), and therefore, the desired repetition frequency (2 MHz) can be obtained as the output signal S. On the other hand, regarding jitter, 1 of the reference signal S0
Sub reference signals SA, SB, SC shifted by 1/3 of the period
, the jitter is also reduced to 1/3 compared to simply using a single signal with a repetition frequency of 0 times twice. Moreover, the first fall of the output signal S is obtained based on the sub-reference signal SA, which has the earliest temporal relationship to the rise time of the trigger signal among the three sub-reference signals SA, SB, and SC. However, the AND gate 26 has FF1, FF2,
It is clear that the outputs of FF3 may be ANDed.

FIG. 3 shows a specific circuit example in the case where m=p=3 and n=3. The difference from the circuit shown in FIG. 2 is that frequency dividers 23, 24, and 25 are configured as 1/3 frequency dividers. That is, each frequency divider 23, 2
4 and 25 are sub reference signals SA, SB, and
A presettable first flip-flop 231 receives one of the clocks SC at its clock input terminal CK.
, a presettable second flip-flop 232 which receives the Q output of the flip-flop at its clock input terminal CK, and a first flip-flop 232.
31 and the second flip-flop 232
The output of the NAND gate is connected to the preset input terminals of both flip-flops 231 and 232 via a NOR gate 234 and an inverter 27.
Entered in PR. The trigger signal G is applied from the other input terminal of the NOR gate 234 to the preset input terminal PR of both flip-flops 231 and 232.
is input.

1 to 8 in FIG. 7 show the operation of each part of the circuit in FIG. 3. As is clear from the relationship between 1 to 4 and 8 in Figure 7, even when m = p = 3, which is an odd number, the same effect as when it is an even number, such as mm = p = 2 in Figure 2, is obtained. is obtained. That is, the desired repetition frequency is obtained as the output signal S, and the first fall of the output signal S is caused by the three sub-reference signals SA,
Of SB and SC, it is obtained based on the sub-reference signal SA, which has the earliest temporal relationship to the rise time of the trigger signal. Of course, jitter also depends on the number n of sub-reference signals.
corresponds to 1/3.

Next, as a second embodiment, m times the repetition frequency of the required output signal (m is an integer of 1 or more)
By receiving the reference signal of The frequency is divided into 1/2m (i.e., 1/p = 1/2m) using a frequency divider, and the logical product of the inverted signals and the logical product of the non-inverted signals of the output of each frequency divider is output. A synchronization signal selection output method that extracts the logical sum of the signals as an output will be explained.
As is already clear, this method works when p is an even number.

FIG. 4 shows a specific circuit example in the case of m=1, n=3, and p=2. In terms of the circuit, the circuit of FIG. 4 has a 1/2 frequency divider 23,
Flip-flop FF comprising 24 and 25
Not only the Q outputs of FF1, FF2, and FF3 are ANDed by the first AND gate 26, but also the outputs are ANDed by another second AND gate 28.
The outputs of both AND gates 26 and 28 are connected to OR gate 29
The configuration is such that the output is output to the terminal 5 through the terminal 5.

1 to 13 in FIG. 6 show the operation of each part of the circuit in FIG. 4. 9 to 11 in this figure are the frequency divider 2
FF1, FF2, which constitutes 3, 24, 25,
This is the output of FF3, and has the inverted waveform of the Q output described above. Further, 12 indicates the output waveform of the AND gate 28, and 13 indicates the output waveform of the OR gate 29.

As is clear from the relationship between 1 to 4 and 13 in FIG. 6, the repetition period T of the output signal S obtained from this OR gate 29 is equal to the period TA of the sub-reference signal,
It is the same as TB and TC (that is, the period of the reference signal S0). Therefore, it is sufficient to use the reference signal S0 having the same repetition frequency as the repetition frequency of the output signal S. For example, when the repetition frequency desired for the output signal S is 2 MHz, a 2 MHz signal may be used as the reference signal S0. This also means that in the circuit of FIG. 4, the reference signal with a lower repetition frequency than in the configurations of FIG. 2 and FIG.
This means that S0 can be used. Nevertheless, the jitter decreases by 1/corresponding to the number n of sub-reference signals.
Of course, it has the effect of reducing the output signal S to 3.
The first fall of the three sub-reference signals SA, SB,
Among the SCs, it is obtained based on the sub-reference signal SA, which has the earliest temporal relationship to the rise time of the trigger signal.

As shown in FIG. 5, in the circuit shown in FIG. It is also conceivable to take a configuration in which the output and the output of the AND gate 26 are outputted through the OR gate 29. However, in this case, 1 to 1 in Figure 7
13, in the output waveform of the OR gate 29, the number of pulses is doubled, but the falling positions of the pulses occur at different intervals in time, and the repetition frequency is not doubled. This is inconvenient from the perspective of using it as a scale. However, if the output of the OR gate 29 is passed through the flip-flop 30 again as shown in FIG.
An output signal that can be used as a reference scale can be obtained.

FIG. 8 shows a specific circuit example in the case of m=2, n=3, and p=4. This circuit of FIG. 8 is similar to the circuit of FIG.
2, FF3 and flip-flops FF4, FF5,
By cascading FF6, the frequency divider 23,
24 and 25 are configured as a 1/4 frequency divider. 1 to 13 in FIG. 9 show the operation of each part of the circuit in FIG. 8. 5-7 and 8-10 in this figure
are the Q outputs of the first flip-flops FF1 to FF3 and the Q outputs of the second flip-flops FF4 to FF6, which constitute the 1/4 frequency dividers 23, 24, and 25, and 11 and 13 are the AND26, 2
8 shows the output waveform, and 13 shows the output waveform of the OR gate 29.

As is clear from the comparison with 2 to 4 in FIG. 9, the repetition period T of the output signal S obtained from this OR gate 29 is the period TA, TB, TC of the sub-reference signal.
(that is, the period of the reference signal S0), and the output signal S becomes a pulse signal with a duty of 50%. Therefore, the repetition frequency 2 (4M
Hz), an output signal S with a repetition frequency (2 MHz) can be obtained and can be used as a reference scale for calibration. Also, the hatched portion t shown at the time after the trigger signal G
is a jitter, and this jitter t is a reference signal
The number is reduced to 1/3 corresponding to the number n of sub-reference signals obtained by phase-dividing S0. Furthermore, the first falling edge of the output signal S is caused by the three sub-reference signals SA, SB, SC.
Among these, the sub-reference signal SA is obtained based on the sub-reference signal SA, which has the earliest temporal relationship with the falling point of the trigger signal G.

Moreover, the circuit of FIG. 8 has a great advantage not seen in the circuits of FIGS. 2 to 4. That is, in the circuits of FIGS. 2 to 4, as m increases, the width of the output pulse output to the AND gate 26 or 28 decreases, and therefore there is a limit to its operating frequency. On the other hand, in the circuit of FIG. 8, the pulse width is widened by the second flip-flop, so that it is possible to handle a repetition frequency that is one step lower and perform the AND operation.
Therefore, in conventional circuits that do not perform phase division, and in the circuits shown in Figures 2 to 4 that divide the sub-reference signal by performing phase division, special active elements with high cutoff frequencies are required. Even in the frequency domain where it is necessary to output the synchronization signal, it is possible to perform the same synchronization signal selection output operation using general-purpose active elements.
A simple and practical synchronization signal selection output circuit can be realized.

FIG. 10 is a circuit diagram in which the number n of phase divisions is increased. As the number n of phase divisions increases in this way, the jitter t decreases to t=1/(0・n) corresponding to the number of phase divisions, that is, the number n of sub-reference signals, and approaches infinity. and t like 14 in Figure 9.
=0.

(Effects of the Invention) As described above, the present invention receives a reference signal that is m times the repetition frequency of the required output signal (m is an integer of 2 or more) and shifts the phase of the reference signal. This is because it creates two or more sub-reference signals with different phases, starts dividing these sub-reference signals into 1/m when a trigger is received, and extracts the AND of the divided signals as an output. , Jitsuta,
Corresponding to the number of phase divisions, that is, the number of sub-reference signals n, t=
The output signal is reduced to 1/(0·n), and an output signal with the same level of small jitter as in the case without phase division can be obtained by simply handling a frequency of 1/n.

Another invention of the present invention is to receive a reference signal m times the repetition frequency of the required output signal (m is an integer of 1 or more), and to shift the phase of the reference signal to produce two or more sub-channels with different phases. Create a reference signal,
2m from the time of receiving the trigger.
The circuit starts to divide the frequency by a factor of 1, outputs the logical product of the inverted signal and the logical product of the non-inverted signal of each signal after frequency division, and outputs the logical sum of both the logical product signals. Since the device operates at a frequency lower than the cut-off frequency of the active device used, it is possible to easily extract an output signal with the desired accuracy using a general-purpose active device.

The present invention can be applied to various uses.

Application example 1 In the calibration of the measuring equipment mentioned at the beginning of this specification, that is, the adjustment work to accurately determine the repetition period of the measuring clock, the reference clock that should be displayed on the two-sample oscilloscope together with the measuring clock of the measuring equipment is used. It can be used to create.

Application example 2 This is an application to synchronous detection. For example, in a color television receiver, in order to demodulate and extract the color signal from the carrier color signal, it is necessary to add a reference subcarrier to the demodulator, so bursts are used to add the reference subcarrier within the receiver. Must be made. Therefore, a color synchronization circuit creates continuous subcarriers that have the same frequency and phase as the burst. In this case, the frequency of the subcarrier on the transmitting side is very stable, with a deviation of 3579545 Hz ± 10 Hz, and fluctuations within ± 0.1 Hz per second. Therefore, in the color synchronization circuit of the receiver, it is necessary to create a reference subcarrier that is not only stable in frequency but also stable in phase accuracy within about ±5°. The present invention can be used to create a signal for synchronous detection such as this reference subcarrier.

If such a reference subcarrier is conventionally
If you try to obtain the above frequency deviation, fluctuation error, and phase accuracy by simply increasing the frequency received by the synchronization signal selection output circuit, the minimum frequency required is a phase accuracy of ±5°. , =3579545×(360/5)≒258MHz, that is, approximately 258MHz.

However, if five types of phases are prepared according to the present invention, the minimum frequency to achieve the necessary phase accuracy is: =258×(1/5)×(1/3579545)≒14.4MHz, that is, 14.4 MHz, and can be easily realized.

It is believed that a color television receiver that performs synchronous detection according to the present invention will require almost no color adjustment.

Application example 3 In the color television transmitters currently used in Japan, 8 to 12 cycles of the color subcarrier as shown in Figure 11 are used as a color burst.
It is inserted into the back pouch of each horizontal sync pulse. As mentioned above, this burst signal is absolutely necessary to perform synchronous detection.
However, according to the present invention, it is possible to extract a signal with high frequency accuracy in synchronization with the trigger.
This burst portion can be replaced with a trigger signal (one pulse signal), and the operation is more stable.

Application Example 4 If the circuit according to the present invention is used as it is in a horizontal axis (time axis) deflection circuit of an oscilloscope, an oscilloscope with very accurate time axis can be obtained.

Application Example 5 According to the present invention, it is possible to easily extract a signal synchronized with the trigger, so as shown in FIG. This allows information to be easily sent and retrieved. Also,
Varying the frequency of the carrier wave (in this case,
By changing the trigger signals and combining them so that they can be understood by the receiver, more information can be sent.

[Brief explanation of the drawing]

Fig. 1 is a basic principle diagram of the synchronization signal selection output method of the present invention, Figs. 2 and 3 are circuit diagrams according to the first embodiment, and Fig. 2 shows the 1/2 frequency division. FIG. 3 is a diagram for frequency division by 1/3, FIGS. 4 and 5 are circuit diagrams according to the second embodiment, and FIG. 4 is a diagram for frequency division by 1/2. Figure 5 is a diagram for frequency division by 1/3, Figure 6 is a time chart showing the operation of the circuits in Figures 2 and 4, and Figure 7 is the circuit in Figures 3 and 5. FIG. 8 is a circuit diagram for dividing the frequency by 1/4 according to the second embodiment. FIG. 9 is a time chart diagram showing the operation of the circuit in FIG. 8. FIG. 10 is a time chart diagram showing the operation of the circuit in FIG. A circuit diagram in which the number of phase divisions is increased in the circuit diagram for frequency division by 1/4 according to the second embodiment, FIG. 11 is a diagram showing a color video signal from the color TV transmission side,
FIG. 2 is a diagram for explaining a transmission method to which the present invention can be applied, FIG. FIG. 14 is a diagram showing the jitter that appears between Brown in this case, and FIG. 15 is a diagram for explaining how the jitter decreases as the frequency of the input signal increases in the conventional system. 1... Clock generator, 2... Trigger generator, 3, 4... Input terminal, 5... Output terminal, 10
...delay device, 20... selection circuit, 21... frequency dividing circuit, 22... AND circuit, 23, 24, 25...
Frequency divider, 26...AND gate, 27...Inverter, 28...AND gate, 29...OR gate.

Claims (1)

[Claims] 1. By receiving a reference signal m times the repetition frequency of the required output signal (m is an integer of 2 or more) and shifting the phase of the reference signal, n (n is 2
Create sub-reference signals with different phases (an integer greater than or equal to
A trigger is applied to the preset input terminals of the frequency dividers all at once, and from the moment the trigger is applied, each frequency divider divides each of the above sub-reference signals into 1/m, and the output signal of each frequency divider is is input to the n-input AND gate,
A synchronous signal selection output method characterized by extracting an output signal from the AND gate. 2 By receiving a reference signal m times the repetition frequency of the required output signal (m is an integer of 1 or more) and shifting the phase of the reference signal, n (n is 2
Create sub-reference signals with different phases (an integer greater than or equal to A trigger is applied to the input terminals all at once, and from the moment the trigger is applied, each frequency divider divides the frequency of each of the above sub-reference signals to 1/2m, and the non-inverted output signal of each frequency divider is divided into the first n input
and inputting the inverted output signal of each frequency divider to a second n-input AND gate,
Input the outputs of both AND gates to the OR gate and
A synchronous signal selection output method characterized by extracting the output signal from an OR gate.