JPH0523647B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to logic circuits, and more particularly to a latch circuit and a flip-flop circuit using the latch circuit. [Technical background of the invention and its problems] Conventionally, a latch circuit (Transperent Latch)
For example, it is configured as shown in FIG. 21a.
That is, the input data DI is input to the input terminal D of the clocked inverter 11 controlled by the clock signal φ.
is supplied to The output end of this clocked inverter 11 is connected to the input end of an inverter 12, and also the output end of a clocked inverter 13 controlled by a clock signal. The output terminal of the inverter 12 and the input terminal of the clocked inverter 13 are connected, and a latch output DO is obtained from the output terminal Q of the inverter 12. FIG. 21b shows the above-mentioned
Figure 3 shows a block diagram of the circuit of Figure a. FIG. 22 shows a master-slave type D flip-flop circuit constructed by cascading two stages of the latch circuits shown in FIG. 21a. FIG. 23 shows a D configured by continuously connecting clocked inverters 14 ₁ , 14 ₂ and inverters 15 ₁ , 15 ₂ controlled by a clock signal φ, respectively.
type flip-flop circuit, and the above-mentioned second
Clocked inverters 13 ₁ , 13 ₂ in Figure 2
is removed. Figures 22 and 2 above
The flip-flop circuit shown in FIG. 3 is represented by a block diagram as shown in FIG. A shift register can be constructed by continuously connecting such D-type flip-flop circuits in a plurality of stages as shown in FIG. In FIG. 25, each D-type flip-flop 16 ₁ , 16 ₂ . . . 16n receives a clock signal φ
Data is sequentially shifted to the next stage at the falling edge of . As mentioned above, latch circuits are basic circuits such as flip-flop circuits and shift registers. Incidentally, the above-mentioned D-type flip-flop circuit is widely used in computer registers, etc., but as the operating speed of computers increases, it is desired that the above-mentioned D-type flip-flop circuit also be faster. In particular, such requirements are strong for registers forming the stages of supercomputers operating in pipeline processing. However, the above configuration has the disadvantage that it cannot sufficiently meet the above-mentioned high speed requirements. This is a problem with the clocked inverters that constitute the latch circuits and flip-flop circuits. This will be explained in detail below. A clocked inverter consists of P-channel MOS transistors connected in series between power supplies V _DD and V _SS as shown in Figure 26.
Q ₁ , Q ₂ and N-channel MOS transistors
It consists of Q ₃ and Q ₄ . A clock signal φ is supplied to the gates of the MOS transistors Q ₁ and Q ₄ , respectively, and the MOS transistors Q _{2 and} Q 4 are supplied with a clock signal φ, respectively.
Input data DI is supplied to the gate of _Q3 .
Then, output data DO is obtained from the connection point between the MOS transistors Q ₂ and Q ₃ . When a D-type flip-flop as shown in FIGS. 22 and 23 is constructed using a clocked inverter with the above configuration, the input data DI
In order to latch the clock signal φ must be “1”.
output node of clocked inverter ₁₁₁ or ₁₄₁ within the period of “0” level.
It is necessary that N ₁ and N ₂ reach the circuit threshold value V _M of the inverter 12 ₁ or 15 ₁ , respectively. Therefore, there is a limit to increasing the frequency of the clock signal φ. Furthermore, even if the potentials of nodes N ₁ and N ₂ reach the circuit threshold value _VM , if the clock signal φ reaches the "0" level before each node N ₁ and N ₂ is sufficiently precharged or discharged, , it takes time to drive the gate of the next stage, causing a decrease in operating speed. Furthermore, if the threshold voltage of the P-channel MOS transistors Q ₁ and Q ₂ that make up the clocked inverter becomes lower than the set value due to manufacturing process reasons or during use (e.g. -0.8V
), the drive ability of the P-channel MOS transistors Q ₁ and Q ₂ drops significantly, making it impossible to bring the output node to the "1" level in a short time, and the operating speed decreases. This results in a decrease in performance and reliability. [Object of the Invention] This invention has been made in view of the above circumstances, and its purpose is to provide a latch circuit that is capable of high-speed operation, has a wide operating margin, and has high reliability, and to provide a latch circuit that can operate at high speed, has a wide operating margin, and has high reliability. An object of the present invention is to provide a flip-flop circuit using the circuit. [Summary of the Invention] That is, in the present invention, in order to achieve the above object, the latch circuit of the first invention has a first clocked gate and an output terminal connected to the input terminal of the first clocked gate. a second clocked gate having an input terminal connected to the output terminal and controlled by the same clock signal as the first clocked gate; and a second clocked gate controlled by the control signal and supplying data to the input terminal of the first clocked gate. a first data transfer gate; and a second data transfer gate that is controlled by the control signal and supplies data in phase opposite to the data to the input terminal of the second clocked gate; It is characterized in that latch outputs having mutually opposite phases are obtained from the output ends of one clocked gate. The flip-flop circuit according to the second invention includes a first clocked gate controlled by a first clock signal, an output terminal connected to the input terminal of the first clocked gate, and an input terminal connected to the output terminal. a second clocked gate controlled by the first clock signal; a first data transfer gate controlled by the first control signal for supplying data to an input of the first clocked gate; a second data transfer gate that is controlled by a control signal and supplies data in phase opposite to the data to the input terminal of the second clocked gate;
A third clocked gate controlled by the second clock signal, an output terminal connected to the input terminal of the third clocked gate, and an input terminal connected to the output terminal, and controlled by the second clock signal. a fourth clocked gate which is controlled by a second control signal and which supplies a first latch signal outputted from the output terminal of the second clocked gate to the input terminal of the third clocked gate. a data transfer gate; and a fourth data transfer that is controlled by the second control signal and supplies a second latch signal output from the output of the first clocked gate to the input of the fourth clocked gate. The fourth and third clocked gates are characterized in that outputs having mutually opposite phases are obtained from the output terminals of the fourth and third clocked gates. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1a shows an example of the construction of a latch circuit, and FIG. 1b shows its block diagram. Data DI of opposite phase is supplied to the input terminals of clocked inverters (data transfer gates) 17 ₁ and 17 ₂ controlled by a clock signal φ, respectively. The above clocked inverters 17 ₁ , 17 ₂
A clocked inverter (clocked gate) ₁₈ controlled by a clock signal is connected between the output terminals of the
The input and output ends of the circuit are connected to each other, and the output and input ends of a clocked inverter (clocked gate) ₁₈₂ controlled by a clock signal are connected to each other. and a connection point N ₃ between the input end and the output end of the clocked inverters 18 ₁ and 18 ₂ ;
A latch output signal DO is obtained from the connection point _N4 between the output end and the input end. In the above configuration, the clocked inverters 18 ₁ and 18 ₂ constitute a sense amplifier circuit, which amplifies the data DI inputted via the clocked inverters 17 ₁ and 17 ₂ . ing. Now, if the clock signal φ goes to the "1" level, the data DI is transmitted to the node via the clocked inverters 17 ₁ and 17 ₂ , respectively.
Supplied to N ₃ and N ₄ . When the clock signal reaches the "1" level, the potentials at nodes _N3 and ^N4 are amplified and latched by clocked inverters ₁₈₁ and ₁₈₂ . At this time, even if the circuit threshold value V _M of the clocked inverters 17 ₁ and 17 ₂ fluctuates for some reason, the nodes N ₃ and N ₄
If the magnitude relationship of the potentials is correct, these nodes
N ₃ and N ₄ are clocked inverters 18 ₁ and 18 ₂
The voltage is immediately corrected to the correct potential. for example,
Each clocked inverter 17 ₁ , 17 ₂ , 18 ₁ ,
The circuit threshold value V _M of 18 ₂ is set to 2.5V, and the input data
When DI = “0” (0V) and ^DI = “1” (5V) are applied, and the clock signal φ changes from “1” level to “0” level, the potentials of nodes N ₃ and N ₄ each become 1.5V. ,
Even if it reaches 1.0V, this potential is immediately corrected to 5V and 0V by clocked inverters ₁₈₁ and ₁₈₂ , and data can be given to nodes connected to these nodes _N3 and _N4 . Note that when the clock signal φ is at the "0" level, the data on the nodes _N3 and _N4 are held statically by the clocked inverters ₁₈₁ and ₁₈₂ . Therefore, according to such a configuration, if at least one of the clocked inverters 17 ₁ and 17 ₂ takes in enough data DI or ^DI , the other one will not operate normally and the potential of its output node will change to the next one. Normal operation can be performed even if the circuit threshold value _VM of the gate connected to the stage is not reached, and high reliability can be obtained. Further, even if the outputs of the clocked inverters 17 ₁ and 17 ₂ are not completely determined, it is sufficient to determine their magnitude relationship, so that the operating speed can be increased. Figures 2 to 7 are the same as Figure 1a above.
Circuit simulation of a sense amplifier circuit consisting of clocked inverters 18 ₁ and 18 ₂ in
This shows the simulation results using SPICE. In this simulation, the circuit is configured as shown in FIG. A circuit like this
CMOS, and the ratio of channel width Wn and channel length Ln of N-channel MOS transistor to Wn/Ln
=15/1.2, the ratio of channel width Wp to channel length Lp of a P-channel MOS transistor is Wp/Lp=
They are set to 22/1.5. Figure 2 shows A
The simulation result is shown when a clock signal is applied after initializing B (corresponding to node _N3 in FIG. 1) to 5V and B (corresponding to node _N4 in FIG. 1) to 0V. Similarly, Figure 3 shows A
= 4V, B = 1V, Figure 4 shows A = 3V, B = 2V, Figure 5 shows A = 2.6V, B = 2.4V, Figure 6 shows A = 2V,
B=1V, and in FIG. 7, the clock signal is applied after initial setting to A=1V and B=0V, respectively. As shown in the figure, even if the input signal A,
Even if the level of B is lower than the circuit threshold voltage V _M of the inverters 19 ₁ and 19 ₂ , the amplification operation of the clocked inverters 18 ₁ and 18 ₂ will eventually
A′=0V, B′=5V are set. In this way, it is possible to operate satisfactorily even if one of the supplied data has an incomplete value. Next, as shown in FIG. 9, an inverter 2 is used instead of the clocked inverter ₁₈₁ in FIG.
A similar circuit simulation was performed by setting 0. The results are shown in FIGS. 10 and 11.
In Figure 10, A=2.5V is set,
In FIG. 11, the clock signal is supplied after initial setting to A=2V. As shown, the ninth
In the circuit configuration shown in the figure, input signal A is
If it is 2.5V, this potential can be corrected to 5V by the clocked inverter ₁₈₂ and inverter 20, but if the input signal A is 2V, it becomes 0V and correction is impossible. On the other hand, in the circuit shown in FIG. 8, as shown in FIGS. 6 and 7, even when the input signal A is 2V and 1V, it can be corrected to 5V and latched. FIG. 12a shows another embodiment of the invention. In the figure, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. That is, in place of the clocked inverter ₁₈₂ in FIG.
This clock gate 21
This is made possible by supplying a SET signal to the SET signal. FIG. 12b shows a block diagram of FIG. 12a. Even in such a configuration, basically the first
The circuit operates in the same way as the circuit shown in Figure a, and the same effect can be obtained. In each of the above embodiments, clocked inverters 17 ₁ and 17 ₂ were used as data transfer gates, but as shown in FIG.
2 ₁ and 22 ₂ , and inverters 23 ₁ and 23 ₂ may be provided at nodes N ₃ and N ₄ , and the latch outputs DO and ^DO may be obtained from the output terminals of these inverters 23 ₁ and 23 ₂ . FIG. 14 shows another embodiment of the present invention, in which two stages of the latch circuits shown in FIG. 1a are connected in cascade to form a master-slave type D flip-flop. a clocked inverter 17 ₁ controlled by a clock signal (first control signal);
17 ₂ input terminals have opposite phase data DI, ^DI , respectively.
is supplied. Each of the above clocked inverters 17
The input and output terminals of a clocked inverter ₁₈₁ , which is controlled by a clock signal, are connected between the output terminals of the clocked inverter ₁₈₁ and the output terminal of the clocked inverter _{182 ,} which is controlled by a clock signal. and input ends are connected respectively. Connection point between the input end of the clocked inverter ₁₈₁ and the output end of the clocked inverter ₁₈₂ (node _N3 )
is connected to the input terminal of a clocked inverter ₁₇₃ controlled by a clock signal (second control signal). In addition, the clocked inverter 18
The input end of a clocked inverter 174 controlled by a clock signal is connected to the connection point (node _N4 ) between _{the input end of the clocked inverter 2 and} the output end of the clocked inverter ₁₈₁ . Each of the above clocked inverters 1
The input and output terminals of a clocked inverter 18 ₃ controlled by a clock signal φ are connected between the output terminals of the circuits 7 ₃ and 17 ₄ , and a clocked inverter 18 ₄ controlled by a clock signal φ is also connected. The output end and input end of are connected to each other. Then, an output signal DO is obtained from the connection point (node _N5 ) between the input end of the clocked inverter ₁₈₃ and the output end of the clocked inverter ₁₈₄ , and the output signal DO is connected to the input end of the clocked inverter ₁₈₄ and the output end of the clocked inverter 184. The output signal ^DO is obtained from the connection point (node N ₆ ) with the output end of the loaded inverter 18 ₃ . In the above configuration, a latch circuit consisting of clocked inverters 17 ₁ , 17 ₂ and 18 ₁ , 18 ₂ , and clocked inverters 17 ₃ , 17 ₄
and 18 ₁ and 18 ₂ respectively perform exactly the same operation as the circuit of FIG. 1a. Therefore, each latch circuit is capable of high-speed operation and has high reliability, and a flip-flop circuit constructed by cascading such latch circuits is also capable of high-speed operation and has a wide operating margin and high reliability. Gain reliability. FIG. 15 shows the results of an operation simulation performed on the flip-flop circuit shown in FIG. 14 using the circuit simulation SPICE described above. Here, the fourteenth
The circuit shown in the figure is converted into CMOS, and the ratio of channel width Wn and channel length Ln of N-channel type MOS transistor is Wn/Ln = 15/1.2, and the ratio of channel width Wp and channel length Lp of P-channel type MOS transistor is
Wp/Lp is set to 15/1.2, respectively, and the clock signal φ is set to 333.33MHz (period: 3nsec). As shown in the figure, it can be seen that sufficient operation is possible even when the clock signal φ has a high frequency. FIG. 16 shows a block diagram of the flip-flop circuit shown in FIG. 14. If this flip-flop circuit 24 is cascaded in multiple stages (n stages) by connecting the input end D and the output end Q, respectively, as shown in FIG. 17, and the same clock signal φ is supplied to each clock input end CK. , a shift register can be constructed. Note that, as shown in FIG. 18, the nodes N ₃ ,
Inverters 25 1 to 25 ₄ are provided between N ₄ and the input terminals of clocked inverters _{17 3} and 17 ₄ , and between nodes _{N 2} and _{N 6} , respectively.
Even if the output signals DO and ^DO are obtained from the first
The circuit operates in the same manner as the circuit shown in FIG. 4, and the same effect can be obtained. FIG. 19 shows another embodiment of the present invention, in which transfer gates 26 ₁ to 26 ₄ are provided in place of clocked inverters 17 ₁ and 17 ₄ as data transfer gates in FIG. It is something that This circuit corresponds to a two-stage cascade connection of the latch circuits shown in FIG. 13 above. FIG. 20 shows yet another example of the structure of the flip-flop circuit. That is _, in each of the embodiments described above, the clock signal φ was used, but in _the circuit shown in _{FIG .}
The circuit configuration is the same as that shown in FIG. 14 above. It goes without saying that the configurations shown in FIGS. 19 and 20 can also basically operate in the same way as the circuits shown in FIGS. 14 and 18 and provide the same effects. [Effects of the Invention] As described above, according to the present invention, a latch circuit that is capable of high-speed operation, has a wide operating margin, and has high reliability, and a flip-flop circuit using this latch circuit can be obtained.

[Detailed description of the invention]

FIG. 1 is a diagram showing a latch circuit according to an embodiment of the present invention, and FIGS. 2 to 7 are diagrams showing the results of simulations conducted to explain the operation of the circuit shown in FIG. 1, respectively. Figure 8 is the second figure above.
Figures 19 and 11 are diagrams showing the circuits used in the simulations shown in Figures 7 to 7, Figure 19 is a diagram showing the circuits used in another simulation, and Figures 10 and 11 are the circuits shown in Figure 9 above. Figures 12 and 13 are diagrams showing simulation results, respectively, showing latch circuits according to other embodiments of the present invention, and Figure 14 is a flip-flop circuit constructed using the latch circuit shown in Figure 1 above. 15 is a diagram showing the simulation results of the flip-flop circuit shown in FIG. 14, FIG. 16 is a block diagram of the flip-flop circuit shown in FIG. 14,
FIG. 17 is a diagram showing a shift register constructed using the flip-flop circuit shown in FIG.
8 to 20 are diagrams showing other configuration examples of the flip-flop circuit shown in FIG. 14, respectively.
1 shows a conventional latch circuit, FIG. 22 shows a conventional flip-flop circuit constructed using the latch circuit shown in FIG. 21, and FIG. 23 shows another example of the structure of the conventional flip-flop circuit. figure,
FIG. 24 is a block diagram of the flip-flop circuit shown in FIGS. 22 and 23, FIG. 25 is a diagram showing a shift register constructed using the flip-flop circuit shown in FIG. 24, and FIG. 26 is a diagram of a clocked inverter. FIG. 3 is a circuit diagram showing a configuration example. 18 ₁ , 18 ₂ ...Clocked inverter (first,
second clocked gate), ... clock signal,
17 ₁ , 17 ₂ ... clocked inverter (first and second data transfer gates), φ ... clock signal (control signal), DI, ^DI ... input data, DO, ^DO ... output signal.

Claims (1)

[Claims] 1. A first clocked gate, an output terminal connected to the input terminal of the first clocked gate, an input terminal connected to the output terminal, and controlled by the same clock signal as the first clocked gate. a second clocked gate that is controlled by a control signal and supplies data to the input of the first clocked gate; a first data transfer gate that is controlled by the control signal and supplies data to the input of the second clocked gate; A latch circuit comprising a second data transfer gate that supplies data in phase opposite to the above data, and obtaining latch outputs in phases opposite to each other from the output terminals of the second and first clocked gates. 2. The latch circuit according to claim 1, wherein said first and second clocked gates each comprise a clocked inverter. 3. The latch circuit according to claim 1, wherein each of said first and second data transfer gates comprises a clocked inverter. 4 A first clocked gate controlled by the first clock signal, an output terminal connected to the input terminal of the first clocked gate, and an input terminal connected to the output terminal, and controlled by the first clock signal. a second clocked gate that is controlled by the first control signal and supplies data to an input terminal of the first clocked gate; a second data transfer gate that supplies data with the opposite phase to the above data to the input end of the second clocked gate; a third clocked gate controlled by the second clock signal; and an output to the input end of the third clocked gate. a fourth clocked gate whose terminals are connected to each other and whose input terminal is connected to the output terminal and which is controlled by the second clock signal;
a third data transfer gate that is controlled by a control signal of the second clocked gate and supplies the first latch signal outputted from the output terminal of the second clocked gate to the input terminal of the third clocked gate; a fourth data transfer gate that is controlled by a signal and supplies a second latch signal output from the output of the first clocked gate to the input of the fourth clocked gate; A flip-flop circuit characterized in that outputs having mutually opposite phases are obtained from the output end of a third clocked gate. 5. The flip-flop circuit according to claim 4, wherein each of said first to fourth clocked gates comprises a clocked inverter. 6. The flip-flop circuit according to claim 4, wherein each of said first to fourth data transfer gates comprises a clocked inverter.