JPH0523654B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a demultiplexing circuit, and particularly to a scrambling method in a synchronous multiplex converter.

2. Description of the Related Art In a synchronous network in which all clocks in the network are synchronized with a reference clock, a method has been proposed to simplify the demultiplexing circuit. An example of such a method is, for example, Bell Technical Advisory (TA-TSY-
000253, Issue/, April, 1985).

That is, on the multiplexing side, as shown in FIG. 2a, after converting the low-order group data signal 101 into a pseudo-random pattern by the scrambler circuit 1,
An ID bit representing a channel number is inserted by the overhead bit insertion circuit 7, and the low-order group signal 10 is
Set it to 4. Next, the m-bit shift register 4 multiplexes m low-order group signals 104 into a high-order group signal 105. On the separation side, as shown in FIG. 2b, the high-order group signal 105 is converted into m low-order group signals by the m-bit shift register 9 and output from each stage of the shift register. Among these, the first-stage low-order group signal is supplied to a channel number separation circuit 10, where the channel number (ID bit) 102 is separated. Separation is completed by controlling the m×m selector 8 using this channel number 102. Thereafter, the separated low-order group signal is converted into the original low-order group data signal by the descrambler circuit 5.

In such a multiplexing/demultiplexing circuit, scrambling is performed on low-order group signals, so that the scrambling effect is reduced on high-order group signals. That is, if the low-order group input data signals 101 in FIG.
5, m identical codes are consecutive.

Problem to be Solved by the Invention In order to solve this problem, it is necessary to set the scrambler circuits to different initial values.

On the transmitting side, as shown in Figure 2a, the initial value is 1.
07 is set in the scrambler circuit 1, and at the same time, an initial value is inserted in the overhead bit insertion circuit 7. On the receiving side, as shown in FIG. Set to rambler circuit 5. FIG. 3 shows an example of a frame structure including a channel number (ID bit) and an initial value of the scrambler circuit (SEED bit) as overhead bits.

As described above, in the conventional system, it was necessary to transmit the initial value using overhead bits.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide a novel method that eliminates the need to transmit initial values using overhead bits and maintains the scrambling effect in high-order group signals. The purpose of this invention is to propose a demultiplexing circuit.

Means for Solving the Problems In a multiplexing system in which low-order group signals of m channels are bit-multiplexed by m-bit shift registers, it is necessary to transmit the channel number without fail.

The demultiplexing circuit according to the present invention is configured by adding a circuit for converting a channel number to an initial value of a scrambler circuit on the transmitting side and the receiving side, thereby eliminating the need for transmitting the initial value. Has characteristics.

Since the channel number is different for each channel, it is possible to generate a different initial value for the scrambler circuit for each channel. In this way, even if the same in-phase pattern is input to each channel, the phases of the patterns output from the scrambler circuit are different, so it is possible to produce a scrambling effect on the higher-order group signals.

Embodiment Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIGS. 1a and 1b show an embodiment of a demultiplexing circuit according to the present invention.

The operation of the multiplexer shown in FIG. 1a is as follows.
Channel number 102 is supplied to initial value generation circuit 3, converted to initial value 103 of the scrambler circuit, and set in scrambler circuit 1. The low-order group data signal 101 is converted into a pseudo-random pattern in the scrambler circuit 1, a channel number is inserted into overhead bits in the channel number insertion circuit 2, and then multiplexed into the high-order group signal 105 by the m-bit shift register 4. be done.

Of the separation section shown in FIG. 1B, the operations of the m-bit shift register 9, channel number separation circuit 10, and m.times.m selector 8 are similar to those of the conventional circuit shown in FIG. 2B. The low-order group signal 104 output from the m×m selector 8 is supplied to the channel number separation circuit 6 to separate the channel numbers. The channel number is converted into an initial value 103 of the descrambler circuit by the initial value generating circuit 3 and set in the descrambler circuit 5.

Effects of the Invention As explained above, according to the present invention, in a method for multiplexing scrambled low-order group signals of m channels into a high-order group signal with a clock frequency m times, the initial value of the scrambler circuit can be changed by using overhead bits. It is possible to construct a demultiplexing circuit that produces a scrambling effect on higher-order group signals without transmitting the signal.

[Brief explanation of the drawing]

Figures 1a and b are block diagrams showing one embodiment of the present invention, Figure 2 is a block diagram showing a conventional circuit configuration, and Figure 3 shows an example of the channel arrangement of high-order group signals and the configuration of a low-order group frame. FIG. DESCRIPTION OF SYMBOLS 1... Scrambler circuit, 2... Channel number insertion circuit, 3... Initial value generation circuit, 4... m-bit shift register, 5... Descrambler circuit, 6... Channel number separation circuit, 7... Overhead bit insertion circuit, 8... m×m selector, 9...m-bit shift register, 10...channel number separation circuit, 11...initial value separation circuit.

Claims (1)

[Claims] 1. On the transmitting side, the low-order group signal of m channels into which the channel number is inserted as an overhead bit is multiplexed into a high-order group signal with a clock frequency of m times, and on the receiving side, the multiplexed signal is separated in a demultiplexing circuit. , the transmission side includes a scrambler circuit that converts an input low-order group data signal into a random pattern, and an initial value generation circuit that converts the channel number into an initial value of the scrambler circuit and sets it in the scrambler circuit; and an insertion circuit for inserting the channel number into overhead bits, and the receiving side converts the random pattern low-order group signal separated from the high-order group signal into the original low-order group data signal based on the channel number. A demultiplexing circuit comprising a descrambler circuit and an initial value generation circuit that converts a channel number separated from the low-order group signal into an initial value of the descrambler circuit and sets it in the descrambler circuit.