JPH0524594B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to memory circuits, and more particularly to asynchronous static memories.

Conventionally, various circuits have been devised to reduce the power supply current during operation of asynchronous static memories that do not require an external clock. First, a typical conventional example will be shown below, and its configuration and operation will be explained.

First, a conventional static memory will be explained with reference to FIG. 1a.

Address input signal Ai (i=0, 1, 2,...,
n) is input to the input buffer 101. or,
Chip select input signal, data input signal
D _IN and the write enable input signal are each input to input buffer 102 . The configurations of input buffers 101 and 102 are as shown in FIGS. 1b and 1c, respectively. In the input buffer 101 of FIG. 1b, the address change detection signal φi is output for a certain period determined by the delay time of the delay circuit 11 when the address input Ai changes from low level to high level or from high level to low level. This is a signal that goes low level. address input signal
The timing relationship among Ai, address buffer signals A'i,', and address change detection signal φi is as shown in FIG.

The clock generating section 103 generates an address change detection signal φi (i=0, 1, 2, . . . ,
n) and chip select buffer signal CS'.
A precharge clock signal φp is generated by using AND logic. The precharge clock signal φp
is the precharge of each bit line BL arranged in the memory cell matrix section 107 when the chip select input signal is at low level and the address input signal Ai changes or when the chip select input signal is at high level. That is, the data on the bit line is reset. or,
The signal A′i buffered by the input buffer 101,
A desired memory cell 109 is selected from A'i by the X address decoder 104 and the Y address decoder 105. D _IN control unit 106, D _puT control unit 10
8 controls data writing and reading, respectively. FIG. 1e shows the main part of the memory cell matrix section 107. Multiple word lines WL
A memory cell 109 is arranged at each intersection of a plurality of bit line pairs BL, and a plurality of bit line pairs BL. Here, the memory cell 109 is a 6-transistor cell having a CMOS configuration as shown in FIG. 1f. Next, the operation of the memory cell matrix section 107 will be explained. Note that the signal waveforms of each part are as shown in FIG. When the memory circuit is selected, that is, when the chip select input signal is at low level,
By switching the address input signal Ai,
The X address decode signal Xi and Y address decode signal Yj also switch. On the other hand, as the address input signal Ai changes, an address change detection signal φi is generated, and thus a precharge clock signal φp is generated. The timing relationship among the Xi, Yi, and φp is as shown in FIG. In Figure 2, during the period when φp is at low level, Xi,
Yj is switched and only one memory cell address determined by address input signal Ai is selected.

The precharge clock signal φp precharges the bit line BL for a certain period of time including the time when a new memory cell is selected, and resets the state of the bit line. By using such a precharge clock signal φp, the bit line precharge period can be reduced to 5% to 10% of the operating cycle time.
Since the memory cell matrix section 107
The average value of the power supply current consumed by the bit line is much lower than that of other conventional systems that use a resistive load at the end of the bit line. This is because in the conventional system in which a resistive load is provided at the end of the bit line, current always flows from the bit line to the memory cell in a DC manner.

However, this conventional example also has the following drawbacks from the point of view of the peak value of the power supply current. That is, as can be seen from FIG. 2, even after Xi and Yj are selected and the read or write operation is completed, the voltage on the "0" information side line of the bit line BL remains the same as when the transfer gate _Q111 is open. It is pulled by the driver transistor Q ₁₁₂ of the memory cell in the memory cell, and slowly drops to near the GND potential. Eventually, the next address cycle occurs, and the precharge clock signal φp is generated.
All bit lines are charged to Vcc potential. At this time, the peak value of the power supply current reaches a considerably large value because one of the bit lines BL has dropped to near the GND potential. For example, 2K x 8 bit RAM
In the case of Vcc=5V, the peak value of power supply current Iccpeak
is approximately 100mA or more. When mounting a RAM with a large power supply peak current on a board, it is necessary to pay special attention to pattern design and power supply design, so it is desirable that the power supply peak current is as small as possible.

As described above, the memory circuit constructed as in this conventional example has the disadvantage that the peak value of the power supply current becomes extremely large when the bit line is precharged.

The object of the present invention is to suppress the average value of the power supply current during operation to the same level or less as the conventional example, and to suppress the peak value of the power supply current during operation to be sufficiently smaller than the conventional example.
The purpose is to provide memory circuits.

A memory circuit according to the present invention includes a memory cell having a MOS transistor and a transfer gate whose gates are cross-connected, a word line connected to the memory cells in the row direction, and a bit line connected to the memory cells in the column direction. A precharge circuit is provided for each of the bit line pairs and supplies a current to the bit line pair by inputting an address decode signal for bit line selection; The transfer gate of the memory cell is provided with a sense-up which detects and outputs the potential level between the bit line pair by inputting an address decode signal for the memory cell.
Driven by the word line, the bit line and the
The precharge circuit is provided to connect the nodes to which the MOS transistors are connected, and after precharging the bit line pair selected by the precharge circuit according to a change in the address input signal of the memory cell, In a memory circuit comprising circuit means for reading out information stored in a memory cell selected by an address decode signal and the bit line selection address decode signal by the sense amplifier, the potential of the selected word line is changed to the point where the read operation is completed. a word line control circuit that later sets the selected voltage to an intermediate potential below which the transfer gate is in an operating state; and a word line control circuit that sets the potential of an unselected bit line to a second value close to the value at the time of resetting this bit line. A bit line potential holding circuit is also provided.

In the memory circuit according to the present invention, the word line control circuit includes an inverter circuit that receives an address decode signal for word line selection, an N-channel transistor whose gate receives the output of the inverter circuit, and a change in address input signal. a delay circuit that delays a clock signal that becomes high level for a certain period of time until the read operation is completed; a two-input NAND circuit that receives the output of this delay circuit and the address decode signal for word line selection; a first P-channel transistor to whose gate the output of the NAND circuit is applied; a second P-channel transistor to whose gate the output of the inverter circuit is applied; and a third P-channel transistor whose gate is connected to a reference voltage. a P-channel transistor, the drains of the N-channel transistor and the first and second P-channel transistors are commonly connected to the source of the third P-channel transistor, and the common connection point is connected to a word line. The source of the N-channel transistor and the drain of the third P-channel transistor are connected to the reference voltage, and the sources of each of the first and second P-channel transistors are connected to a power supply voltage. be able to.

Further, the bit line potential holding circuit of the memory circuit of the present invention has its gate connected to the bit line selection address decode signal line, its source connected to the power supply voltage, and its drain connected to each bit line. and two fourth P-channel transistors.

In the present invention, the above word line and Vcc (or GND)
During this period, it turns ON (or OFF) when writing,
A transistor that is turned OFF (or ON) during reading can be provided.

A first embodiment of the present invention will be described with reference to FIGS. 3a, b, and c and FIG. 4.

First, with reference to FIG. 3a, the overall structure of the memory of this embodiment is explained. FIG. 3a shows that the memory cell matrix section 107 of FIG. This is a configuration in which a section 302 is added. The word line control section 302 shown in FIG. 3b uses a precharge signal φp
A NAND gate 32 receives as input the delayed signal via the delay circuit 31, and receives the output φx of this NAND gate 32 and the X decoder output Xi as input.
P channel transistors Q ₃₀₁ , Q ₃₀₃ , N channel transistors controlled by the NAND gate 34 and the inverted signal of the output of the NAND gate 34 and the inverter 33 of the X decoder output Xi
and a voltage output circuit formed by Q ₃₀₂ and Q ₃₀₄ . This circuit 302 changes the potential of the selected word line signal Wi after the read operation is completed.
It serves to lower the Vcc potential to a certain intermediate potential. To realize this operation, a word line control signal φx, which is a phase delay signal of the precharge clock signal φp, is generated. By the φx, the word line drive P-channel transistor _Q301 is switched from ON to OFF after the read operation is completed.

In this embodiment, it is assumed that the delay time of the delay circuit 31 is set so that the word line control signal φx falls based on the pre-estimated completion time of the read operation. Therefore, after the read operation is completed, the word line signal Wi goes to the potential determined by the current capability ratio of the P channel transistors Q ₃₀₃ and Q ₃₀₄ . Note that for unselected word lines, since the X decoder output Xi is at the GND potential, the P channel transistors Q ₃₀₁ ,
Q ₃₀₃ is OFF, N-channel transistor Q ₃₀₂ is ON
Therefore, the word line signal Wi also becomes the GND potential. That is, the states of unselected word lines are the same as in the conventional example.

Next, the operation of the memory cell matrix section 301 will be explained with reference to FIG. 3c. Note that the operating waveforms are as shown in FIG. FIG. 3c shows a circuit in which a bit line potential holding circuit 303 is added to the conventional memory cell matrix section 101 shown in FIG. 1c. First, the bit line potential holding circuit 303 will be explained. For each bit, the circuit 303 is composed of P channel transistors Q ₃₀₅ and Q ₃₀₅ ' whose opening and closing are controlled by the Y decoder output Yj. Therefore, for the selected bit line, since the Y decoder output Yj is at Vcc potential, the P channel transistors Q ₃₀₅ and Q ₃₀₅ ' are turned off. That is, the state of the selected bit line is the same as in the first embodiment. On the other hand, for the unselected bit line, since the Y decoder output Yj is at the GND potential, the P channel transistors Q ₃₀₅ and Q ₃₀₅ ' are turned on. Here, the relationship with the operation of the selected word line described above will be considered. First, the selected word line signal Wi rises to the Vcc potential, information of the memory cell connected to the selected word line begins to appear on the bit line, and one of the bit line bears BL slowly begins to fall from the Vcc potential. Eventually, the potential difference between BL and
The signal is amplified by the sense amplifier 110 and transmitted to the data output system as read data. At the time when read data is transmitted to the data output system, that is, at the time when reading is almost completed, the word line control signal φx falls, the word line drive P-channel transistor Q ₃₀₁ is turned off, and the word line signal Wi is P channel transistor Q ₃₀₃ ,
towards the intermediate potential determined by Q ₃₀₄ . This intermediate potential is applied to the selected memory cell 10 in the write operation.
The value should be designed to be as low as possible within the range that transfer gate Q ₁₁₁ of 9 is definitely turned on.
For example, the transistor sizes of the P channel transistors Q ₃₀₃ and Q ₃₀₄ are determined so that the intermediate potential is about 3 V when Vcc=5V.

In this way, since the gate potential of the transfer gate Q ₁₁₁ of the memory cell 109 connected to the selected word line, that is, the potential of the above Wi, moves toward the intermediate potential,
Although the current capability of the Q ₁₁₁ decreases and the level drop speed of the selected “0” information side bit line (BL or) becomes smaller, the transfer gate Q ₁₁₁
is ON, the potential of the "0" information side bit line continues to decrease toward the GND potential. on the other hand,
As for the unselected "0" information side bit line, the bit line holding circuit 303 operates, so the bit line potential is held at approximately Vcc potential, and Vcc → Q ₃₀₅ → bit line →
DC current flows through the path Q ₁₁₁ → Q ₁₁₂ → GND. Applicable
The DC current is mainly determined by the current capability of the transfer gate Q ₁₁₁ . As mentioned above, the word line signal Wi, which is the gate signal of Q ₁₁₁ , is at an intermediate potential, so the
Q ₁₁₁ 's current capability can be kept fairly low. For example, when V _U = SV and Wi = SV, the above DC current is approximately 120 μA per unit, whereas when Vcc = 5V and Wi = 3V, the above DC current is approximately 120 μA per unit.
It is 60μA. Therefore, in this example, 2K x 8 bits
When applied to RAM, the total number of bit lines is 128 columns, so the above DC flowing through all non-selected bit lines
The total current is approximately 7.2mA (0.06mA x 120),
This is a much smaller value than the conventional value (0.12mA x 120 = 14.4mA).

On the other hand, as described above, the selected "0" information side bit line drops almost to the GND potential, and is precharged to the Vcc potential in the next address cycle. At this time, a peak appears in the power supply current. Although the value of this peak depends on the number of selected bit lines, it is clear that it is considerably smaller than that of the conventional example. This is because in the above conventional example, all the selected and unselected "0" information side bit lines drop to almost the GND potential, and all of them are set to Vcc in the next address cycle.
This is because the potential was pre-charged. For example, when this embodiment is applied to a 2K×8 bit RAM, the peak value is 20 mA or less.

Here, if the potential of the word line is left at an intermediate potential without being reset after completion of reading, the DC current flowing through the transfer gate _Q111 of the unselected memory cell will be determined by the current capacity of the transfer gate _Q111 . Requires less DC current. In order to reduce the DC current flowing to this unselected memory cell,
If the potential of the word line is reset, the potential of the bit line of the selected memory cell will not be held, so it is necessary to provide a data latch circuit for latching the read data on the data bus line of the sense-up output, for example, and the circuit The problem is that it becomes complicated. In the embodiment of the present invention, by resetting the word line in this way, the sum of DC currents flowing through the unselected bit lines can be reduced without complicating the circuit.

Furthermore, when a write operation is performed in this embodiment, the potential after writing at the node on the "1" side of the memory cell 109 is (potential of Wi) - (V _TN ), the potential after writing at the node on the "0" side. is the GND potential, and the word line signal
As long as the potential of Wi is not too low, sufficient writing is performed. However, V _TN is the threshold voltage of the N-channel transistor. In particular, in this embodiment, since the memory cell 109 has a CMOS configuration, the potential of the node on the "1" side is reduced to Vcc several nanoseconds after writing due to the P channel transistor _Q113 of the memory cell 109.
potential. Note that the operating waveforms are as shown in FIG.

As described above, this embodiment secures almost the same operating margin and average power supply current as the conventional example, while
A memory circuit with sufficiently low power supply peak current has been realized.

Next, another embodiment of the present invention will be described.

In this embodiment, the word line control section 302 in the first embodiment is replaced with the word line control section 501 shown in FIG. This is a memory circuit that replaces the memory cell 502 shown in FIG. 5b. The word line control unit 501 of this embodiment sends a write enable buffer signal to the word line control unit 302 of the conventional example.
P-channel transistor with WE′ connected to the gate
This is a circuit with _Q501 added between the word line and Vcc. Furthermore, the memory cell 502 of this embodiment has a resistor 5.
01 and N-channel transistors Q ₁₁₁ and Q ₁₁₂ .

As mentioned above, in the write operation of the first embodiment, the potential of the node on the "1" side of the memory cell 109 is
From (Wi potential) - (V _TN ) immediately after writing, the number +
After 1 second, the P-channel transistor Q ₁₁₃
Increases to Vcc potential. However, when the memory cell is an NMOS memory cell 502 as in this embodiment,
Since the resistor 501 normally has a high resistance of several gigaohms, it takes a long time of several hundred microseconds for the "1" side node potential to rise to the Vcc potential after writing. In this way, if the node potential on the "1" side of the memory cell remains at an intermediate potential for a long time, there is a high probability that the memory cell information will be destroyed by electrical noise or alpha particles, making it difficult to use in actual use. becomes more likely to cause problems.

In this embodiment, in order to eliminate this drawback, the intermediate potential of the selected word line during writing is set higher than that during reading. Word line control section 5
Write enable buffer signal shown in 01
P-channel transistor whose opening/closing is controlled by WE'
Due to _Q501 , the intermediate potential of the selected word line during writing is higher than that during reading, thereby preventing information destruction in the memory cell 502 after writing.

As described above, the present invention realizes a memory circuit in which the average value and peak value of the power supply current during operation can be sufficiently reduced by lowering the selected word line potential to an intermediate potential after the completion of a read operation. It is. Although the above embodiments are examples in which precharge transistors Q ₁₀₂ and Q ₁₁₃ are provided at the end of the bit line, the gist of the present invention can also be satisfied if a resistive load is provided at the end of the bit line. , it is possible to realize a memory circuit in which the average value and peak value of the power supply current during operation are sufficiently small.

Furthermore, each of the above embodiments is an example in which the present invention is applied to a memory circuit with a complete CMOS configuration or a peripheral CMOS configuration; It is also possible to apply the present invention to a memory circuit or the like having a transistor configuration. others,
It goes without saying that various examples of application that satisfy the gist of the present invention are possible.

[Brief explanation of the drawing]

Figures 1a, b, c, d, e, and f respectively show a block diagram of a conventional memory, an address input buffer circuit diagram, an input buffer circuit diagram, a clock generation circuit diagram, and a memory cell matrix circuit diagram. , is a memory cell section circuit diagram. FIG. 2 is a signal waveform diagram showing read/write operations in the conventional example, and FIGS. 3 a, b, and c are block diagrams, partial circuit diagrams, and memory cell matrices, respectively, showing the first embodiment of the present invention. FIG. 4 is a signal waveform diagram showing the read/write operation of the first embodiment of the present invention, and FIGS. 5 a and b are partial circuit diagrams of the second embodiment of the present invention. , is a memory cell section circuit diagram. 101, 102...input buffer, 103...
Clock generator, 104...X address decoder, 105...Y address decoder, 106...
D _IN control unit, 107...Memory cell matrix unit, 108...D _puT control unit, 109...Memory cell, 110...Sense up, 301...Memory cell matrix unit, 302...Word line control unit, 303...Bit line potential holding circuit, 501...
...Word line control unit, 502...Memory cell.

Claims (1)

[Claims] 1. A memory cell having a MOS transistor and a transfer gate whose gates are cross-connected, a word line connected to the memory cells in the row direction, and a bit line connected to the memory cells in the column direction. and a precharge circuit provided for each of the bit line pairs and supplying current to the bit line pair by inputting an address decode signal for bit line selection; and a precharge circuit provided for each of the bit line pairs to supply current to the bit line selection. and a sense-up for detecting and outputting a potential level between the bit line pair by inputting an address decode signal for the memory cell, the transfer gate of the memory cell being driven by the word line and connecting the bit line and the bit line.
The bit line pair is connected to the node to which the MOS transistor is connected, and after the precharge circuit precharges the bit line pair selected by the change in the address input signal of the memory cell, the word line selection bit line pair is In a memory circuit comprising circuit means for reading out information stored in a memory cell selected by the address decode signal and the bit line selection address decode signal by the sense amplifier, the potential of the selected word line is changed to the point where the read operation is completed. A word line control circuit that later sets the selected voltage to an intermediate potential lower than this, at which the transfer gate is in an operating state, and a word line control circuit that sets the potential of the unselected bit line to a second value close to the value at the time of resetting this bit line. A memory circuit comprising: a bit line potential holding circuit for holding a bit line potential; 2. The word line control circuit includes an inverter circuit which inputs an address decode signal for word line selection, an N-channel transistor whose gate receives the output of this inverter circuit, and which operates for a certain period of time depending on changes in the address input signal. a delay circuit that delays a high-level clock signal until the read operation is completed; a two-input NAND circuit that receives the output of this delay circuit and the address decode signal for selecting the word line; and the output of this delay circuit and the word line a two-input NAND circuit to which a selection address decode signal is input; a first P-channel transistor to which the output of the two-input NAND circuit is applied; and a first P-channel transistor to which the output of the inverter circuit is applied; a third P-channel transistor whose gate is connected to a reference voltage, and a drain of each of the N-channel transistor and the first and second P-channel transistors; The sources of the P-channel transistors are connected in common, the common connection point is connected to a word line, the source of the N-channel transistor and the drain of the third P-channel transistor are connected to the reference voltage, and the source of the first P-channel transistor is connected to the reference voltage. , second P
2. The memory circuit according to claim 1, wherein each source of the channel transistor is connected to a power supply voltage. 3. The bit line potential holding circuit has two fourth pins whose gates are connected to the address decode signal line for bit line selection, whose sources are connected to the power supply voltage, and whose drains are connected to the respective bit lines. 3. The memory circuit according to claim 1, wherein the memory circuit is formed of a channel transistor. 4. Any one of claims 1 to 3, characterized in that a transistor is provided between the word line and the power source, which is turned on (or off) during writing and turned off (or on) during reading. Memory circuit described in .