JPH0524600B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read-only memory in which contents can be electrically written, that is, a programmable read-only memory, and in particular to a programmable read-only memory having test memory cells. -Relates to read-only memory.

[Conventional technology]

Recent programmable read-only memories (hereinafter referred to as P-ROMs), especially bibolar P-ROMs, have the flexibility to allow the user to freely write the contents of each memory, so they can be used for extremely wide-ranging information processing and control. It has a variety of uses.

The memory cell (hereinafter referred to as a cell) of such a P-ROM is as shown in FIG.
The emitter of the base-open transistor Q ₁ is connected to the bit line B, the collector is connected to the word line W, and diodes D ₁ and D ₂ are connected in series in opposite directions as shown in the equivalent circuit shown in Fig. 3. There are destructive memory cells. This junction breakdown type memory cell is written as shown in FIG. 4 by making the non-conductive state before writing conductive by shorting the diode _D2 shown in the equivalent circuit.

However, in such a P-ROM in which logic information is written into cells, the manufacturer ships the product in an unwritten state, and writing is performed for the first time by the user, so there is a problem with the writing yield.

As shown in Fig. 5, the conventional junction destruction type cell
Word lines W ₁ , W ₂ for each cell M ₁₁ , M ₁₂ , M ₂₁ , M ₂₂
Through the word driver circuit WD ₁ , WD ₂
is connected. Word driver circuit WD
This circuit selects a word line by setting the word line to high or low level, and absorbs a write current during writing. In Figure 5,
Cells M ₁₁ and M ₂₂ show the written state, but the cells that have not been written yet in the cell state
Word driver circuit connected to word line W ₂ when writing to M ₁₂
Select WD ₂ , turn it on, and apply a write current (for example, 200 ^mA ) from bit line B ₁ on the emitter side of cell M ₁₂ .
When , a write current flows into the selected word driver circuit WD ₂ through cell M ₁₂ and destroys diode D ₂ shown in FIG.

[Problem that the invention seeks to solve]

However, when writing to this cell _M12 , from the bit line _B1 through the cell _M12 to be written,
In addition to the current path of the selected word driver circuit WD ₂ , the cell M ₁₁ that has been written from bit line B ₁ and the cell M ₂₁ that has not yet been written
From the collector of the emitter, the cell being written
It is clear that there is a current path to the selected word driver circuit WD ₂ through M ₂₂ , and this current path has a reverse breakdown voltage of cell M ₂₁ (a polarity different from the voltage applied to the cell to be written). (withstanding voltage when applying _{a voltage of} Emitter from collector, written cell M ₂₂
If the current flows through the current path, it will result in a write failure. Since this writing failure occurs during writing by the user, there arises a problem of lowering the writing yield.

Therefore, an object of the present invention is to improve such problems, and to provide a P-ROM having a test function to determine whether or not a desired memory cell can be normally written to, and which has a high write yield. be.

[Means for solving problems]

Programmable read-only of the present invention
The memory consists of fixed memory cells with base-open transistors, and the emitters of these base-open transistors are connected to column lines, and the collectors are connected to row lines, in N rows and M columns (N and M are positive integers).
In a programmable read-only memory including a memory cell array arranged in a matrix, the fixed memory cell is provided for at least one of the N row lines and the M column lines and has the same configuration as the fixed memory cell. The test fixed memory cell is in an unwritten state and has a configuration in which the base open transistor of the test fixed memory cell has an emitter connected to a row line and a collector connected to a column line.

[Effect]

In order to achieve the purpose _of the present invention, as explained _{using FIG} . cell
It is only necessary to test whether a current path occurs through _M22 , and for that purpose, when writing cell _M21 , the third
As shown in the figure, V ₁ is the maximum voltage of bit line B ₁ at the moment when the diode is destroyed, V ₂ is the forward voltage of cells M ₁₁ and M ₂₂ that have already been written, and word driver circuit that is selected and turned on. If the on level of is V ₃ , then the cell M ₂₁ which has not been written yet
The withstand voltage from the collector to the emitter is (V ₁ −2V ₂ −
V ₃ ) Focusing on the fact that it is sufficient to test the above, in addition to the regular cell matrix, all cells in an unwritten state, that is, cells with the same structure as the regular cells, are shown in Figure 2 of the regular cells. various basses,
Connect the emitter of the open transistor to the bit line,
In contrast to the case where the collector is connected to the word line, test cells are provided in the row and/or column directions, with the emitter connected to the word line and the collector connected to the bit line.

P-ROMs cannot be tested by directly writing data into regular cells, and generally the circuit elements built into the circuit have reverse breakdown voltage (a polarity different from the voltage during normal operation). It is extremely difficult to confirm the withstand voltage when a voltage of

However, when multiple cells with the same configuration are used under the same conditions,
When formed simultaneously using the same method, the various characteristics of these cells fall within a certain range.

Therefore, in the present invention, the reverse withstand voltage of a regular cell is indirectly tested by testing the reverse withstand voltage of a test cell that is formed simultaneously with the same configuration, the same conditions, and the same method as the regular cell. and guarantee.

Thus, the programmable lead of the present invention
Before the only memory is written to the user for the first time, that is, at the time of shipment from the manufacturer, the test cell according to the present invention has a voltage of (V ₁ −2V ₂ −
Test to see if it has a withstand voltage of V ₃ ) or higher. In other words, as explained using FIG. 5, when attempting to write to cell _M12 , the cell that was originally intended for writing
Does the write current flow from _the bit line _B1 to the cell _M11 that is being written to, the collector to the emitter of the cell _M21 that has not yet been written, and the cell _M22 that has been written to? This can be indirectly tested by testing the test cells, making it possible to provide a P-ROM with a high write yield.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, this embodiment has at least a plurality of electrically writable cells in a common region of a semiconductor of one conductivity type, and each memory cell M ₃₃ ,
M ₃₄ , M ₄₃ , and M ₄₄ are connected. more cells
Word driver circuits WD ₃ and WD ₄ are connected to M ₃₃ , M ₃₄ , M ₄₃ , and M ₄₄ via word lines W ₃ and W ₄ . Furthermore, cells with the same structure as the unwritten cells M ₃₃ , M ₃₄ , M ₄₃ , M ₄₄ in the unwritten state according to the present invention are connected to the bit lines by connecting the emitters of the base open transistors of the normal cells as shown in FIG. , as opposed to connecting the collector to the word line,
As a test cell with the emitter connected to the word line and the collector connected to the bit line, cells M ₃₅ and M ₄₅ were connected in the row direction, and cells M ₅₃ and M ₅₄ were connected in the column direction, respectively.
Cells M ₅₃ and M ₅₄ are connected to word driver circuits WD ₃ and WD ₄ via word lines W ₃ and W ₄ , and cells M ₃₅ and M ₄₅ are connected to word driver circuit WD ₅ via word line W ₅ . This is because it is connected to the

In this embodiment, the word driver circuit WD ₅ connected to the word line W ₅ is turned on,
The breakdown voltage from the collector to the emitter of cell M ₃₅ or M ₄₅ from bit line B ₃ or B ₄ is (V ₁ −2V ₂ −V ₃ )
Further, the word driver circuit WD ₃ connected to the word line W ₃ is turned on, and the withstand voltage of the collector and emitter of the cell M ₅₃ is detected from the bit line B ₅ , as well as the word line W ₄ . Turn on word driver circuit WD ₄ connected to bit line B ₅ and test whether the withstand voltage of the collector and emitter of cell M ₅₄ is at least (V ₁ - 2V ₂ - V ₃ ) from bit line B 5. In other words, when attempting to write to a desired cell, data is transferred from a cell that has already been written to the same bit line as the desired cell, from the collector of the unwritten cell to the same word line as this written cell, and then through the emitter of this unwritten cell. A write current flows through the cell being written between the same bit line as the write cell and the word line of the desired cell.
The manufacturer can indirectly test and guarantee whether or not a desired cell will not be written and a write failure will occur at the shipping stage.

In the above description, the number of bit lines, word lines, and memory cells is limited, but the present invention applies to memory cells arranged in a matrix of N rows and M columns.
Applies to memories with cell arrays.

Furthermore, test memory cells may be provided in only one of the rows or columns.

〔Effect of the invention〕

As explained above, the present invention uses a base open transistor whose emitter is connected to a column line and whose collector is connected to a row line as a fixed memory cell.
In a programmable read-only memory having a memory cell array arranged in a matrix of N rows and M columns (N and M are positive integers),
Same configuration as fixed memory cells with emitters connected to row lines,
A base open transistor with the collector connected to a column line is installed as a memory cell for testing in the row and/or column direction, and the withstand voltage from the collector to emitter of this test memory cell is tested. It becomes possible to indirectly test the withstand voltage of the emitter from the collector of the memory cell, and the write yield can be improved, which is highly effective.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing the structure of a junction destruction type memory cell, FIG. 3 is an equivalent circuit diagram thereof, FIG. 4 is an equivalent circuit diagram after writing, and FIG. 5 is a circuit diagram showing a conventional example. . B ₃ , B ₄ , B ₅ ... bit line, M ₃₃ , M ₃₄ , M ₄₃ ,
_M44 ...Memory cell, _M35 , _M45 , _M53 , _M54 ...
...Test memory cell, W ₃ , W ₄ , W ₅ ... Word line, WD ₃ , WD ₄ , WD ₅ ... Word driver circuit.

Claims (1)

[Claims] 1. A matrix of N rows and M columns (N and M are positive integers) in which fixed memory cells are configured with base-open transistors, and the emitters of these base-open transistors are connected to column lines and the collectors are connected to row lines. In a programmable read-only memory including a memory cell array arranged in a shape, a test having the same configuration as the fixed memory cell is provided for at least one of the N rows of row lines and M columns of column lines. A programmable read-only memory cell characterized in that the test fixed memory cell is in an unwritten state and the emitter of the base-open transistor of the test fixed memory cell is connected to the row line and the collector is connected to the column line. ·memory.