JPH0524670B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit configured with MIS transistors, such as MOS transistors, and particularly relates to a semiconductor integrated circuit including MOS transistors with an effective channel length of 1 μm or less. [Technical Background of the Invention] The development of semiconductor integrated circuits including MOS transistors has been remarkable, and in the late 1960s, MOS transistors with an effective channel length of approximately 10 μm were being integrated with tens to hundreds of elements. It has been realized. Furthermore, microfabrication and high integration have progressed, and in recent years, VLSI has continued to develop with an effective channel length of about 1.5 μm and hundreds of thousands of elements, and in the future submicron MOS with an effective channel length of 1 μm or less.
The emergence of submicron semiconductor integrated circuits using transistors is expected. By the way, in conventional MOS type semiconductor integrated circuits, internal functional circuits are operated directly by external power supply, and the supply voltage has been reduced as the effective channel length of the MOS transistors that make up the internal functional circuits has been reduced. There is. For example, the current
The one with an effective channel length of 1.5μm is operated under a single 5V power supply. [Problems in the background art] As the effective channel length of MOS transistors decreases, the electric field inside the device increases under the condition that the power supply voltage is constant, and this increase in electric field causes the following problems. An inconvenience will occur. Generation of hot electrons and hot holes due to impact ionization Increase in substrate current Decreased punch-through resistance Occurrence of breakdown at source and drain junctions Change in threshold voltage of MOS transistor over time due to trapping of hot carriers in the gate insulating film This has the disadvantage that the voltage range of the externally supplied power source is severely limited. Furthermore, future submicron semiconductor integrated circuits will likely require a lower power supply voltage than the current standard 5V single power supply. This is to prevent the occurrence of the above-mentioned disadvantages, but in particular, changes over time in the threshold voltage of the MOS transistor due to trapping of hot carriers into the gate insulating film are
This causes a significant deterioration in the speed performance of submicron semiconductor integrated circuits and causes malfunctions. FIG. 1 is a sectional view showing the structure of a general enhancement type MOS transistor. In the figure, reference numeral 1 denotes a silicon substrate of p-type conductivity, for example, and a pair of n ⁺ type source region 2 and drain region 3 are formed on the inner surface of this substrate 1 .
Furthermore, a gate electrode 5 made of polycrystalline silicon is formed on the channel between the source and drain regions with a gate insulating film 4 interposed therebetween. FIG. 2 is a diagram showing the energy band state of the MOS transistor having the above configuration. As shown in FIG. 2, the potential barrier φ _e for electrons formed between the silicon substrate 1 and the surface of the gate insulating film 4 is approximately 3.1 eV.
Yes, and the potential barrier φ _h for the hole is about 3.8eV. Here, the element is miniaturized,
In Figure 1, if the effective channel length of the MOS transistor, indicated by L _eff , is shortened to 1 μm or less and the power supply voltage is set to 5 V, the hot electrons and hot holes generated by impact ionization are The probability of being emitted into the gate insulating film 4 increases beyond the potential barriers φ _e and φ _h . Then, electrons or holes are trapped, resulting in a large change in threshold voltage over time. On the other hand, from a system application point of view, it is preferable to share the power supply for each integrated circuit that makes up the system from the standpoint of miniaturization and cost reduction. Preferably, the circuit also operates under a 5V power supply, which is the current standardized power supply. However, in conventional semiconductor integrated circuits in which the internal functional circuits are operated directly by an external power supply, operating them under a 5V power supply causes the characteristics to deteriorate as described above, leading to the occurrence of defects. There are drawbacks. Furthermore, in conventional semiconductor integrated circuits, their performance, such as operating speed, current consumption, etc., vary greatly depending on externally supplied voltage. For this reason, there are disadvantages in that the degree of difficulty in designing the integrated circuit increases and that it becomes difficult to use in system applications. Furthermore, in conventional semiconductor integrated circuits,
For application purposes, it must be operated under a highly accurate power source. That is, when using a power supply with low precision, application of an excessive voltage causes deterioration and reliability problems, and deterioration and malfunctions occur due to power supply spikes and power supply noise. [Objective of the Invention] This invention was made in consideration of the above circumstances, and its first purpose is to provide a semiconductor that operates with high reliability without deterioration under a wide range of externally supplied power supply voltages. The purpose is to provide integrated circuits. A second object of the present invention is to provide a semiconductor integrated circuit that operates with constant performance over a wide range of externally supplied power supply voltages. A third object of the invention is to provide a semiconductor integrated circuit that does not deteriorate due to power supply spikes. A fourth object of the present invention is to provide a semiconductor integrated circuit that operates stably against power supply noise and fluctuations. [Summary of the invention] In order to achieve the above object, this invention has the following features:
A transistor element that shifts the voltage of either one of the first and second terminals to which power supply voltage is supplied to the internal power line, and detects the voltage of the internal power line at a predetermined threshold voltage. and a voltage detection circuit that supplies the detection output to the control terminal of the transistor element, forming an internal power supply circuit that obtains a constant voltage shifted from the voltage of the first or second terminal, and this internal power supply circuit Under the voltage obtained at and the voltage at the first or second terminal,
An internal functional circuit made up of MOS transistors is operated. [Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing the structure of a semiconductor integrated circuit according to the present invention. In the figure, 10 is a power supply terminal to which a power supply voltage V _CC (for example, 5V) is supplied from the outside, 20 is a ground terminal to which a ground voltage V _SS (0V) is supplied from the outside, 3
0 is an internal power supply circuit that steps down and shifts the voltage supplied to the terminal 10 to obtain a constant voltage V _INT , and 40 is an internal power supply that is supplied with the voltage V _INT obtained by this internal power supply circuit 30 and is charged by this voltage. line, 50
is a memory such as dynamic RAM, static RAM, ROM, EPROM, E ² PROM, etc., or a microprocessor, microcomputer, etc., which is configured with MOS transistors and operates using the voltage on the internal power supply line 40 as a power supply voltage. 60 is an input terminal provided for supplying an input signal to this internal functional circuit 50 , and 70 is an output provided for outputting a signal from the internal functional circuit 50 to the outside. It is a terminal. The internal power supply circuit 30 detects the voltage of the voltage reduction circuit 32 having a control terminal 31 and the internal power supply line 40 at a predetermined threshold voltage, and the detected output is a voltage supplied to the control terminal 31 of the voltage reduction circuit 32 . It is composed of a detection circuit 33 . In the semiconductor integrated circuit having the above configuration, the internal power supply circuit 30 is connected to the voltage V _CC supplied to the power supply terminal 10.
A constant voltage V _INT lower than this voltage V _CC is created and used as the power supply voltage of the internal functional circuit 50 . In addition, the internal power supply circuit 30
Then, the voltage V _INT is obtained from the voltage V _CC as follows. That is, the step-down circuit 32 steps down the voltage V _CC in accordance with the output from the voltage detection circuit 33 supplied to its control terminal 31 to obtain the voltage V _INT . on the other hand,
The voltage detection circuit 33 detects the voltage V _INT at the internal power supply 40 at a predetermined threshold voltage V _TH . Since this detection output is supplied to the control terminal 31 of the step-down circuit 32 , the output voltage from this step-down circuit 32 is
V _INT is controlled by a closed loop consisting of a voltage step-down circuit 32 and a voltage detection circuit 33 to match V _TH . 4 to 7 are specific circuit diagrams of the internal power supply circuit 30 in the embodiment circuit of FIG. 3, respectively. In FIG. 4, the step-down circuit 32 is composed of an enhancement type P-channel MOS transistor 101, the source of which is connected to the terminal 10, and the drain connected to the internal power supply line 40.
are connected to the control terminal 3, and the gate is connected to the control terminal 3.
Connected to 1. The voltage detection circuit 33 includes a P-channel MOS transistor 301 and an N-channel MOS transistor 301.
A CMOS inverter 303 consisting of a MOS transistor 302 and another similar configuration
It is configured by cascading CMOS inverters 304 . The threshold voltage V _TH of this voltage detection circuit 33 is
2 which mainly constitutes the CMOS inverter 303
It is determined by the ratio between the threshold voltage V _th and the mutual conductance of each of the two MOS transistors 301 and 302, and is set to, for example, 2.0V. In an internal power supply circuit with such a configuration,
If the voltage V _INT of the internal power supply line 40 is lower than the threshold voltage V _TH of the voltage detection circuit 33 , that is, if V _INT <V _TH , the output signal of the voltage detection circuit 33 becomes a low level (V _SS potential), and this By P
The degree of conductivity of the channel MOS transistor 101 is increased, and the voltage V _INT of the internal power supply line 40 is increased.
On the other hand, if V _INT > V _TH , the voltage detection circuit 33
The output signal becomes high level (V _CC potential), thereby the conductivity of P channel MOS transistor 101 decreases, and the potential V _INT of internal power supply line 40 becomes low. By the above operation, internal power line 4
The voltage V _INT of 0 will be set to V _INT =V _TH . In other words, in this circuit, since V _TH is set to 2.0V as described above, V _INT is also set to a constant 2.0V, and even when the external supply voltage V _CC is constant 5V or due to voltage fluctuations. , the value of V _INT remains constant at 2.0V even with fluctuations due to power supply spikes and power supply noise. Note that in this specific circuit, the voltage detection circuit 33 consists of two CMOS inverters 303 connected in cascade.
and 304, it is possible to sufficiently increase the degree of amplification when detecting the voltage of the internal power supply line 40, so that when the voltage of the internal power supply line 40 fluctuates, it can be restored in a short time. can be returned to. Further, since a CMOS inverter is used, the threshold voltage V _TH can be easily controlled, and the voltage of the internal power supply line 40 can be set relatively freely. The internal power supply circuit in FIG. 5 shows an example in which the step-down circuit 32 is composed of an enhancement type N-channel MOS transistor 102. And this
The drain of the MOS transistor 102 is the terminal 10
The sources are connected to the internal power supply line 40, and the gates are connected to the control terminal 31. At this time, the voltage detection circuit 33 is an N-channel MOS
An inverter circuit 307 includes a transistor 305 and a load resistor 306. That is, in this circuit, compared to the circuit in FIG. 4, the P channel MOS transistor 101 is replaced by an N channel MOS transistor.
Since the transistor 102 is replaced and the operation for the signal supplied to the control terminal 31 is reversed, the voltage detection circuit 33 is also replaced from a two-stage inverter configuration to a one-stage inverter configuration. In addition, the N channel in this Figure 5 circuit
A depletion type MOS transistor 102 may be used. In the internal power supply circuit of FIG. 6, the P-channel MOS transistor 10 as the step-down circuit 32 of FIG.
PNP type bipolar transistor 1 instead of 1
03, and even with this configuration, it operates in the same way as the circuit shown in FIG. At this time, the control terminal 31 is connected to the base of the PNP type bipolar transistor 103. Also in the case of this specific circuit, the voltage detection circuit 33 has two
Since it is composed of CMOS inverters 303 and 304, when the voltage of the internal power supply line 40 fluctuates, it can be restored to the original state in a short time, as in the case of Fig. 4.The internal power supply circuit of Fig. 7 , an N-channel MOS transistor 10 as a step-down circuit 32 in FIG.
NPN type bipolar transistor 1 instead of 2
04, and even with this configuration, it operates in the same way as the circuit shown in FIG. At this time, the voltage detection circuit 33 is a one-stage CMOS inverter 3 consisting of a P-channel MOS transistor 301 and an N-channel MOS transistor 302.
It consists of 03. Although this may be configured similarly to the inverter circuit 307 in FIG. 5, a CMOS configuration is more effective in supplying a larger base current to the bipolar transistor 104. Incidentally, in each of the circuits shown in FIGS. 4 to 7, the voltage setting on the internal power supply line 40 is performed by charging the capacitance associated with the internal power supply line 40 with the output voltage of the step-down circuit 32 . on the other hand,
The voltage step-down circuit 32 , the internal power supply line 40, and the voltage detection circuit 33 constitute a closed loop, and depending on the conditions, there is a possibility that an oscillation phenomenon may occur in this closed loop.
Therefore, in each of the above embodiments, the time constant when the internal power supply line 40 is charged by the step-down circuit 32 is T, and the time constant (threshold detection time) when the voltage detection circuit 33 detects the voltage is T _d . In this case, the transistors ₁₀₁ , 1
The sizes of transistors 02, 103, and 104 or the size of each transistor in the voltage detection circuit 33 are set to prevent oscillation. FIG. 8 is a block diagram showing the structure of another embodiment of the invention. In this embodiment circuit, two internal power supply circuits 30A and 30B having different output voltages are provided, and different parts of the internal functional circuit 50 are operated by the respective output voltages V _INT1 and V _INT2 . In this way, two internal power supply circuits 30
By providing A and 30B, the power supply voltage is lowered in one part of the internal functional circuit 50 to reduce power consumption, and the power supply voltage is raised in the other part to increase the operating speed. can be obtained. In this way, the following effects are achieved in the above embodiment. First, in each embodiment, it is possible to obtain on-chip an internal power supply circuit that outputs a constant voltage of 2.0V and has a high current supply capability for a wide range of externally supplied power supply voltage V _CC from 2.0V to 8V, for example. Under this constant and stepped-down internal power supply voltage, the effective channel length is less than 1 μm.
Since the internal functional circuit 50 including the MOS transistor operates,
All problems related to power supply voltage limitations due to miniaturization of MOS transistors can be solved, and thereby a submicron-order semiconductor integrated circuit without deterioration phenomena can be realized. Furthermore, even if the external supply voltage changes, the internal functional circuits operate under a constant, stepped-down internal power supply voltage, so performance such as operating speed and current consumption remains constant despite changes in the external supply voltage. Stable submicron-order semiconductor integrated circuits can be realized. Similarly, a semiconductor integrated circuit that is resistant to power supply noise can be realized, and a semiconductor integrated circuit that does not deteriorate even when a power supply spike is applied can be realized.
This enables MOS with an effective channel length of less than 1 μm.
It is possible to operate semiconductor integrated circuits, including transistors, on a single 5V power supply, which is a conventional standardized power supply, and with a TTL interface, and it is also possible to operate a semiconductor integrated circuit including transistors with a TTL interface using a single 5V power supply, which is a conventional standardized power supply, and it will also be possible to maintain similar performance under a future low-voltage power supply, such as 3.5V. It can also be run with . By the way, in the example circuit shown in FIG. 3 above,
Using the power supply voltage V _CC supplied to the power supply terminal 10, the internal power supply circuit 50 shifts this to create a low constant voltage V _INT , and the internal functional circuit 50 is connected to the ground potential V _SS
The internal power supply circuit 30 is configured to operate between this constant voltage V _INT and the voltage shift circuit 34 in place of the step-down circuit 31 , as shown in the embodiment of FIG . ' may be used to shift the voltage at the ground terminal 20 from 0V and supply it to the internal power supply line 40. In this embodiment, the internal functional circuit 50 operates under the shifted voltage V _INT obtained from the internal power supply line 40 and the power supply voltage V _CC . Figures 10 to 13 respectively represent the above-mentioned figure 9.
This is a specific circuit diagram of the internal power supply circuit 30 ' in the embodiment circuit shown in the figure, and corresponds to those in FIGS. 4 to 7, respectively. And these first
In the circuits shown in FIGS. 0 to 13, in order to shift the ground voltage V _SS as an output voltage and output a voltage higher than this, the P channel MOS transistor 101 and the N channel MOS transistor in FIGS. 4 to 7 are used.
In place of the transistor 102, the PNP type bipolar transistor 103, and the NPN type bipolar transistor 104, an N channel MOS transistor 401 and a P channel MOS transistor 40 are used.
2. NPN type bipolar transistor 403,
A voltage shift circuit 34 is configured by each PNP type bipolar transistor 404. Note that, similarly to FIG. 8, two internal power supply circuits 30 ' shown in FIG. 9 may be provided, and different parts of the internal functional circuit 50 may be operated with the respective output voltages. Note that this invention is not limited to the above embodiments, and various modifications are possible. For example, the step-down circuit 32 or the voltage shift circuit 34 has been described as being composed of a single MOS transistor or a bipolar transistor, but it is also possible to construct it by connecting two or more transistors in parallel or in series. It's okay. In addition, although the case where the output voltage of the internal power supply circuit shown in FIGS. 4 to 7 or 10 to 13 is set to 2.0V has been described, this is the threshold voltage in the voltage detection circuit 33.
It goes without saying that by setting V _TH , as the effective channel length of the MOS transistor is reduced to 1 μm, 0.5 μm, and 0.1 μm, it can be changed from 2.0 V to 0.5 V, for example. [Effects of the Invention] As explained above, according to the present invention, it operates with high reliability and constant performance without deterioration under a wide range of externally supplied power supply voltage, without deterioration due to power supply spikes, and with no power supply noise. Accordingly, it is possible to provide a semiconductor integrated circuit that operates stably against fluctuations.

[Brief explanation of the drawing]

Figures 1 and 2 are typical MOS
A cross-sectional view and an energy band state diagram of a transistor, FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS.
A circuit diagram specifically showing a part of the example circuit shown in the figure;
FIG. 8 is a block diagram showing the configuration of another embodiment of the present invention, FIG. 9 is a diagram showing the configuration of another different embodiment of the invention, and FIGS. 10 to 13 are respectively implementations of FIG. 9. FIG. 2 is a circuit diagram specifically showing a part of the example circuit. DESCRIPTION OF SYMBOLS 10... Power supply terminal, 20... Ground terminal, 30... Internal power supply circuit, 40... Internal power supply line, 50... Internal functional circuit, 60... Input terminal, 70... Output terminal, 31... Control terminal, 32... Step-down circuit, 33... voltage detection circuit,
34...Voltage shift circuit, 101,402...P channel MOS transistor, 102,401...N channel MOS transistor, 103,404...
PNP type bipolar transistor, 104,40
3...NPN type bipolar transistor.

Claims (1)

[Scope of Claims] 1. Has first and second terminals to which a power supply voltage is supplied to each other, and a control terminal, and shifts the voltage of one of the first and second terminals. It consists of a transistor element for voltage shifting, an internal power supply line to which the voltage shifted by the transistor element is supplied and charged by this voltage, and two CMOS inversion circuits connected in cascade, and the internal power supply line is connected to the internal power supply line. voltage detecting means that detects and amplifies the voltage at a predetermined threshold voltage and supplies the output to the control terminal of the transistor element; and the internal power supply line and the other of the first and second terminals. 1. A semiconductor integrated circuit, which operates at a voltage between 1 and 2, and includes a functional circuit composed of MIS transistors. 2. The time constant when charging the internal power supply line by the voltage shifting transistor element is T, and the time constant when detecting voltage in the voltage detecting means is td.
The size of the transistor element for voltage shifting or the size of the element constituting the signal inversion circuit in the voltage detection means is set so as to satisfy the relationship td<T. The semiconductor integrated circuit according to item 1.