JPH0524685B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to field effect transistors (hereinafter referred to as FETs).
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[Prior Art] FIG. 3A is a plan view of a first conventional spiral inductor, and FIG. 3B is a plan view of a spiral inductor in FIG. 3A.
It is a longitudinal cross-sectional view taken along the A' line. In FIGS. 3A and 3B, a spiral metal conductor pattern 1 is formed on a dielectric substrate 2, and two ends 1 of the metal conductor pattern 1 are formed on a dielectric substrate 2.
A spiral inductor is constructed with terminals a and 1b.

Figures 4 and 5 show the second conventional single gate FET 11 and dual gate FET, respectively.
21 is a circuit diagram of an active inductor using 21. In Figure 4, resistor 16 is a single gate FET
connected between the drain 12 and gate 14 of 11,
In addition, the capacitor 15 is the source 13 of the FET 11,
It is connected between the gates 14. Here, FET11
Since the impedance Z ₀ seen from the terminals 17 and 18 connected to the drain 12 and source 13 of the FET 11 side, respectively, shows inductivity, the
FET circuits can be used as active inductors.

In Figure 5, resistor 16 is a dual gate
The capacitor 15 is connected between the drain 22 and the first gate 24 of the FET 21.
connected between the source 21 and the first gate 24,
Furthermore, the capacitor 26 is connected to the source 2 of the FET 21.
1 and the second gate 25. This capacitor 26 grounds the second gate 25 at high frequency and suppresses the capacitive electrostatic coupling between the drain 22 and the first gate 24, so that the active inductor in FIG. 5 is the same as the active inductor in FIG. The high frequency characteristics are improved compared to .

[Problems to be Solved by the Invention] However, although the spiral inductor of the first conventional example has a simple configuration as described above, in order to obtain the required inductance, the shape of the spiral inductor must be large. At the same time, the magnetic field generated by the spiral inductor leaks to the surrounding area, making it impossible to form other circuit patterns on nearby substrates, resulting in problems such as an increase in the actual occupied area.

On the other hand, in the active inductor using FET of the second conventional example, the FET circuit itself can be configured smaller than that of the first conventional example, and since it does not use a magnetic field, other circuit patterns can be connected in close proximity. Therefore, the active inductor is suitable for miniaturization of integrated circuits. However, even if the capacitive coupling capacitance can be ignored using the circuit shown in FIG. .

To simplify the analysis of this active inductor circuit, if a single-gate FET or dual-gate FET is expressed only by the depletion layer capacitance Cgs between the gate and source directly below the gate, and the mutual conductance gm, the conventional active inductor The impedance Z ₀ of is given by the following equation.

Z ₀ =1+jωCnR/gm+jωCn (1) Here, Cn=C ₁ +Cgs, and R and C ₁ are the resistance value of the resistor 16 and the capacitance of the capacitor 15, respectively. Expressing the above equation (1) as an equivalent circuit, we get
Under the condition gm≫ω ² Cn ² R, as shown in Figure 6, the resistance value (1/gm) is the resistance 61 and the inductance value (CnR/gm) is the inductance 62.
A capacitor 63 with capacitance Cn is connected to the series circuit of
Generally corresponds to circuits connected in parallel. In this case, as the frequency increases due to the influence of the parallel capacitance Cn, the inductance component in equation (1) decreases rapidly. Furthermore, even if C ₁ = 0 to reduce the influence of the parallel capacitance Cn, the influence of the depletion layer capacitance Cgs still remains as shown in the following equation, making it difficult to prevent the inductance value of the active inductor from decreasing. .

Z ₀ = 1 + jωCgsR/gm + jωCgs ...(2) On the Smith Chart in Figure 7, the gate length is 0.5μm.
The impedance of equation (2) when using the FET Z ₀
The calculated value of the frequency locus is shown by the solid line 71, and the resistance 61
The calculated frequency locus of the series circuit of the inductance 62 and the inductance 62 is shown by a broken line 72. Here, set the frequency to 0.5G
When changing from Hz to 10GHz, each trajectory 71,7
2 changes from 71a to 71b and from 72a to 72b, respectively.

As is clear from FIG. 7, each locus 71 and 7
2 do not match, and in conventional active inductors,
The influence of the depletion layer capacitance Cgs between the gate and source of the FET cannot be ignored. This is because the current flowing into the terminal 17 includes the current flowing through the resistor 16 and the capacitor Cn. Therefore, there has been a problem in that it is difficult to operate the active inductor in a high frequency band, for example, a microwave band or higher.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an active inductor whose inductance value does not decrease even in a high frequency band, such as a microwave band or higher, and which can be miniaturized.

[Means for Solving the Problems] The present invention provides a first field effect transistor, a source electrode connected to the drain electrode of the first field effect transistor, and a gate electrode connected to the source of the first field effect transistor. a second field effect transistor connected to the electrode; and a resistor connected between the gate electrode of the first field effect transistor and the drain electrode of the second field effect transistor, A field effect transistor is characterized in that the drain electrode and gate electrode are two terminals.

The present invention also provides a first field effect transistor and a second field effect transistor having a source electrode connected to the drain electrode of the first field effect transistor and a gate electrode connected to the source electrode of the first field effect transistor. an effect transistor, a resistor connected between the gate electrode of the first field effect transistor and the drain electrode of the second field effect transistor, and between the gate electrode and the source electrode of the first field effect transistor. and a capacitor connected to the second field effect transistor, and the drain electrode and gate electrode of the second field effect transistor are two terminals.

[Function] With the former configuration, the source-grounded first field-effect transistor and the gate-grounded second field-effect transistor are connected in cascade, and the resistor is connected between the gate electrode of the first field-effect transistor and the second field-effect transistor. is connected to the drain electrode of the field effect transistor, and a current approximately equal to the current i flowing through the resistor and the depletion layer capacitance of the first field effect transistor is transferred from the depletion layer capacitance of the second field effect transistor to the first field effect transistor. is supplied to the drain electrode of Therefore, the drain current of the second field effect transistor is reduced by the above current i, and the current flowing into one terminal of the active inductor is reduced by the above current i.
will no longer be included. This makes it possible to suppress a decrease in the inductance of the two terminals of the active inductor compared to the conventional example.

In addition, with the latter configuration, in addition to the former configuration, a capacitor is provided between the source electrode and gate electrode of the first field effect transistor, so the inductance of the active inductor is increased by the capacitor. can be done. Therefore, in addition to suppressing the decrease in inductance, an active inductor having an arbitrary inductance can be realized by changing the capacitance of the additional capacitor.

[Embodiment] FIG. 1 is a circuit diagram of an active inductor according to a first embodiment of the present invention. This active inductor is
Source common FET31 and gate common FET35
By cascading the FET31 and connecting the resistor 16 between the gate of FET31 and the drain of FET35,
It is characterized by suppressing the above-mentioned parallel capacitance Cn. In FIG. 1, the same parts as in the above-mentioned drawings are given the same reference numerals.

In Figure 1, the drain 32 of FET 31 is
It is connected to the source 37 of the FET 35, and the source 33 of the FET 31 and the gate 38 of the FET 35 are connected to the ground terminal 18. Also, a resistor 16 with a resistance value R
is connected between the gate 34 of FET 31 and the drain 36 of FET 35, and the drain 36 of FET 35 is
is connected to terminal 17. Further, a resistor 50 having a resistance value R ₀ is connected between terminals 17 and 18. Note that the FETs 31 and 35 have parasitic capacitances Cgs ₁ and Cgs ₂ between the gate and the source, respectively, and the parasitic amounts Cgs ₁ and Cgs ₂ are generally approximately equal to the depletion layer capacitance immediately below the gate electrode. Below, the parasitic capacitance
Cgs ₁ and Cgs ₂ are called depletion layer capacitance.

First, terminal 1 in Fig. 1 without the resistor 50
Impedance when looking at the FET circuit side from 7 and 18
Find Z ₀ . Here, in order to simplify the analysis as in the conventional example, FETs 31 and 35 have depletion layer capacitances Cgs ₁ and Cgs ₂ directly under the gates and mutual conductance.
If expressed as gm ₁ and gm ₂ , impedance Z ₀ is given by the following equation.

Z ₀ = Za／Zb ……(3) Za＝1＋jωCgs ₁ R ……(4) Zb＝gm ₁ +jω｛Cgs ₁ −Cgs ₂ (gm ₁ /gm ₂ ) +(ωCgs ₁ Cgs ₂ /gm ₂ ² ) Cgs ₂ } ...(5) Here, it is assumed that FET31 and FET35 have almost the same electrical characteristics, and Cgs ₁ = Cgs ₂ = Cgs,
If gm ₁ =gm ₂ =gm, the impedance Z ₀ of the above equation (3) becomes the following equation.

Z ₀ =1+jωCgsR/gm+jω(ωCgs/gm) ² Cgs……(
6) In general, for short gate length FETs used in the microwave band and above, (ωCgs/gm) ² is sufficiently smaller than 1, so as can be seen by comparing with equation (2),
The effects of FET parasitic capacitance are greatly suppressed. To explain the reason qualitatively, a current approximately equal to the current i flowing through the resistance R and the depletion layer capacitance Cgs ₁ is supplied from the depletion layer capacitance Cgs ₂ to the drain of the FET 31, and therefore the drain current of the FET 35 is This is because the current flowing into the terminal 17 does not include the current i.

Therefore, for example, even at frequencies above the microwave band, (ωCgs/gm) ² <<1, so the above (6) is satisfied.
The imaginary term in the denominator of the equation can be ignored and the circuit of FIG. 1 operates as an active inductor.

The calculated value of the frequency locus of impedance Z ₀ in equation (6) is shown by a solid line 73 on the Smith chart in FIG. Further, the calculated frequency locus of the series circuit of the resistor 61 and inductance 62 in the above-described equivalent circuit of FIG. 6 is shown by a broken line 72 on the Smith chart of FIG. Here, when the frequency is changed from 0.5 GHz to 10 GHz, the trajectories 72 and 73 change from 72a to 72b and from 73a to 73b, respectively.
By comparing FIG. 7 and FIG. 8, the locus 73 approaches the locus 72 of the series circuit of the resistor 61 and the inductance 62 compared to the locus 71. Therefore, it can be seen that the active inductor of the present invention shown in FIG. 1 without the resistor 50 operates well even in the microwave band.

Next, the inductance value of the impedance Z ₀ when looking at the FET circuit side from the terminals 17 and 18 in FIG. 1 when the resistor 50 is added will be explained.

Figure 9 shows the resistor 50 in Figure 1.
5 is a diagram illustrating the effect of connecting between the drain 36 and gate 38 of the active inductor in FIG. It is a characteristic. A broken line 76 is the frequency characteristic (C ₁ =0) of the conventional active inductor shown in FIG.

In Figure 9, the inductance value when there is no resistor 50 increases from a frequency of 2 GHz to approximately
It has a peak value at 8 GHz, and the inductance value decreases at frequencies above that. On the other hand, resistance 50
If there is an inductance value, the frequency is about 6G
The inductance value is approximately constant up to Hz, and at frequencies higher than that, the inductance value gradually decreases. Further, the inductance value of the conventional active inductor shown in FIG. 4 decreases from a frequency of 1 GHz. Therefore, resistance 5
0 has the function of suppressing an increase in the inductance value in the characteristic 75 without the resistor 50 and making the characteristic 74 close to the characteristic 76 of the conventional example. Therefore, by appropriately setting the resistance value of the resistor 50, a constant inductance can be achieved over a wide frequency range.

FIG. 2 is a circuit diagram of an active inductor according to a second embodiment of the present invention. In FIG. 2, the same parts as in the above-mentioned drawings are given the same reference numerals. The circuit shown in FIG. 2 is different from the _circuit shown in FIG. A capacitor 51 with a capacity of C ₂ is connected.

The impedance Z ₀ when looking at the circuit side from terminals 17 and 18 of the circuit of this second embodiment is determined by replacing capacitance Cgs ₁ with capacitance (C ₁ +Cgs ₁ ) and replacing Cgs ₂ with capacitance (Cgs 1 ) in equation (5). C ₂ + Cgs ₂ ), it can be calculated using the following formula.

Z ₀ = Zc / Zd ... (7) Zc = 1 + jω (C ₁ + Cgs ₁ ) R ... (8) Zd = gm ₁ + jω [(C ₁ + Cgs ₁ ) - (C ₂ + Cgs ₂ )・(gm ₁ / gm ₂ ) + {ω ² (C ₁ +Cgs ₁ ) ・(C ₂ +Cgs ₂ )/gm ₂ ² }Cgs ₂ ...(9) In the above equation (9), so that the following equation is satisfied
When FETs 31 and 35 and capacitors 15 and 51 are selected, C ₁ +Cgs ₁ ≒ (C ₂ +Cgs ₂ ) (gm ₁ /gm ₂ ) (10) Zd in the above equation (9) becomes as follows.

Zd≈gm ₁ (11) This makes it possible to suppress the influence of the above-mentioned parallel capacitance 63, and it becomes possible to operate the circuit shown in FIG. 2 as an active inductor in a high frequency band.
Furthermore, as can be seen from equation (8), by increasing the capacitance C ₁ of the capacitor 15, the inductance value of the active inductor can be made larger than that of the first embodiment, and the capacitor 15 and By changing the capacitances C ₁ and C ₂ of FET 31 so as to satisfy the above equation (10),
There is an advantage that an active inductor having an arbitrary inductance value can be realized without changing the structure such as the gate width of the active inductor.

In the above second embodiment, the capacitor 1
5 and 51 are provided, but the present invention is not limited to this, and at least a capacitor 15 may be provided.
When only capacitor 15 is provided (C ₂ = 0), (10)
The capacitance of the capacitor and
It is necessary to set the FET's mutual conductance, gate length, or depletion layer capacitance Cgs. In addition, in the second embodiment, when two capacitors 15 and 51 are provided, compared to a case where only capacitor 15 is provided among the two capacitors 15 and 51,
This has the advantage that it is easy to set the capacitance of the capacitor and the mutual conductance of the FET so as to satisfy equation (9).

[Effects of the Invention] As detailed above, according to the present invention, the source-grounded first field-effect transistor and the gate-grounded second field-effect transistor are connected in cascade, and the resistor is connected to the first field-effect transistor. Since the gate electrode of the transistor is connected to the drain electrode of the second field effect transistor, a current approximately equal to the current i flowing through the resistor and the depletion layer capacitance of the first field effect transistor flows through the depletion layer of the second field effect transistor. The layer capacitance supplies the drain electrode of the first field effect transistor. Therefore, the drain current of the second field effect transistor is reduced by the above current i, so that the current flowing into one terminal of the active inductor does not include the above current i, and the inductance of the two terminals of the active inductor decreases. can suppress the decrease compared to the conventional example.
Moreover, it can be constructed using only field effect transistors and resistors, and there is no magnetic field leakage.
It can be made smaller than the conventional spiral inductor.

Further, in addition to the above configuration, since a capacitor is provided between the source electrode and gate electrode of the first field effect transistor, the inductance of the active inductor can be increased by the capacitor. Therefore, in addition to suppressing the decrease in inductance, there is an advantage that an active inductor having an arbitrary inductance can be realized by changing the capacitance of the additional capacitor.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an active inductor according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of an active inductor according to a second embodiment of the present invention, and FIG.
A plan view of the conventional spiral inductor, Part 3
Figure B is a longitudinal sectional view taken along the line A-A' in Figure 3A, and Figures 4 and 5 are the singles of the second conventional example.
A circuit diagram of an active inductor using FET and dual FET, Figure 6 is a circuit diagram of the equivalent circuit of the circuit of Figures 4 and 5, Figure 7 is a circuit diagram of the active inductor of Figure 4 and the equivalent circuit of Figure 6. Figure 8 is a Smith Chart showing the calculated frequency loci of the series circuit of the resistor and inductor in Figure 1, and Figure 9 is a Smith Chart showing the calculated frequency loci of the active inductor in Figure 1 and the series circuit of Figure 6. 4 is a diagram showing the frequency characteristics of each inductance of the active inductor of FIGS. 1 and 2 and the active inductor of FIG. 4. FIG. 31, 35... Field effect transistor (FET), 32, 36... Drain, 33, 37
...Source, 34,38...Gate, 16,50
...Resistor, 15,51...Capacitor.

Claims (1)

[Claims] 1 A first field effect transistor, a source electrode connected to the drain electrode of the first field effect transistor, and a gate electrode connected to the first field effect transistor.
a second field effect transistor connected to the source electrode of the field effect transistor; and a resistor connected between the gate electrode of the first field effect transistor and the drain electrode of the second field effect transistor. An active inductor, characterized in that the drain electrode and gate electrode of the second field effect transistor are two terminals. 2. The active inductor according to claim 1, further comprising another resistor between the drain electrode and the gate electrode of the second field effect transistor. 3 a first field effect transistor, a source electrode connected to the drain electrode of the first field effect transistor and a gate electrode connected to the first field effect transistor;
a second field effect transistor connected to the source electrode of the field effect transistor; a resistor connected between the gate electrode of the first field effect transistor and the drain electrode of the second field effect transistor; An active inductor comprising a capacitor connected between the gate electrode and the source electrode of the first field effect transistor, and the drain electrode and the gate electrode of the second field effect transistor are two terminals. 4. The active inductor according to claim 3, further comprising another capacitor between the source electrode and gate electrode of the second field effect transistor. 5. The active inductor according to claim 3, further comprising another resistor between the drain electrode and the gate electrode of the second field effect transistor.