JPH0525133B2 - - Google Patents

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention relates to a complex computer system equipped with a shared memory, and in particular, the present invention relates to a complex computer system equipped with a shared memory. The present invention relates to a request buffer control method for controlling input/output of a request buffer that temporarily stores input/output requests to a memory.

(Prior Art) In a complex computer system equipped with a shared memory, a bus control device is prepared for each computer that shares the shared memory. This bus control device has a FIFO (first-in-first-out) request buffer that temporarily stores input/output requests to shared memory or main memory that are transferred from the input/output channel via the input/output bus. There is.

Since shared memory is a memory device that allows access from multiple computers (computer systems), it is placed physically far away from each system, and is connected to each system using relatively long cables. Because it is connected, it is slower than the main memory used within each system. Furthermore, the shared memory is instantaneously overloaded due to requests from multiple systems, resulting in a long access time. For this reason, input/output requests to the shared memory from the input/output channel are often made to wait. At this time, even if the input/output request subsequent to this input/output request is a request to the main memory and the main memory can be accessed, the input/output request is forced to wait in the request buffer, which is a problem.

(Problems to be Solved by the Invention) As mentioned above, conventionally, when an input/output request to shared memory (low-speed resource) is kept waiting, subsequent input/output requests to main memory (high-speed resource) Even if it was, there was a problem with having to wait for everything.

This invention has been made in view of the above circumstances, and its purpose is to prevent input/output requests to the other memory among subsequent input/output requests, even when an input/output request to either the shared memory or the main memory is pending. The object of the present invention is to provide a request buffer control method that does not necessarily require waiting for requests.

[Structure of the Invention] (Means and Actions for Solving the Problems) This invention provides a bus control device prepared for each system of a complex computer system that transmits input/output requests from an input/output channel to a shared memory. temporarily store
A FIFO-type first request buffer and a FIFO-type second request buffer that temporarily stores input/output requests to the main memory are provided.
Based on the busy signal and the second busy signal indicating that the main memory is busy, an input/output request is taken out from either the first or second request buffer and transferred to the shared memory or main memory via the system bus. For example, when the shared memory is in a busy state, it is possible to take out an input/output request to the main memory from the second request buffer.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a complex computer system to which the present invention is applied. In the figure, 10 is a shared memory shared by a plurality of computers (computer systems) such as a computer 20. The shared memory 10 has multiple input/output ports, one of which is connected to the system bus 2 of the computer 20.
Connected to 1. Further, the input/output ports of the shared memory 10 are respectively connected to system buses of other systems.

In the computer 20, 22 is a main memory.
Main memory 22 is connected to system bus 21 . 23 is an input/output bus, 24 is this input/output bus 2
3 and a bus control device connected to the system bus 21; 25 is an input/output channel connected to the input/output bus 23;

In the bus control device 24, 31 is a bus receiver connected to the input/output bus 23, and 32 temporarily stores an input/output request to the shared memory 10 (low-speed resource) input by the bus receiver 31.
A FIFO type request buffer (hereinafter simply referred to as a buffer) 33 is a FIFO type request buffer (hereinafter simply referred to as a buffer) that temporarily stores input/output requests to the main memory 22 (high-speed resource) input by the bus receiver 31. ). 34
Reference numeral 35 indicates a control unit that controls various parts of the bus control device 24 such as buffers 32 and 33, and a bus driver 35 that sends input/output requests taken out from the buffer 32 or 33 onto the system bus 21.

The control unit 34 includes a clock signal CLK synchronized with the bus cycle of the input/output bus 23, a memory start signal 41, a request identification bit 42, and a shared memory busy signal (hereinafter referred to as SM busy signal) 43.
and a main memory busy signal (hereinafter referred to as MM busy signal) 44. The memory start signal 41 is supplied from a specific signal line on the input/output bus 23, and indicates (at low level) that an input/output request is being sent onto the input/output bus 23. The request identification bit 42 is, for example, the first bit of the input/output request input by the bus receiver 31, and indicates whether the request is for the shared memory 10 (if 1) or the main memory 22 (if 0). Note that the input/output request is determined by the request identification bit 42.
In addition, it has memory address information and function information for specifying operations such as read/write (and write information in the case of a write operation). SM
The busy signal 43 is supplied from the shared memory 10 and indicates whether the shared memory 10 is in a state in which requests cannot be accepted (when it is Low) or not (when it is High). Further, the MM busy signal 44 is supplied from the main memory 22, and indicates whether the main memory 22 is in a state where it cannot accept requests (when it is Low) or not (when it is High).

Next, the operation of one embodiment of the present invention will be explained with reference to the timing chart of FIG.

Now, it is assumed that an input/output request A11 for the shared memory 10 is sent from the input/output channel 25 onto the input/output bus 23, and the memory start signal 41 on the specific signal line of the input/output bus 23 becomes active (Low). The control unit 34 controls the bus receiver 31 when the memory start signal 41 is active.
Set to input enable state. As a result, the bus receiver 31 inputs the input/output request A11 on the input/output bus 23. A request identification bit 42, which is the first bit of the input/output request A11, is supplied to the control section 34. The control unit 34 checks whether the input/output request A11 input by the bus receiver 31 is for the shared memory 10 or the main memory 22 based on the logical value of the request identification bit 42, and
If the request is for the shared memory 10 as in this example, the request A11 is temporarily stored in the buffer 32. At this time, the input/output request preceding the input/output request A11 is not stored in the buffer 32, the input/output request is not stored in the buffer 33, and the SM busy signal 43 from the shared memory 10 is high. If this indicates that the shared memory 10 is in a ready state, the control unit 34 immediately takes out the input/output request A11 temporarily stored in the buffer 32 to the bus driver 35, and transfers it to the system bus via the bus driver 35. 21. On the other hand, if the SM busy signal 43 is low as shown in FIG. 2, indicating that the shared memory 10 is in a busy state, the input/output request A
11 to the system bus 21.

Now, on the input/output bus 23, there is an input/output request A1.
1, an input/output request A to the main memory 22
21 and A22 are transmitted consecutively.
These input/output requests A21 and A22 are input/output requests A21 and A22.
Similarly to 11, it is input by the bus receiver 31. Since the input/output requests A21 and A22 input by the bus receiver 31 are requests for the main memory 22, they are temporarily stored in the buffer 33 under the control of the control section 34. At this time, it is assumed that no input/output request (to the main memory 22) that precedes the input/output request A21 exists in the buffer 33. Further, as shown in FIG. 2, the SM busy signal 43 is low and the shared memory 10 is in a busy state, and the MM busy signal 44 is low as shown in FIG.
It is assumed that the main memory 22 is in a ready state when it is High. In this case, the control unit 34
is the input/output request A2 temporarily stored in the buffer 33.
1, A22 immediately and in the order of storage
5 and sends it out onto the system bus 21 via the bus driver 35. As a result, the input/output requests A21 and A22 are not affected by the input/output request A11, which was issued earlier but whose execution is awaited.
Executed promptly.

When the SM busy signal 43 eventually becomes High as shown in FIG.
The input/output request A11 stored in 2 is taken out by the bus driver 35 and sent onto the system bus 21 via the bus driver 35. As a result, the input/output request A11 is executed.

Note that if the shared memory 10 and the main memory 22 become ready while an input/output request waiting to be executed is stored in both the buffers 32 and 33, the input/output request will be sent from either of the buffers 32 and 33. It is necessary to decide whether to take out the This decision is made by prioritizing input/output requests to the main memory 22, which is a high-speed resource, and making input/output requests to the shared memory 10, which is a slow resource, wait until the buffer 33 is empty; Until then, various methods can be applied, such as a method of alternately extracting input/output requests from the buffers 32 and 33.

In the above explanation, the request identification bit 42 is provided in the input/output request, and the logic value of this bit 42 is used to identify whether the input/output request is for the shared memory 10 or the main memory 22, but this is not limited to this. It's not a thing. For example, by detecting whether the address position indicated by the address information in the input/output request falls within the address area allocated to the shared memory 10 or the address area allocated to the main memory 22 using a comparator or the like, the input/output It is also possible to identify the output request destination.

[Effects of the Invention] As detailed above, according to the present invention, even when an input/output request to either the shared memory or the main memory is awaited, the input/output request to the other memory among the subsequent input/output requests is processed. Output requests do not necessarily have to wait. Therefore, input/output requests to the main memory, which is a high-speed resource, do not have to wait because the shared memory, which is a low-speed resource, is in a state where requests cannot be accepted, and the throughput of input/output processing is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a composite computer system to which the present invention is applied, and FIG. 2 is a timing chart for explaining the operation. 10...Shared memory, 20...Computer, 22...
...Main memory, 23...I/O bus, 24...Bus control device, 25...I/O channel, 32, 33
... Buffer (request buffer), 34... Control unit.

Claims (1)

[Scope of Claims] 1 A shared memory, a plurality of computers that share this shared memory, a system bus to which the shared memory is connected, a main memory connected to this system bus, this main memory and the shared A plurality of bus controllers each having at least one input/output channel for performing data input/output using memory, and a bus controller for transmitting input/output requests from the input/output channel to the shared memory or main memory via the system bus. a first-in-first-out method in which input/output requests from the input/output channels to the shared memory are temporarily stored in the bus control device of each of the computers; a request buffer; a first-in-first-out second request buffer for temporarily storing input/output requests from the input/output channel to the main memory; and whether or not the shared memory is in a state in which requests cannot be accepted. The input/output request is made from either the first request buffer or the second request buffer based on a first busy signal indicating whether or not the main memory is in a state in which requests cannot be accepted. control means for extracting the data and sending it to the corresponding shared memory or main memory via the system bus; In this case, the input/output request is retrieved from a request buffer that stores an input/output request to a memory that is in a request-acceptable state, which is the other one of the first request buffer or the second request buffer. Request buffer control method.