JPH0525154B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a memory card used as an external memory for OA (office automation) equipment, such as a word processor. [Technical background of the invention and its problems] In recent years, with the advancement of semiconductor packaging technology, memory cards with built-in semiconductor memory elements have come to be used as external memory in office equipment such as word processors. . In many conventional memory cards, the terminals of the memory chip are used as they are as an interface with the main body of the data processing device. In other words,
Address signals, data signals, write signals, output enable signals, and chip select signals were output directly to the outside of the memory card. This method can be implemented relatively easily if the memory card has one or two memory chips and has a relatively small capacity, since there is no need to incorporate peripheral circuits into the card. However, it is not suitable for realizing a relatively large capacity card mounting 4 to 8 memory chips. because,
This is because address signal lines equal to the memory capacity are required, so the number of address signal lines must be increased as the memory capacity increases. The basic size of modern memory cards is 54 x 86 mm, which is the size of a business card, and there are restrictions on the number of interface signals that can be held within this size. Furthermore, the mounting of the connector part,
This is because, from the viewpoint of contact reliability and cost, it is desirable that the number of interface signal lines be as small as possible. [Object of the Invention] The present invention has been made in view of the above circumstances, and provides a memory card that can be accessed at high speed without increasing the number of interface signal lines even if the built-in memory capacity is large. The purpose is to [Summary of the Invention] In order to achieve the above object, the present invention incorporates an address counter and an address update circuit in a memory card. This eliminates the need for direct addressing of the memory chip from the external interface, thereby reducing the number of address signal lines on the memory card. Furthermore, when accessing consecutive memory addresses, the addresses are automatically updated by simply repeating WRITE MEMORY DATA or READ MEMORY DATA on the data processing device main body side, eliminating the need to reset the addresses. That is, consecutive memory addresses can be accessed easily and at high speed. [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is an interface gate array. The interface gate array 1 is located between the main body of the data processing device (not shown) and the memory chip 2, and has a built-in control circuit for controlling data transfer between the main body and the memory.
Memory chip 2 is a static random access memory (SRAM) consisting of a 64K bit CMOS memory with an 8K x 8 bit configuration. In the embodiment of the present invention, eight SRAMs are installed, resulting in a total memory capacity of 64 Kbytes. 3 is a power supply control circuit, and 4 is a backup battery, which is provided to hold the contents written in the memory when the memory card is not connected to the main body. When the memory card is connected to the main unit, the power supply control circuit 3
It has a switching circuit that supplies 5V and supplies power from the backup battery 4 when it is not connected to the main body. Furthermore, when +5V is not supplied from the main unit, there is a signal (CE) for prohibiting all operations for the interface gate array 1 .
supply. FIG. 2 is a diagram showing an example of the internal configuration of the interface gate array shown in FIG. 1. The interface array 1 includes counters 11 to 13, buffers 21 to 32, decoders 41 and 42, and a selector 5.
1, 52, and a control circuit 61. Counters 11 to 13 are address counters whose memory addresses are set in response to memory access from the main body. RmA ₀₀ to RmA ₁₉ indicate counter contents, that is, memory addresses. Buffers 21-27 receive signals from the main body, and buffers 28-32 are used to send signals to the memory chip. The decoder 41 generates a control signal from the address signals AD ₀ and AD ₁ ,
Decoder 42 produces chip select signals 0-7 from the memory addresses. The selector 51 selects which signal is to be sent to the main body from among the contents of the address counters 11 to 13 and the data read from the memory. The selector 52 selects the contents of the address counters 12 and 13 from the decoder 4 according to signals SZ0 and SZ1 that determine the capacity of the memory chip.
Select whether to send to 2. Control circuit 61 produces various signals that control each of the blocks described above. Here, we will briefly explain the interface signals with the data processing device main body. First, DT ₀ -DT ₇ (DATA) are 8-bit bidirectional data signals. The main body reads/writes the memory and reads/writes the address counters 11 to 13 via this signal. AD ₀
-AD ₁ (ADDRESS) is an address signal for selecting an input/output port in the memory card. RD (READ) is a signal output when reading from a memory card. WR (WRITE) is a signal output when writing to a memory card. CS (CARD SELECT) is a signal to the memory card. The main unit must output this signal when accessing the memory card. CE (CARD ENABLE) is a signal that is enabled for the memory card. This signal is input from the power control circuit 3 within the memory card. WP (WRITE PROTECT) is a write protection signal. This signal can be provided by an interface signal from the main body, a write protect switch attached to the memory card, or a jumper within the memory card. When this signal indicates the write protection state, write operations to the memory chip 2 are prohibited. Additionally, the state of this signal can be read from the main body. JP ₀ -JP ₂ (JUMPER OPTION) are 3-bit jumper options that can be set arbitrarily.
This jumper option can be read from the main body. This signal is used, for example, to identify the type of memory card when multiple types of memory cards are used in the same system. SZ0-SZ1 (MEMORY SIZE) are signals for setting the capacity of the memory chip.
64KB (8KB x 8), 256KB (32KB x 8), 1MB
(128 KB x 8) or 2 MB (256 KB x 8) memory chips can be connected, and the capacity of the memory chip is specified by this signal. Next, we will briefly explain the interface signals with the memory. mD ₀ -mD ₇ (MEMORY DATA) are bidirectional data signals through which read/write data to memory is sent. mA ₀ −mA ₁₇ (MEMORY
ADDRESS) is an address signal for memory. It has an address space of 256KB. 0-7 (MEMORY CHIP
SELECT) is the chip select signal for the memory. Up to 8 memory chips can be connected. (MEMORY WRITE ENABLE)
This is a write signal to memory. (MEMORY OUTPUT ENABLE)
is the output enable signal for the memory.
This signal is output during a memory read operation. Figures 3 and 4 are timing charts showing the operation of the embodiment of the present invention.
MEMORY READ each. Figure 5・
FIG. 6 is a diagram cited to explain the operation of the embodiment of the present invention, and is a diagram showing a data format when writing a memory address to be accessed to the address counter, and a data format when reading it, respectively. It is. Hereinafter, the operation of the embodiment of the present invention will be explained in detail. The interface gate array 1 has four input/output ports, which are selected by the address signal (AD _{0 to 1} ), read by the read signal (RD), and written by the write signal (WR). . Read and write operations to the input/output port are performed only when the card select signal (CS) and card enable signal (CE) are both "1". The following table shows the input/output ports and an overview of their operations.

【table】

〔Effect of the invention〕

As described above, according to the present invention, by incorporating an address counter into the memory card, there is no need to address the memory chip directly from an external interface, and the number of address signal lines of the memory card can be reduced. In addition, when accessing consecutive memory addresses on a memory card, the main unit uses WRITE MEMORY.
The address is automatically incremented by simply repeating DATA or READ MEMORY DATA, and there is no need to reset the address. That is, consecutive memory addresses can be accessed easily and at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of the interface gate array in FIG. 1, and FIGS.
The figure is a timing chart showing the operation of the embodiment of the present invention.
Indicates each READ. 5 and 6 are diagrams cited to explain the operation of the embodiment of the present invention, and respectively show the data format when writing a memory address to be accessed to the address counter and the data format when reading. FIG. 3 is a diagram showing a format. 1 ... Interface gate array, 2... Memory chip, 3... Power supply control circuit, 4... Backup battery, 11-13... Address counter, 21-32... Buffer, 41, 42... Decoder, 51 , 52...Selector, 61...Control circuit.

Claims (1)

[Scope of Claims] 1. In a memory card that has a built-in readable/writable memory chip and is removably attached to a data processing unit, a data input/output terminal that is shared for read/write data input/output and address data input. an address counter that outputs a memory address for read/write access to the memory chip; and an address counter that outputs a memory address for read/write access to the memory chip; and an address counter that is supplied to the data input/output terminal by the data processing device main body in response to an address setting command from the data processing device main body. and address setting means for setting a memory address to be stored in the address counter. 2. In a memory card that has a built-in readable/writable memory chip and is removably attached to the data processing unit, a data input/output terminal that is shared for input/output of read/write data and input of address data, and a terminal for reading/writing the memory chip / an address counter that outputs a memory address for write access; and an address counter that outputs a memory address for write access; A memory card comprising: address setting means for setting an address counter; and updating means for updating the contents of the address counter each time the memory chip is read/written.