JPH0525226B2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a signal processing circuit for a solid-state imaging device;
In particular, it relates to signal processing circuits for MOS solid-state imaging devices.

Background technology A CCD type solid-state image sensor (hereinafter abbreviated as CCD area sensor) with a horizontal charge-coupled device (HCCD) and a MOS type solid-state image sensor (hereinafter abbreviated as MOS area sensor) with a horizontal signal line (HSL). ) is publicly known. Since these area sensors generate characteristic noise along with their output signals, many prior art techniques have been proposed for noise removal. JP-A No. 53-40215 discloses that a horizontal signal line and a reference power source are connected by a reset transistor, and a horizontal signal line of a vertical signal line is connected by a horizontal scanning transistor and a clear transistor connected in parallel. Television Image Engineering Handbook,
Page 432 shows how to connect the signal line and reference power supply using a reset transistor in a MOS line sensor.
It also discloses sampling the signal voltage. Sekin & Tompset, charge transfer device,
Kindai Kagakusha, 49 pages, and Howes & Morgan,
Charge−Coupled Devices & systems, John
WiLey&sons, page 74 discloses processing the signal voltage of a CCD area sensor by means of phase-box double sampling technique.

DISCLOSURE OF THE INVENTION The above prior art improves the SN ratio of a MOS area sensor or a CCD area sensor. However, the SN ratio of solid-state imaging devices needs to be further improved, and many problems need to be solved for practical use. Equipped with a conventional reset transistor that connects the horizontal signal line and the reference power supply
The problem with MOS area sensors is that the signal charge is divided into the vertical signal line and horizontal signal line, so the signal voltage on the horizontal signal line becomes small. Because the horizontal signal line is not sufficiently charged due to the large capacitance of the vertical signal line and the short turn-on time of the horizontal scanning transistor, only about 30% of the signal charge of the photocell is sent to the HSL. The clear operation of the clear transistor performed during the horizontal blanking period causes fixed noise charges to remain in the vertical signal line (VSL). The above-mentioned fixed noise charges are generated due to variations in the horizontal scanning transistor and the clear transistor or variations in the horizontal scanning pulse voltage and the clear pulse voltage. The problem with conventional CCD area sensors that use phased double sampling circuits is that the clamp circuit and sample hold circuit of the phased double sampling circuit involve switching operations, making it difficult to configure them with bipolar signal processing circuits. It is a certain thing. Furthermore, the clock noise of the above-mentioned clamp circuit and sample-and-hold circuit reduces the signal-to-noise ratio of the signal. The present invention has been made to solve the above problems. Several independent inventions are disclosed to solve the above problems. These independent inventions are described together because they are deeply interrelated and produce synergistic effects when practiced together.
The present invention is therefore an improvement in the SN ratio of a solid-state imaging device. JP-A-58-15374, JP-A-58-59681, and JP-A-57-187173 are prior inventions of the present invention filed by the present applicant. JP57-41081, JP57
−65073, JP 57-83974, JP 58-145153, Special
No. 57-107771, Japanese Patent Application No. 57-129146, Japanese Patent Application No. 58-6134, and Japanese Patent Application No. 58-20405 are prior inventions related to the present invention.
The features and advantages of the present invention are explained below.

The basic features of the present invention include: a charge-coupled device for transferring signal charges; an output diode for receiving the signal charges provided at the output end of the charge-coupled device;
A reset switch that resets the output diode, a coupling capacitor to which the signal voltage of the output diode is input via an amplifier, a clamp circuit that clamps the other end of the coupling capacitor, and a circuit that connects the other end of the coupling capacitor to the other end of the coupling capacitor. In a solid-state imaging device comprising an analog transmission gate to which a signal voltage is input directly or via an amplifier, the first period in which the reset switch operates is:
This period overlaps with the second period in which the clamp circuit operates.

Of course, this second period can also include the first period.

For example, in a MOS area sensor having one type of structure, the reset transistor operates during the first period to apply a reference potential to the horizontal signal line, and the clamp circuit operates during the second period to apply the reference potential to the coupling capacitor. A reference potential is applied to the two ends, and signal charges are read out from the storage capacitor to the HSL in the next third period. In this way, the reset noise caused by the reset transistor is greatly reduced, and the average signal voltage output is greatly increased compared to the embodiment in which a resistor is connected to the horizontal signal line. In the conventional example in which a horizontal switch circuit is configured by a horizontal scanning transistor and a clear transistor, and is equipped with the above-mentioned reset switch, the capacitance division between VSL and HSL and the shortening of the operation time of the horizontal scanning switch greatly reduce the HSL signal voltage. It got smaller. According to the present invention, it is possible to obtain a horizontal signal voltage 2 to 3 times higher than that of the conventional example described above, and furthermore, the horizontal scanning switch can be made smaller, so that the horizontal scanning noise is reduced. Additionally, set a second period after the first period, or
By setting the second period to overlap with the period, the reset noise output during or after the first period can be removed by the clamp circuit. As a result of the above, the signal-to-noise ratio was greatly improved.

In the above embodiments, other structures are added. Then, the output signal voltage is selectively transmitted by the sampling hold circuit or the analog transmission gate circuit during a fourth period other than the first period or the second period. In this way, horizontal scanning noise voltage can also be removed. However, before the fourth period begins, the signal charge needs to be read out from the storage capacitor to the HSL. In conventional line sensors, it is known to eliminate horizontal scan noise through the use of reset switches and sample and hold circuits. However, when applying this technology to an area sensor, due to the reason explained in Independent Invention 1.
The disadvantages were that the signal voltage of NSL was small and that VSL had a large residual signal charge. Furthermore, the signal-to-noise ratio decreased significantly due to reset noise. Furthermore, in the conventional phase-box double sampling technique, it was not known that by applying this technique to the MOS area sensor of Independent Invention 1, horizontal scanning noise can be removed together with reset noise. According to the present invention, since horizontal scanning noise and reset noise can be removed, it is possible to eliminate signal
The signal-to-noise ratio is greatly improved. Horizontal scanning noise is removed by using the horizontal switch circuit, reset switch, sampling hold circuit or analog transmission gate circuit of Independent Invention 1 and setting the first, third, and fourth periods so that they do not overlap. can. Furthermore, reset noise can also be removed by using a low-pass filter. Note, however, that noise charge remains in the HSL after the reset period (first period) due to clock voltage fluctuations or thermal fluctuations when the reset switch turns off. If this noise voltage is clamped via a capacitor (coupling capacitor), the S/N ratio can be further improved. This is due to the fact that the fluctuation noise described above does not change much over a short period of time. That is, low frequency components of fluctuation noise are cut out. The high frequency components are then suppressed by a low pass filter. In the horizontal switch circuit disclosed in Independent Invention 1, a signal charge of 80% to 95% or more of the signal charge of VSL is
The ability to transfer to HSL is explained by the applicant's prior invention. As a result, the problem of clearing residual signal charge (residual signal charge in VSL) by using a reset switch becomes easier. In the past, a clear switch connected in parallel with a horizontal scan switch generated a large amount of noise. This is due to variations in the clear pulse voltage and horizontal pulse voltage, and variations in threshold voltage or capacitance of the clear transistor and horizontal scanning switch. Furthermore, the reset switch of the present invention
Since it is only necessary to discharge the battery, it can be made smaller and its reset noise can be reduced. The above explanation is an explanation of both independent invention 1 and dependent invention 1. It should be noted that sampling of signal voltages by the analog transmission chain circuit is simpler than the sample-and-hold circuit disclosed in the conventional phase-box double sampling technique, and has the advantage that it can be constructed using a bipolar integrated circuit. In conventional sample and hold circuits, the noise voltage coexisting with the input signal voltage at the moment the sampling switch turns off is held only during the hold period. As a result, the above-mentioned instantaneous high-frequency noise voltage is lowered in frequency, and there is a drawback that it cannot be removed even by using a low-pass filter. By using an analog transmission gate circuit, the above-mentioned high frequency noise voltage is transmitted as is, and therefore can be easily removed by a low pass filter.

In another embodiment of the structure, the horizontal scan noise can be much smaller than in embodiments using horizontal scan transistors, allowing the fourth period to begin at a time when the third period does not end. The problem with dependent invention 1 is that it is necessary to set the first, second, third, and fourth periods within one pixel processing period. Conventional Sobako 2
In the heavy sampling technique, each period is set independently from each other. As a result, the operating time of each switch became very short, and the design became very difficult due to the increase in the number of pixels. For example, one pixel signal
When processing at 130nsec, each period is
20 nsec, with a transient period of about 13 nsec between each period. The present invention ameliorates the above problems.

In another embodiment of the structure, the fourth period may overlap the third period because the clamp circuit suppresses the transmission of switching noise of the reset switch. As a result, each period can be made longer than in the conventional double sampling technique. Increasing the signal transmission period (fourth period) improves the average SN ratio.

In other embodiments of the structure, the horizontal scan noise will be very small. Therefore, by setting the first period within the second period, a signal voltage with very small reset noise and horizontal scanning noise can be generated at the second end of the coupling capacitor. the result,
The sample and hold circuit or analog transfer gate can be set to any time period. Furthermore, the sample hold circuit and analog transmission gate circuit can be omitted. As a result, each period is longer, the average signal-to-noise ratio is improved, and circuit design is simplified. For example, when processing one pixel signal at 130 nsec, the first period starts at the same time as the second period, the first period is 40 nsec, the second period is 60 nsec, the fourth period is 70 nsec, and the third period starts at the same time as the second period. It is arbitrarily set to 4 periods.

In another embodiment of the structure, each HSL receives signal charge from a different VSL in each horizontal scan period. In this way, since each HSL can operate in an overlapping manner, the time required for processing one pixel signal increases significantly. In a preferred embodiment, HSL
2 or 4 are installed. In this way, each of the first to fourth periods becomes significantly longer, which facilitates circuit design and reduces clock power.

In another aspect of the structure, a simple bipolar analog transmission gate circuit is disclosed. In a preferred embodiment, the output signal voltage is generated from the collector of said bipolar transistor and said pulse circuit is a second bipolar transistor. In this way, in an embodiment in which a plurality of analog transmission gates are arranged, level differences due to variations in base-emitter voltage and increases in clock power can be suppressed.

In a CCD type linear or area sensor that has a DC MOS gate (potential barrier) between the HCCD and the output diode, the transfer clock noise of the HCCD is constant and very small, so the fourth period is executed before the third period ends. However, the deterioration of the SN ratio is very small. Of course, it is also possible to remove transfer clock noise with a low-pass filter. In this way, each period can be extended.

According to the present invention, the first to fourth periods can be extended. By overlapping the first and second periods, the first
~The fourth period can be extended. In preferred embodiments, sample and hold circuits or analog transmission gate circuits are omitted. The period other than the second period is the fourth period, and the third period is the fourth period.
Set within the period.

A problem with each of the above-mentioned inventions and conventional phase-box double sampling circuits is the design of a high-speed clamp circuit. Particularly in embodiments that do not have sample-and-hold circuits or analog transmission gate circuits, the clamp circuit must operate at high speed. (It is necessary to fix the potential of the second end of the coupling capacitor at high speed.) In adopting the structure of claim 13, the above problem is solved. That is, the clamp period (second
If, during a period of Suppresses the potential change at the second end of . Then, the above-mentioned potential fluctuation at the first end of the coupling capacitor is rapidly discharged due to the constant current discharge characteristic of the discharge circuit. During this discharge, the charging current of the emitter follower circuit is suppressed to zero or to a large extent. The more the emitter resistance of the discharge circuit is reduced, the larger the above discharge current becomes. In a preferred embodiment, a DC voltage is applied to the base of the second bipolar transistor, the control circuit is a third bipolar transistor, and the emitter follower transistor (of the charging circuit) and the base of the third bipolar transistor have opposite voltages. A phase pulse voltage is applied. In this way, the clamp circuit can be constructed from a bipolar transistor integrated circuit.
Furthermore, the second bipolar transistor can be operated in saturation. In a preferred embodiment, if the polarity of the signal voltage is designed so that the reset-off pulse noise voltage generated when the reset switch turns off reduces the above charging current, the falling transient waveform voltage of the reset-off pulse noise voltage decreases from the charging current. Since it works in the direction of increasing the emitter-base voltage of the emitter follower transistor in the circuit,
The falling transient waveform voltage of the reset-off pulse noise voltage mentioned above can be clamped at high speed. the result,
The clamp period can end immediately after the reset period ends.

In each of the above-mentioned inventions, it is equivalent to adding known or unknown electric parts to the extent that the basic operation is not impaired. Other features and effects of each of the above-mentioned inventions will be explained below.

Example Fig. 1 shows the correspondence box 2 explained in the section of the description of the prior art.
This is an equivalent circuit representing the heavy sampling technique.
The signal charge output from the CCD 1 is changed into voltage by the output diode 2, and the output diode 2
is reset to DC potential Vocl by reset switch 3. Node 2A is connected to clamp switch 6 via amplifier 4A and coupling capacitor 5. The node 5B is input to a sample hold circuit constituted by a sample switch 7 and a capacitor 8 via an amplifier 4B. Amplifier 4C has high input resistance. FIG. 2 is a clock waveform diagram of FIG. FIG. 3 is an equivalent circuit representing one embodiment of the present invention. VSL 12 and HSL 11 are connected by a horizontal switch circuit 6. Briefly, during the horizontal blanking period, the VSL signal charge is incompletely transferred to the second end of the first capacitor 9C via the first transfer gate having a DC gate potential.
Furthermore, it is incompletely transferred to the second end of the storage capacitor 9E via the second transfer gate 9D. The third capacitor 9A is a capacitor for stopping transfer, and the complete transfer gate 9F is a transfer gate for clearing noise charges. Third transfer gate 9 with DC gate potential
G is a potential barrier, and when the horizontal scanning circuit 10 applies the horizontal scanning pulse voltage Vx to the first end of the storage capacitor 9E, the signal charge at the second end is transferred to the HSL by crossing the potential barrier. . HSL11
is connected to reset switch 3 and amplifier 4A. Regarding the incomplete transfer operation and variations of horizontal switch circuits, reference is made to the above-mentioned prior application by the applicant. Amplifier 4A is connected to clamp circuit 6 via coupling capacitor 5. Then, the signal voltage at the second end of the coupling capacitor is outputted via the amplifier 4B. A clock waveform diagram of the signal processing circuit of FIG. 3 is illustrated in FIG. However, the voltage value and polarity can be freely designed. Since the first period in which the reset switch operates is included in the second period in which the clamp circuit operates, the potential at the second end 5B of the capacitor 5 is hardly affected by reset noise. And after the clamp switch turns off,
Since the third period in which the horizontal scanning pulse voltage is applied to the capacitor 9E is set, the signal voltage is output in the fourth period in which the HSL voltage is output. Since the horizontal scanning noise of the horizontal switch circuit described above is small, the dynamic range of the amplifier 4A may be small. However, in order to improve the SN ratio, an amplifier is required. 4A
preferably includes a voltage amplification amplifier built into the fixed image sensor. In one embodiment, the voltage amplification amplifier described above is a CMOS common source amplifier.
The above P-type well for the CMOS amplifier can be made using the same process as the P-type well for blooming suppression. However, it is desirable to create the resistor connected to the amplifier in the signal processing chip. FIG. 5 is an equivalent circuit diagram showing another embodiment of the present invention. 5 is basically the same as that shown in FIG. 4 with an analog transmission gate circuit 13 added thereto. However, other aspects of the horizontal switch circuit are disclosed. Specifically, the third capacitor 9F
and a fourth transfer gate 9H are added. these are
This is a MOS electrode, and signal charges are completely transferred.
FIG. 6 is a clock waveform diagram of one embodiment of FIG. 5.
The first period R1 in which the reset switch operates and the second period C2 in which the clamp circuit operates overlap. After the clamp period ends, a third period S3 is set in which a horizontal scanning pulse voltage is applied to the first end of the storage capacitor 9E, and a fourth period T4 in which the analog transmission gate circuit operates overlaps with the third period. The above-mentioned overlapping times are arbitrary. 7 and 8 represent an equivalent circuit of one embodiment of the clamp circuit. In FIG. 7, a clock voltage V2 is applied to the base of an emitter follower transistor 14, which is a charging circuit. The emitter is connected to the second end 5B of the coupling capacitor 5. The discharge circuit includes a second bipolar transistor 15, an emitter resistor 19, and a third biporter transistor 1 whose emitter is connected to a common emitter.
A DC voltage is applied to the base of the third bipolar transistor 16 comprising the transistor 6, and a clock voltage V2 is applied to the base of the second transistor 15 via a rectifier. One end of the rectifying element 17 is a resistor 1
8 to the first power supply Vs. If the clock voltage changes so that the base of the second transistor 15 becomes more than 0.5V lower (negative) than the base of the third transistor, the second transistor is cut off and the discharge stops. If the second end 5B is connected to an amplifier with high input resistance, then the second end 5B
The potential at B is held for a sufficiently long period of time so that emitter follower transistor 14 is also cut off by varying clock voltage V2 by 1V or more. Then, when the clock voltage V2 becomes positive again, the transistors 14 and 15 are turned on. It is possible to apply the clock voltage to the second terminal 5B via a rectifying element instead of the transistor 14. Further, it is possible to apply a DC potential to the emitter of the second transistor 15 via a rectifier instead of the third transistor 16. Figure 8
is a modified embodiment of FIG. 7, in which the second transistor 1
A DC current is applied to the base of the third transistor 16, and an anti-phase clock waveform 2 is applied to the base of the third transistor 16. Of course, the second transistor 1 is connected via a rectifier instead of the third transistor.
A clock voltage of 2 may be applied to the emitter of 5. Figure 9 is an applied example of Figure 5, in which HSL is
a second end 5 of the coupling capacitor 5;
It is disclosed that three analog transmission gate circuits are arranged in each of B2, B5 and B1. HSL11
A is connected to the odd-numbered VSL, and HSL11B is connected to the even-numbered VSL. The signal processing circuit connected to the HSL 11B operates at a phase that is 180 degrees different from that of the signal processing circuit connected to the HSL 11A. And analog transmission gate circuit 13
(A to F) separate color signals, respectively. Then, the separated color signals are added by adders 44A, B, and C. According to this embodiment, color separation is performed by arranging a plurality of analog transmission gate circuits shown in FIG. FIG. 10 is a sectional view of one embodiment of an analog transmission gate circuit. Three bipolar differential amplifiers 24, 25, and 26 are arranged, and each differential amplifier 24, 25, and 26 has the same structure. Each amplifier has a first transistor 20A, a collector resistor 23A connected to its collector, an emitter resistor 22A connected to its emitter, and a second transistor 21A connected to a common emitter. An input signal voltage is applied to the base of the first transistor 20A, and clock voltages V _4X , V _4Y , and V _4Z are applied to the base of the second transistor. It is possible to take out the output from the emitter, and it is also possible to apply the clock voltage through a rectifier instead of the second transistor. When the first transistor is cut off, its collector is held at the second power supply potential _VD . The analog transmission gate circuit of FIG. 9 may be understood with reference to FIG. FIG. 11 is an equivalent circuit for explaining one embodiment of the adder circuits 44A, B, and C in FIG. 9, and in particular only 44A is shown.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing a conventional phase-box double sampling circuit. FIG. 2 is a clock waveform diagram of FIG. FIG. 3 is an equivalent circuit diagram showing one embodiment of the present invention. FIG. 4 is a clock waveform diagram of FIG. 3. FIG. 5 is an equivalent circuit diagram showing another embodiment of the present invention. FIG. 6 is a clock waveform diagram of one embodiment of FIG. 5. 7 and 8 are equivalent circuit diagrams representing the lamp circuit of the present invention. FIG. 9 is a block diagram representing an applied embodiment of FIG. 5. FIG. 10 is an equivalent circuit diagram showing the analog transmission gate circuit of the present invention.
FIG. 11 is an equivalent circuit diagram showing the adder circuit.

Claims (1)

[Claims] 1. A charge-coupled device that transfers signal charges, an output diode provided at the output end of the charge-coupled device that receives the signal charges, a reset switch that resets the output diode, and an amplifier. a coupling capacitor to which the signal voltage of the output diode is inputted at one end; a clamp circuit that clamps the other end of the coupling capacitor; and an analog circuit to which the signal voltage is inputted from the other end of the coupling capacitor directly or via an amplifier. In a solid-state imaging device comprising a transmission gate, a first period during which the reset switch operates is:
A solid-state imaging device characterized in that the period overlaps with the second period in which the clamp circuit operates. 2. The solid-state imaging device according to claim 1, wherein the second period includes the first period.