JPH0527270B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an interconnect structure for an imaging array;
More particularly, it relates to interconnect structures for mercury cadmium telluride imaging arrays interconnected with silicon signal processing devices.

Description of the Prior Art The current method of connecting a mercury cadmium telluride focal plane array structure to a silicon signal processing chip involves running a gold wire from an indium pad on top of the zinc sulfide on the detector array to a silicon signal processing chip. A gold wire is glued to a pad on the chip carrier containing the chip, and then a gold wire is glued from the pad on the signal processing chip to a pad that already has a gold wire from the detector array. This interconnection method has a significant drawback in that it requires a large number of connections. Moreover, ball bonding on zinc sulfide insulators is extremely delicate;
If not done properly, leaks will occur at the electrodes. Bonding to indium on zinc sulfide requires pressing the cold capillary with low force, while bonding to metal on ceramic requires higher temperatures and pressures with smaller tolerances. . Because of these problems, the yield and reliability of the combined device is not high.

A method for making such an imaging array device is described in U.S. Pat. No. 4,231,149, assigned to Texas Instruments, Inc., entitled "Narrow Bandgap Semiconductor Charge Coupled Imaging Device and Method of Fabrication." This patent describes the fabrication of the imaging array itself.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for connecting focal plane arrays without using metal wires. It is also an object of the present invention to provide a structure having a focal plane array placed on a signal processing device.

An imaging structure is disclosed having several imaging devices arranged in an array and placed on a substrate. The substrate is placed on a silicon substrate with electrical circuitry. The imaging substrate has an opening placed over a bonding pad on a silicon substrate. The bonding pads are interconnected with electrical circuitry on the silicon substrate. The imager is selected to connect to conductors placed in these holes (i.e., apertures) and to an electrical bus that constitutes a connection from the imager on the imager substrate to the electrical circuitry made on the silicon substrate below. connected.

In a preferred embodiment of the invention, a mercury cadmium telluride imaging array is created having an array of imaging devices on the surface of a substrate. The substrate has holes along its edges. This hole is located directly above a bonding pad in a silicon substrate that is placed below the imaging substrate. This silicon substrate has an electric circuit such as a signal processing device. The imaging devices on the imaging array are connected to an aluminum bus. Note that this aluminum bus is connected to conductors that reside in holes near the edges of the imaging array and connect the imaging device to signal processing equipment and electrical circuitry provided in the underlying silicon substrate.

A method of forming an imaging array on a processing device chip is described. That is, a thin piece of HgCdTe is first attached to a silicon signal processing chip by a thin layer of epoxy. After thinning the HgCdTe chip, the holes in the imaging array are formed using registration areas on the silicon for alignment. Imaging arrays are made from various combinations of insulators and metals. Finally, the required gates of the imaging array are connected to the associated metallization areas on the silicon processing equipment chip using thick metal passing through the holes in the imaging array chip and epoxy.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a cross-sectional view of a package with a silicon chip 2 supporting a detector array 4 of mercury cadmium telluride HgCdTe. Detector array 4
are arranged accordingly on a signal processing device made on silicon 2. Detector array 4
The adhesive layer 7 is typically a low viscosity epoxy.
mechanically bonded to the silicon portion by. A region 6 is etched into the interior of the mercury cadmium telluride, creating an opening to the bonding region 5 on the silicon processing equipment chip 2. opening 6
are coupled to the remainder of the array 4 such that the image sensing elements in the array 4 and the signal interface on the bonding pad 5 of the signal processing device 2 are electrically connected. A bonding region 3 is provided on the non-conductive silicon oxide to allow external bonding to the package.

FIG. 2 shows a top view of the detector array structure.
Via regions 6 provide interconnections between the image sensing elements of the imaging array 4 and the underlying signal processing equipment. Bonding pads 5 provided at the ends of the silicon chips 2 are used to connect the signal processing equipment below the array 4 to external equipment. That is, via area 6 is for interconnection between the image sensing device of imaging array 4 and the underlying signal processing device, and bonding area 5 is for connecting the package to external equipment.

FIG. 3 shows via regions 6 in two rows of regions 6a and 6.
Another example using the interlaced arrangement of b is shown. This interlaced structure connecting the elements of the imaging array 4 to the underlying silicon signal processing equipment allows for an increased number of vias to be placed along the edges of the array 4.

FIG. 4 shows a top view of a single via region of a mercury cadmium telluride detector array. The surface of the detector array 20 has an aperture 22 approximately 25 microns square.
There is. This opening 22 exposes the epoxy just below the mercury cadmium telluride data array and for connecting the array to the signal processing equipment below. Additionally, an aperture 25 is provided in the center of the first aperture 22, which is approximately 15 microns square and exposes the actual bonding pad in the silicon containing the signal processing device. Next, an infrared detection array is created. During this process, several layers of an insulator, preferably zinc sulfide, are deposited on the HgCdTe chip surface 20 and the HgCdTe opening 22 over the epoxy, with a total thickness of about 1 micron.
After all of the insulating layers are deposited, an opening 25 approximately 10 microns square is formed by etching the deposited insulator and epoxy down to the metal pad 26 on the silicon. A layer of aluminum 23 is then deposited on top of the insulating layer and in contact with bonding pad 26. This aluminum layer 23 extends to a bus 27 that is electrically connected to the mercury cadmium telluride surface imaging array element. A layer of indium 21 is then deposited over the aluminum region 23.

FIG. 5 is a cross-sectional view of the structure shown in FIG. 4. Referring to FIG. 5, the silicon region 30 is
Bonding pads 32 are included to connect the detector elements in the mercury cadmium telluride array to a signal processing device in silicon 30. As previously mentioned, an epoxy layer 31 is provided between the mercury cadmium telluride layer 33 and the silicon layer 30. Additionally, an insulating layer 36 of zinc sulfide that is transparent to infrared radiation insulates the mercury cadmium telluride array 33 from the bus 34. Indium layer 35
However, aluminum bus bonding pad 32
is placed on top of the connection to.

The process of forming the above configuration is as follows. First, the back side of the surface of the mercury cadmium telluride substrate is polished in parallel, and this back side is oxidized or
Alternatively, perform processing to minimize recombination of decimal carriers. A signal processing device disposed on a single semiconductor substrate is fabricated to include bonding pad connections for interconnecting the signal processing device to the image sensing element on the mercury cadmium telluride array, and an epoxy includes the processing device. It is applied over the chips. In a preferred embodiment, some pressure is applied to the low viscosity epoxy to uniformly cure the epoxy to a thickness of 1 micron or less. A mercury cadmium telluride substrate is then placed on top of the epoxy and polished to a final thickness of 10 to 40 microns. The width of the mercury cadmium telluride substrate is then defined to expose the external bonding pad on the silicon. Expose the photoresist on the mercury cadmium telluride array so that the array itself is not removed. The unnecessary portions of the mercury cadmium telluride array are removed by cutting or by immersing the entire array in a bromine/methanol etchant (containing about 1% bromine) at a low temperature of 60°C or lower. Next, an opening in the mercury cadmium telluride array is made down to the epoxy directly above where the leads of the image detection array are to be connected to the signal processing device. The openings may be made by ion milling or by static etching using a methanol solution containing 1% bromine. The bromine methanol solution increases the aperture entrance compared to ion milling, but undercuts the bottom of the photoresist to create the desired tapered aperture. The purpose of this step is to remove the mercury cadmium telluride down to the epoxy layer, without disturbing the epoxy layer. This is because the epoxy layer will later be used to bond the zinc sulfide. The surface of the mercury cadmium telluride is then oxidized. At this stage, an infrared detector array is created. This process creates various levels of insulators and metal gates for signal detection, storage and/or manipulation. Several layers of insulating components are stacked on the HgCdTe opening and its edges. This insulating layer is zinc sulfide and has a total thickness of 1 to 1.5 microns. Zinc sulfide insulates the mercury cadmium telluride edges of the via openings from the connections. This insulating layer must adequately cover the stepped edges of the mercury cadmium telluride. Retaining the portion of the epoxy layer below the stepped edge of the mercury cadmium telluride layer provides the epoxy with an adhesive bond to support the insulating layer. Now, a small opening in the bottom of the via is created by removing the zinc sulfide insulating layer and epoxy to expose the bonding pad that connects to the signal processing device. This opening is formed by ion milling (and etching solution).
(removal of ZnS). A 1000 angstrom layer of aluminum is then deposited to connect the signal processing device bonding pads to the detector array. A 12,000 angstrom thick indium bus is then connected to the aluminum deposited in the vias, connecting the elements contained in the mercury cadmium telluride detector array to the signal processing equipment provided in the underlying silicon.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an imaging array structure according to the present invention. FIG. 2 is a plan view of the imaging array structure shown in FIG. 1. FIG. 3 is a plan view showing another arrangement of via connections in the imaging array. FIG. 4 is a plan view of the via structure. FIG. 5 is a cross-sectional view of the via structure. 22, 25...opening, 30...first substrate, 31
...First electrical insulating layer, 26, 32... Bonding pad, 33... Second substrate, 23, 27, 34
. . . electrical connection portion, 36 . . . second electrical insulating layer.

Claims (1)

[Scope of Claims] 1 (a) a substantially flat first substrate having an electric circuit on one plane; (b) disposed on the one plane of the first substrate, the first (c) a substantially flat second substrate having a detector array on a plane remote from the substrate; and (c) fixing the second substrate substantially parallel to and insulated from the first substrate. , a first electrically insulating layer attached to a surface of the second substrate opposite to the plane on which the detector array is provided, and (d) a side wall penetrating the second substrate and the first electrically insulating layer. (e) a second electrically insulating layer disposed on a side of the second substrate remote from the first substrate and extending along a sidewall of the opening; (f) Passing through an opening formed in the first electrically insulating layer and the second substrate while ensuring insulation with respect to the second substrate by the second electrically insulating layer, from the first substrate in the second substrate. an integrated detector array and signal processor comprising electrical connections coupled from a remote side to circuitry of the first substrate. 2. The first substrate is substantially made of silicon;
The integrated detector array and signal processor of claim 1, wherein said second substrate is made of mercury cadmium telluride. 3. The integrated detector array and signal processor of claim 2, wherein the first electrically insulating layer is made of epoxy resin. 4. The electrical circuit includes a bonding pad,
3. The integrated circuit of claim 2, wherein said electrical connection extends to said bonding pad while remaining isolated from said second substrate by an infrared transparent electrically insulating layer. Detector array and signal processor.