Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH0528904B2 - - Google Patents
[go: Go Back, main page]

JPH0528904B2 - - Google Patents

Info

Publication number
JPH0528904B2
JPH0528904B2 JP17450486A JP17450486A JPH0528904B2 JP H0528904 B2 JPH0528904 B2 JP H0528904B2 JP 17450486 A JP17450486 A JP 17450486A JP 17450486 A JP17450486 A JP 17450486A JP H0528904 B2 JPH0528904 B2 JP H0528904B2
Authority
JP
Japan
Prior art keywords
epitaxial growth
pattern
silicon wafer
distance
pattern shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP17450486A
Other languages
Japanese (ja)
Other versions
JPS6329943A (en
Inventor
Yasuhide Komatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP17450486A priority Critical patent/JPS6329943A/en
Publication of JPS6329943A publication Critical patent/JPS6329943A/en
Publication of JPH0528904B2 publication Critical patent/JPH0528904B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、シリコンのエピタキシヤル成長後の
評価方法に関するものであり、特に、埋込み層を
有したシリコンウエハースにエピタキシヤル成長
を行なうときに生じる、下地のパターンとエピタ
キシヤル層表面のパターンとのズレ、すなわち、
パターンシフト量を測定する方法に関するもので
ある。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for evaluating silicon after epitaxial growth, and in particular, the present invention relates to a method for evaluating silicon after epitaxial growth. , the misalignment between the underlying pattern and the epitaxial layer surface pattern, that is,
The present invention relates to a method of measuring the amount of pattern shift.

〔従来の技術〕[Conventional technology]

従来、この種のパターンシフト量の測定方法
は、シリコンウエハースに埋込み層を形成する工
程と、埋込み層が形成されたシリコンウエハース
にエピタキシヤル成長を行なう工程と、エピタキ
シヤル成長済みウエハースをダイヤモンドポイン
ト等の切断工具により数ミリ角のチツプに切断
し、このチツプを研磨治具にワツクスを用いて貼
付し、角度研磨を行なう工程と、角度研磨了後の
チツプを研磨治具から取外し、ワツクス除去のた
めの洗浄をし、ステンエツチを行ない、埋込み層
を着色させ埋込み層が目で見えるようにする工程
と、ステンエツチ液を除去するための水洗、乾燥
を行なう工程と、表面パターンと、ステンエツチ
により着色された下地埋込みパターンとのズレを
顕微鏡に取付けられた測数計を用いてパターンシ
フト量を測定する工程とで構成されていた。
Conventionally, this type of method for measuring the amount of pattern shift involves a process of forming a buried layer on a silicon wafer, a process of performing epitaxial growth on the silicon wafer on which the buried layer is formed, and a process of depositing the epitaxially grown wafer on a diamond point or the like. The process involves cutting the chips into chips several millimeters square with a cutting tool, attaching the chips to a polishing jig using wax, and performing angle polishing. After angle polishing, the chips are removed from the polishing jig and the wax is removed. The process of cleaning and stain etching to color the embedded layer to make it visible, the process of washing and drying to remove the stain etch solution, the surface pattern, and the process of coloring by stain etching. The process consisted of measuring the amount of pattern shift using a counter attached to a microscope.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の角度研磨法によるパターンシフ
ト量の測定方法では、測定結果が得られるまでに
3時間から5時間の長い時間を要しており、エピ
タキシヤル成長工程の量産ライン中に、測定結果
を早くフイードバツクできない欠点があつた。
The conventional method for measuring the amount of pattern shift using the angle polishing method described above takes a long time of 3 to 5 hours to obtain measurement results, and the measurement results are not available during the mass production line of the epitaxial growth process. There was a drawback that we could not get feedback quickly.

さらに、パターンシフト量をステンエツチ法で
行なうには、下地の埋込みパターンが、エピ成長
時の熱処理により、縦方向の拡散と同時に横方向
にも拡散が行なわれ、横方向の拡散分だけ誤差を
生じ、正確なパターンシフト量を求めるには不適
であるという欠点がある。
Furthermore, in order to adjust the pattern shift amount using the stainless etching method, the buried pattern in the base is diffused in the horizontal direction as well as in the vertical direction due to the heat treatment during epitaxial growth, resulting in an error due to the horizontal diffusion. , has the disadvantage that it is unsuitable for determining an accurate pattern shift amount.

本発明は、この欠点を解決すべくなされたもの
で、測定結果が得られるまでの時間を短縮し、次
回のエピタキシヤル成長までに測定結果をフイー
ドバツクし、さらに、埋込層の横方向拡散による
誤差を無くすパターンシフト量の測定方法を提供
するものである。
The present invention was made to solve this drawback, and it shortens the time it takes to obtain measurement results, feeds back the measurement results until the next epitaxial growth, and further improves the The present invention provides a method for measuring the amount of pattern shift that eliminates errors.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のパターンシフト量の測定方法は、シリ
コンウエハースに埋込み層を形成する第1の工程
と、埋込み層が形成されたシリコンウエハースの
一部にエピタキシヤル成長を行なう第2にの工程
と、エピタキシヤル成長した場所とエピタキシヤ
ル成長しない場所との間にある段差を挟んだ素子
間の距離を測定する第3の工程と、エピタキシヤ
ル成長しない場所の素子間の距離を測定する第4
の工程とを有し、前記第3、第4の工程で測定し
た2ケ所の距離からパターンシフト量を求めるこ
とを特徴とする方法である。
The method for measuring the amount of pattern shift of the present invention includes a first step of forming a buried layer on a silicon wafer, a second step of performing epitaxial growth on a part of the silicon wafer on which the buried layer is formed, and a second step of epitaxial growth. A third step is to measure the distance between elements across a step between a place where epitaxial growth has occurred and a place where no epitaxial growth has occurred, and a fourth step is to measure the distance between elements at a place where epitaxial growth has not been made.
This method is characterized in that the amount of pattern shift is determined from the distances at the two locations measured in the third and fourth steps.

〔実施例〕〔Example〕

次に本発明について図面を参照して詳細に説明
する。
Next, the present invention will be explained in detail with reference to the drawings.

第1図は、本発明の一実施例を説明するため
の、シリコンウエハースの断面の一部分を示した
原理図である。
FIG. 1 is a principle diagram showing a part of a cross section of a silicon wafer for explaining one embodiment of the present invention.

まず、従来から用いられている方法によつて、
シリコンサブストレート1の表面に埋込み形成面
4が形成されているシリコンウエハースを準備し
た。この時の埋込みパターン4の段差は、200Å
であつた。
First, by the conventional method,
A silicon wafer having a silicon substrate 1 and a embedding surface 4 formed thereon was prepared. The level difference of embedded pattern 4 at this time is 200 Å.
It was hot.

次に、シリコンエピタキシヤル成長装置のサセ
プター上に、前記埋込みパターンが形成されてい
るシリコンウエハースを置き、さらにこのシリコ
ンウエハース上の中央部分に石英板を置いてエピ
タキシヤル成長を行なつた。この時、100mmφの
シリコンウエハースの中央部に15mm×40mm厚さ
0.5mmの大きさの石英板を置いた。シリコンウエ
ハースの中央部に石英板を置くことによつて、シ
リコンウエハース内の石英板を置いた部分のエピ
タキシヤル成長を防止できる効果があり、シリコ
ンウエハースの一部分に未エピ成長面4を形成す
ることができ、この未エピ成長面4の表面にはエ
ピタキシヤル成長前の埋込みパターンが残され
る。
Next, the silicon wafer on which the buried pattern was formed was placed on a susceptor of a silicon epitaxial growth apparatus, and a quartz plate was placed in the center of the silicon wafer to perform epitaxial growth. At this time, a 15mm x 40mm thick piece was placed in the center of the 100mmφ silicon wafer.
A quartz plate with a size of 0.5 mm was placed. Placing the quartz plate in the center of the silicon wafer has the effect of preventing epitaxial growth in the part of the silicon wafer where the quartz plate is placed, and forms an un-epitaxially grown surface 4 in a part of the silicon wafer. A buried pattern before epitaxial growth is left on the surface of this non-epitaxially grown surface 4.

次に、エピタキシヤル成長層2と未エピ成長面
4のエピタキシヤル層厚さを測定し、石英板を置
いた未エピ成長面4には、エピタキシヤル成長さ
れていないことを確認した。さらに、石英板を置
いた以外の部分にあるエピタキシヤル成長層2に
は、所望の厚さである20μmのエピタキシヤル変
位層が形成されているのを確認した。
Next, the epitaxial layer thicknesses of the epitaxial growth layer 2 and the non-epitaxially grown surface 4 were measured, and it was confirmed that no epitaxial growth was made on the non-epitaxially grown surface 4 on which the quartz plate was placed. Furthermore, it was confirmed that an epitaxial displacement layer having a desired thickness of 20 μm was formed in the epitaxial growth layer 2 in the area other than where the quartz plate was placed.

次に、エピタキシヤル成長面3内のパターンか
ら未エピ成長面4内のパターンまでの距離6を精
密に測定し、さらに、未エピ成長面4内で前記で
測定したパターンと同一パターン間隔の距離7を
測定し、前記2ケ所の測定した距離6,7の差か
らパターンシフト量5を求めた結果、パターンシ
フト量は15μmであることが確認された。この測
定に要した時間は15分であり、従来の3〜5時間
の測定時間と比較すると大幅に測定時間が短縮さ
れていることを確認した。さらにこの時測定した
パターンシフト量5は、従来のステンエツチ法に
よるパターンシフト量と合つていることも確認し
た。
Next, the distance 6 from the pattern in the epitaxial growth surface 3 to the pattern in the non-epitaxially grown surface 4 is precisely measured, and the distance 6 in the non-epitaxially grown surface 4 with the same pattern spacing as the pattern measured above is further measured. 7 was measured, and the pattern shift amount 5 was determined from the difference between the distances 6 and 7 measured at the two locations. As a result, it was confirmed that the pattern shift amount was 15 μm. The time required for this measurement was 15 minutes, and it was confirmed that the measurement time was significantly shortened compared to the conventional measurement time of 3 to 5 hours. Furthermore, it was confirmed that the pattern shift amount 5 measured at this time matched the pattern shift amount obtained by the conventional stainless etching method.

次に、エピタキシヤル成長しない場所のパター
ン間の距離7が、埋込みパターン形成時に用いた
マスクパターンの距離と合つていることを確認し
た。このことは、エピタキシヤル成長時の熱処理
により、埋込み層の横方向拡散による誤差が発生
していないことの証明である。
Next, it was confirmed that the distance 7 between patterns in areas where epitaxial growth was not performed matched the distance of the mask pattern used when forming the buried pattern. This proves that no error occurs due to lateral diffusion of the buried layer due to the heat treatment during epitaxial growth.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、測定結果が得ら
れるまでの時間を大幅に短縮でき、測定結果が早
くフイードバツクできる効果をもたらし、さら
に、埋込層の横方向拡散による誤差も同時に防止
できる効果をもたらす。
As explained above, the present invention has the advantage of being able to significantly shorten the time it takes to obtain measurement results, allowing quick feedback of measurement results, and also being able to prevent errors due to lateral diffusion of the buried layer. bring.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の原理図である。 1…シリコンサブストレート、2…エピタキシ
ヤル成長層、3…エピタキシヤル成長面、4…埋
込み形成面(未エピ成長面)、5…パターンシフ
ト量、6…段差を挟んでパターン間の距離、7…
エピ成長しない場所のパターン間の距離。
FIG. 1 is a principle diagram of an embodiment of the present invention. 1... Silicon substrate, 2... Epitaxial growth layer, 3... Epitaxial growth surface, 4... Buried formation surface (non-epitaxially grown surface), 5... Pattern shift amount, 6... Distance between patterns across steps, 7 …
Distance between patterns where no epi growth occurs.

Claims (1)

【特許請求の範囲】[Claims] 1 シリコンウエハースに埋込み層を形成する第
1の工程と、埋込み層が形成されたシリコンウエ
ハースの一部にエピタキシヤル成長を行なう第2
の工程と、エピタキシヤル成長した場所とエピタ
キシヤル成長しない場所との間にある段差を挟ん
だ素子間の距離を測定する第3の工程と、エピタ
キシヤル成長しない場所の素子間の距離を測定す
る第4の工程とを有し、前記第3、第4の工程で
測定した2ケ所の距離の差からパターンシフト量
を求めることを特徴とするパターンシフト量の測
定方法。
1 A first step of forming a buried layer on a silicon wafer, and a second step of performing epitaxial growth on a part of the silicon wafer on which the buried layer has been formed.
a third step of measuring the distance between elements across a step between a place where epitaxial growth has occurred and a place where no epitaxial growth has occurred; and a third step of measuring the distance between elements at a place where epitaxial growth has not occurred. a fourth step, and determining the pattern shift amount from the difference in distance between the two locations measured in the third and fourth steps.
JP17450486A 1986-07-23 1986-07-23 Measuring method for quantity of pattern shifted Granted JPS6329943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17450486A JPS6329943A (en) 1986-07-23 1986-07-23 Measuring method for quantity of pattern shifted

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17450486A JPS6329943A (en) 1986-07-23 1986-07-23 Measuring method for quantity of pattern shifted

Publications (2)

Publication Number Publication Date
JPS6329943A JPS6329943A (en) 1988-02-08
JPH0528904B2 true JPH0528904B2 (en) 1993-04-27

Family

ID=15979657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17450486A Granted JPS6329943A (en) 1986-07-23 1986-07-23 Measuring method for quantity of pattern shifted

Country Status (1)

Country Link
JP (1) JPS6329943A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06103715B2 (en) * 1990-11-30 1994-12-14 信越半導体株式会社 Pattern shift measurement method
JP3039210B2 (en) * 1993-08-03 2000-05-08 日本電気株式会社 Method for manufacturing semiconductor device
CN107204283B (en) * 2016-03-18 2020-02-21 万国半导体股份有限公司 A method for monitoring epitaxial layer geometry drift

Also Published As

Publication number Publication date
JPS6329943A (en) 1988-02-08

Similar Documents

Publication Publication Date Title
US5665905A (en) Calibration standard for 2-D and 3-D profilometry in the sub-nanometer range and method of producing it
JPH0321901B2 (en)
JPH0528904B2 (en)
CN101465306A (en) Method for measuring distortion of epitaxial growth picture
JP2694115B2 (en) Calibration / measurement reference structure, method for forming the same, and measurement method using the same
JPH0724278B2 (en) Pattern shift measurement method
US5172188A (en) Pattern shift measuring method
JP2660405B2 (en) Mask alignment method
JPS60160124A (en) Manufacture of semiconductor device
JPH0236523A (en) Wafer alignment mark and formation thereof
JPH02206146A (en) Measurement of film thickness of semiconductor device
JP3024617B2 (en) Measurement method of position distortion and stress and X-ray mask
JPS60167426A (en) Semiconductor crystal wafer
EP0484665B1 (en) Pattern shift measuring method
JPH07251371A (en) Thin film forming polishing method and thin film forming polishing apparatus
JPS61251123A (en) Manufacture of semiconductor device
JPH081885B2 (en) Method of measuring pattern shift during epitaxial growth
JPS63265422A (en) Measurement of epitaxial growth layer
JPS61251124A (en) Manufacture of semiconductor device
JP2004079728A (en) Method for producing semiconductor integrated circuit
JPS61270819A (en) Manufacture of semiconductor device
JPS60145652A (en) Manufacture of semiconductor device
JPS6142152A (en) Alignment mark of semiconductor wafer
JPS61181123A (en) Matching method for position of pattern for semiconductor device
JPS6177337A (en) Manufacture of insulator isolation substrate

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees