JPH0529140B2 - - Google Patents
Info
- Publication number
- JPH0529140B2 JPH0529140B2 JP3695587A JP3695587A JPH0529140B2 JP H0529140 B2 JPH0529140 B2 JP H0529140B2 JP 3695587 A JP3695587 A JP 3695587A JP 3695587 A JP3695587 A JP 3695587A JP H0529140 B2 JPH0529140 B2 JP H0529140B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode terminal
- characteristic testing
- characteristic
- semiconductor substrate
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 description 19
- 239000000758 substrate Substances 0.000 description 11
- 239000000523 sample Substances 0.000 description 4
- 238000000605 extraction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に電極端子に接
続される外部導出用フイルムキヤリヤリードを支
持する導電性突起を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a conductive protrusion supporting a film carrier lead for external extraction connected to an electrode terminal.
従来、この種の半導体装置は、第4図に示すよ
うに、半導体基板1aの一主面の周辺部に外部導
出用フイルムキヤリヤリード(以下、リードと称
す)を接続するための複数の電極端子2及び3
と、同じ主面上に電極端子2及び3と半導体基板
1aの一端との間にリードを支えることによつて
リードと半導体基板1aの端部との電気的短絡を
防止するための、それぞれの電極端子2に対して
1個の導電性突起4とそれぞれの電極端子3に対
して2個の導電性突起5a及び5bとを有してい
る。
Conventionally, this type of semiconductor device, as shown in FIG. 4, has a plurality of film carrier leads (hereinafter referred to as "leads") for connecting to the outside on the periphery of one principal surface of the semiconductor substrate 1a . Electrode terminals 2 and 3
and for preventing an electrical short circuit between the lead and the end of the semiconductor substrate 1a by supporting the lead between the electrode terminals 2 and 3 and one end of the semiconductor substrate 1a on the same main surface. One conductive projection 4 is provided for each electrode terminal 2, and two conductive projections 5a and 5b are provided for each electrode terminal 3.
又、半導体基板1aの一主面の周辺の一部には
特性検査用素子8及び9と、特性検査用電極端子
15a,15b及び16a〜16cとを有している。 Further, in a part of the periphery of one main surface of the semiconductor substrate 1 a , there are characteristic testing elements 8 and 9 and characteristic testing electrode terminals 15 a , 15 b and 16 a to 16 c .
上述した従来の半導体装置は、特性検査用素子
の特性を検査するために特性検査用電極端子に検
査用探針を接触させることで検査を行うようにな
つているので、半導体基板の周辺の限られた領域
には、多数の特性検査用素子及び特性検査用電極
端子を配置することが出来ず、充分な特性検査が
実施できないという欠点がある。
In the above-mentioned conventional semiconductor device, the characteristics of the characteristic testing element are tested by bringing the testing probe into contact with the characteristic testing electrode terminal. There is a drawback that a large number of characteristic testing elements and characteristic testing electrode terminals cannot be arranged in the area where a sufficient characteristic testing cannot be carried out.
本発明は、半導体基板の一主面に設けた外部導
出用フイルムキヤリヤリードを接続する複数の電
極端子と、該電極端子と前記半導体基板の周辺と
の間にそれぞれの前記電極端子に少くとも1個設
けられた前記外部導出用フイルムキヤリヤリード
を支える複数の導電性突起とを備える半導体装置
において、前記電極端子と前記導電性突起とに接
続される特性検査用配線とを含んで構成される。
The present invention provides at least a plurality of electrode terminals for connecting a film carrier lead for external lead provided on one main surface of a semiconductor substrate, and a plurality of electrode terminals connected to each of the electrode terminals between the electrode terminals and the periphery of the semiconductor substrate. A semiconductor device comprising a plurality of conductive protrusions supporting one film carrier lead for external extraction, the semiconductor device comprising: the electrode terminal and a characteristic testing wiring connected to the conductive protrusion. Ru.
次に、本発明について図面を参照して説明す
る。
Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第1の実施例の平面図であ
る。 FIG. 1 is a plan view of a first embodiment of the invention.
第1図に示すように、半導体基板1の一主面の
周辺部にリードを接続するための複数の電極端子
2及び電源印加用のリードを接続するための複数
の電極端子3と、電極端子2及び3と半導体基板
1の一端との間にリードを支えるためのそれぞれ
の電極端子2に対して導電性突起4及びそれぞれ
の電極端子3に対して導電性突起5a,5bとを有
している。 As shown in FIG. 1, a plurality of electrode terminals 2 for connecting leads to a peripheral portion of one main surface of a semiconductor substrate 1, a plurality of electrode terminals 3 for connecting leads for power application, and an electrode terminal. 2 and 3 and one end of the semiconductor substrate 1, there are conductive protrusions 4 for each electrode terminal 2 and conductive protrusions 5 a and 5 b for each electrode terminal 3 for supporting a lead. are doing.
電極端子2と導電性突起4とはそれぞれ特性検
査用配線6a,6bにより特性検査用素子8に接続
され、電極端子3と導電性突起5a,5bはそれ
ぞれ特性検査用配線7a,7b,7cにより特性検
査用素子9に接続される。 The electrode terminal 2 and the conductive protrusion 4 are connected to the characteristic test element 8 by characteristic test wirings 6 a and 6 b , respectively, and the electrode terminal 3 and the conductive protrusions 5 a and 5 b are connected to the characteristic test wiring 7 a and 7, respectively. b and 7c are connected to the characteristic testing element 9.
第2図は特性検査状態の第1の実施例の側面図
である。 FIG. 2 is a side view of the first embodiment in a characteristic testing state.
第2図に示すように、電極端子2と導電性突起
4に特性検査用探針10,11を接触させること
により、特性検査用素子8の特性を検査すること
ができる。 As shown in FIG. 2, the characteristics of the characteristic testing element 8 can be tested by bringing the characteristic testing probes 10 and 11 into contact with the electrode terminal 2 and the conductive protrusion 4.
第3図は本発明の第2の実施例の平面図であ
る。 FIG. 3 is a plan view of a second embodiment of the invention.
第3図に示すように、電源印加用のリードを接
続する電極端子3には半導体基板1の内部に向か
つて伸びている電源配線12が接続されている。
導電性突起5aには電源配線12との接続点13
との間に電位検査用配線14が接続されている。 As shown in FIG. 3, a power wiring 12 extending toward the inside of the semiconductor substrate 1 is connected to an electrode terminal 3 to which a power supply lead is connected.
The conductive protrusion 5a has a connection point 13 with the power supply wiring 12.
A potential test wiring 14 is connected between the two.
ここで、上述した第2図と同様に、電極端子3
と導電性突起5aとの間に特性検査用探針を接触
させることにより電位検査用配線14と接続点1
3までの電源配線12との配線抵抗を測定でき
る。又、電極端子3へ電源を印加することによ
り、導電性突起5aで接続点13における電源配
線12の電位を測定できる。 Here, as in FIG. 2 described above, the electrode terminal 3
By bringing a characteristic testing probe into contact between the conductive protrusion 5a and the conductive protrusion 5a, the potential testing wiring 14 and the connection point 1 are connected.
Wiring resistance with up to 3 power supply wirings 12 can be measured. Furthermore, by applying power to the electrode terminal 3, the potential of the power supply wiring 12 at the connection point 13 can be measured using the conductive protrusion 5a.
以上説明したように本発明の半導体装置は、電
極端子及び導電性突起に特性検査用配線を接続す
ることにより、半導体基板の一部の限られた領域
に特別な特性検査用電極端子を設けることなく、
多種の特性検査を実施できるという効果がある。
As explained above, in the semiconductor device of the present invention, a special electrode terminal for characteristic testing can be provided in a limited area of a part of the semiconductor substrate by connecting the characteristic testing wiring to the electrode terminal and the conductive protrusion. Without,
This has the advantage that a wide variety of characteristic tests can be carried out.
第1図は本発明の第1の実施例の平面図、第2
図は特性検査状態の第1図の実施例の側面図、第
3図は本発明の第2の実施例の平面図、第4図は
従来の半導体装置の一例の平面図である。
1,1a…半導体基板、2,3…電極端子、
4,5a,5b…導電性突起、6a,6b,7a〜7c
…特性検査用配線、8,9…特性検査用素子、1
0,11…特性検査用探針、12…電源配線、1
3…接続点、14…電位検査用配線、15a,1
5b,16a〜16c…特性検査用電極端子。
FIG. 1 is a plan view of the first embodiment of the present invention;
The drawings are a side view of the embodiment of FIG. 1 in a characteristic testing state, FIG. 3 is a plan view of the second embodiment of the present invention, and FIG. 4 is a plan view of an example of a conventional semiconductor device. 1, 1a... Semiconductor substrate, 2, 3... Electrode terminal,
4, 5 a , 5 b ... conductive protrusion, 6 a , 6 b , 7 a to 7 c
... Wiring for characteristic testing, 8, 9... Element for characteristic testing, 1
0, 11...probe for characteristic inspection, 12...power supply wiring, 1
3... Connection point, 14... Potential test wiring, 15 a , 1
5b , 16a to 16c ...electrode terminals for characteristic testing.
1 内部にウエハその他のワークを収容する真空
室に、レーザ光をその外側から該ワークの表面に
向つて導かせる一側の導入窓と、該レーザ光が該
表面で鏡面反射するときこれをその外側に導かせ
る他側の導出窓とを備えると共に、該レーザ光が
該表面で乱反射するときこれを検出する検出器を
備えるものにおいて、該導出窓に施す窓ガラス
を、外方にのびると共にその外端面を傾斜面とす
る中空その他の筒体で構成して成る表面異物の検
出装置。
1 A vacuum chamber containing a wafer or other workpiece is provided with an introduction window on one side that guides laser light from the outside toward the surface of the workpiece, and an introduction window that guides the laser light from the surface when it is specularly reflected. The laser beam is provided with a window on the other side that guides the laser beam to the outside, and a detector that detects when the laser beam is diffusely reflected on the surface. A surface foreign object detection device consisting of a hollow or other cylindrical body with an inclined outer end surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3695587A JPS63204623A (en) | 1987-02-19 | 1987-02-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3695587A JPS63204623A (en) | 1987-02-19 | 1987-02-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63204623A JPS63204623A (en) | 1988-08-24 |
| JPH0529140B2 true JPH0529140B2 (en) | 1993-04-28 |
Family
ID=12484166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3695587A Granted JPS63204623A (en) | 1987-02-19 | 1987-02-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63204623A (en) |
-
1987
- 1987-02-19 JP JP3695587A patent/JPS63204623A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63204623A (en) | 1988-08-24 |
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